LTC1518IS

LTC1518/LTC1519 52Mbps Precision Delay RS485 Quad Line Receivers FEATURES s s s s s DESCRIPTIO s s s s s s s s s Precision Propagation Delay: 18.5ns ± 3.5ns Over 0°C to 70°C Temperature Range High Data Rate: 52Mbps Low tPLH/tPHL Skew: 500ps Typ Low Channel-to-Channel Skew: 500ps Typ Guaranteed Fail-Safe Operation over the Entire Common Mode Range –7V to 12V RS485 Input Common Mode Range Input Resistance ≥ 22k, Even When Unpowered Hot SwapTM Capable High Common Mode Rejection to 26MHz Short-Circuit Protection: 10mA Typ Output Current for an Indefinite Short Three-State Output Capability Will Not Oscillate with Slow Moving Input Signals Single 5V Supply Pin Compatible with LTC488, LTC489 The LTC®1518/LTC1519 are high speed, precision delay differential quad bus/line receivers that can operate at data rates as high as 52Mbps. They are pin compatible with the LTC488/LTC489 RS485 line receivers and operate over the entire – 7V to 12V common mode range. A unique architecture provides very stable propagation delays and low skew over wide input common mode, input overdrive and ambient temperature ranges. Propagation delay is 18.5ns ± 3.5ns over the commercial temperature range. Typical tPLH/tPHL and channel-to-channel skew is 500ps. Each receiver translates differential input levels (VID ≥ 300mV) into valid CMOS and TTL output levels. Its high input resistance (≥ 22k) allows many receivers to be connected to the same driver. The receiver outputs go into a high impedance state when disabled. The receivers have a fail-safe feature that guarantees a high output state when the inputs are shorted or left floating. Other protection features include thermal shutdown and a controlled maximum short-circuit current (50mA Max). Input resistance remains ≥ 22k when the device is unpowered or disabled, thus allowing hot swapping without loading the data lines. The LTC1518/LTC1519 operate from a single 5V supply and draw 12mA of supply current. APPLICATIO S s s s s s High Speed RS485/RS422 Receivers STS-1/OC-1 Data Receivers PECL Line Receivers Level Translators Fast-20/Fast-40 SCSI Receiver , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO RE 2 RO 1 7 DI 4 3 DE LTC1685 6 100Ω 4A1 12 3 RO 2B Propagation Delay Guaranteed to Fall Within Shaded Area (± 3.5ns) TA = 0°C TO 70°C RECEIVER INPUT VID = 1.5V RECEIVER OUTPUT VDD = 5V 52Mbps Data Communication over Twisted Pair RE 2 1 7 100Ω 4 6 3 DE DI RO VOUT = 5V/DIV VIN = 3V/DIV EN EN 1/4 LTC1518 LTC1685 1518/19 F08 –5 0 5 U 10 15 20 25 30 35 40 45 TIME (ns) 1518/19 TA02 U U 1 LTC1518/LTC1519 ABSOLUTE (Note 1) AXI U RATI GS Short-Circuit Duration .................................... Indefinite Operating Temperature Range LTC1518C/LTC1519C ............................. 0°C to 70°C LTC1518I/LTC1519I .......................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C Supply Voltage ....................................................... 10V Digital Input Currents ..................... – 100mA to 100mA Digital Input Voltages ............................... – 0.5V to 10V Receiver Input Voltages ........................................ ± 14V Receiver Output Voltages ............. – 0.5V to VDD + 0.5V Receiver Input Differential ....................................... 10V PACKAGE/ORDER I FOR ATIO TOP VIEW B1 1 A1 2 OUT 1 3 EN 4 OUT 2 5 A2 6 B2 7 GND 8 16 VDD 15 B4 14 A4 13 OUT 4 12 EN 11 OUT 3 10 A3 9 B3 ORDER PART NUMBER LTC1518CS LTC1518IS S PACKAGE 16-LEAD PLASTIC SO TJMAX = 150°C, θJA = 90°C/ W Consult factory for Military grade parts. DC ELECTRICAL CHARACTERISTICS SYMBOL VCM VIH VIL IIN1 IIN2 RIN CIN VOC VID(MIN) dVID VOH VOL IOZR IDD IOSR PARAMETER Input Common Mode Voltage Input High Voltage Input Low Voltage Input Current Input Current (A, B) Input Resistance Input Capacitance Open-Circuit Input Voltage Differential Input Threshold Voltage Input Hysteresis Output High Voltage Output Low Voltage Three-State Output Current Total Supply Current All 4 Receivers Short-Circuit Current A, B Inputs The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±5% (Notes 2, 3) per receiver, unless otherwise noted. CONDITIONS q q q q q q q EN, EN, EN12, EN34 EN, EN, EN12, EN34 EN, EN, EN12, EN34 VA, VB = 12V VA, VB = – 7V – 7V ≤ VCM ≤ 12V (Figure 5) (Note 4) VDD = 5V (Note 4) (Figure 5) – 7V ≤ VCM ≤ 12V VCM = 2.5V IOUT = – 4mA, VID = 0.3V, VDD = 5V IOUT = 4mA, VID = – 0.3V, VDD = 5V 0V < VOUT < 5V VOUT = 0V, VOUT = 5V (Note 7) VID > 0.3V, No Load, Device Enabled q q 2 U U W WW U W TOP VIEW B1 1 A1 2 OUT 1 3 EN12 4 OUT 2 5 A2 6 B2 7 GND 8 16 VDD 15 B4 14 A4 13 OUT 4 12 EN34 11 OUT 3 10 A3 9 B3 ORDER PART NUMBER LTC1519CS LTC1519IS S PACKAGE 16-LEAD PLASTIC SO TJMAX = 150°C, θJA = 90°C/ W MIN –7 2 TYP MAX 12 0.8 UNITS V V V µA µA µA kΩ pF –1 – 500 22 3 3.2 – 0.3 25 4.6 3.3 1 500 q q 3.4 0.3 V V mV V q q q 0.4 – 10 12 – 50 10 20 50 V µA mA mA LTC1518/LTC1519 DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Max VID for Fail-Safe Detection Min Time to Detect Fault Condition CMRR Common Mode Rejection Ratio VCM = 2.5V, f = 26MHz (Note 4) The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±5% (Notes 2, 3) per receiver, unless otherwise noted. CONDITIONS –7V ≤ VCM ≤ 12V MIN TYP 25 2 45 MAX UNITS mV µs dB SWITCHI G TI E CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ± 5% (Notes 2, 3) VID = 1.5V, VCM = 2.5V, unless otherwise noted. SYMBOL tPLH, tPHL tr, tf tSKD tZL tZH tLZ tHZ tCH-CH tPKG-PKG tr, tf Input PARAMETER Input-to-Output Propagation Delay Rise/Fall Times tPLH – tPHL Skew Enable to Output Low Enable to Output High Disable from Output Low Disable from Output High Channel-to-Channel Skew Package-to-Package Skew Maximum Input Rise or Fall Time Minimum Input Pulse Width fIN(MAX) Maximum Input Frequency Maximum Data Rate CL Load Capacitance Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into the device pins are positive; all currents out of the device pins are negative. Note 3: All typicals are given for VDD = 5V, TA = 25°C. Note 4: Guaranteed by design, but not tested. W U CONDITIONS CL = 15pF, 0°C ≤ TA ≤ 70°C (Figure 1) CL = 15pF, – 40°C ≤ TA ≤ 85°C (Figure 1) CL = 15pF CL = 15pF, Same Receiver (Note 5) CL = 15pF, 0°C ≤ TA ≤ 70°C (Figure 2) CL = 15pF, – 40°C ≤ TA ≤ 85°C (Figure 2) CL = 15pF, 0°C ≤ TA ≤ 70°C (Figure 2) CL = 15pF, – 40°C ≤ TA ≤ 85°C (Figure 2) CL = 15pF, 0°C ≤ TA ≤ 70°C (Figure 2) CL = 15pF, – 40°C ≤ TA ≤ 85°C (Figure 2) CL = 15pF, 0°C ≤ TA ≤ 70°C (Figure 2) CL = 15pF, – 40°C ≤ TA ≤ 85°C (Figure 2) CL = 15pF (Figure 3, Note 6) CL = 15pF, Same Temperature (Figure 4, Note 4) (Note 4) 0°C ≤ TA ≤ 70°C (Note 4) – 40°C ≤ TA ≤ 85°C (Note 4) Square Wave, 0°C ≤ TA ≤ 70°C (Note 4) Square Wave, – 40°C ≤ TA ≤ 85°C (Note 4) 0°C ≤ TA ≤ 70°C (Note 4) – 40°C ≤ TA ≤ 85°C (Note 4) (Note 4) q q q q q q q q q q q q q MIN 15 12 TYP 18.5 2.5 500 10 15 10 15 20 25 20 25 500 1.5 MAX 22 25 UNITS ns ns ns ps 35 35 35 35 ns ns ns ns ns ns ns ns ps ns 2000 12 16 26 20 52 40 40 30 80 65 500 19.2 25 ns ns ns MHz MHz Mbps Mbps pF Note 5: Worst-case tPLH – tPHL skew for a single receiver in a package over the full operating temperature range. Note 6: Maximum difference between any two tPLH or tPHL transitions in a single package over the full operating temperature range. Note 7: Short-circuit current does not represent output drive capability. When the output detects a short-circuit condition, output drive current is significantly reduced until the short is removed. 3 LTC1518/LTC1519 TYPICAL PERFOR A CE CHARACTERISTICS CMRR vs Frequency 46.5 COMMON MODE REJECTION RATIO (dB) 25 VCM = 2.5V VID = 1.5V PROPAGATION DELAY (ns) 46.0 45.5 45.0 44.5 44.0 43.5 43.0 42.5 42.0 10 1k 100k FREQUENCY (Hz) 10M 15189 G01 SUPPLY CURRENT (mA) TA = 25°C VCM = 2.5V Supply Current vs Temperature and Data Rate 30 VCM = 2.5V VID = 1.5V 25 1 RECEIVER SWITCHING 20 15 10 5 0 0 10 30 20 DATA RATE (Mbps) 40 50 15189 G04 PROPAGATION DELAY (ns) 20 15 10 5 0 5 15 25 35 55 105 LOAD CAPACITANCE (pF) 205 15189 G05 PROPAGATION DELAY (ns) SUPPLY CURRENT (mA) 100°C 25°C 0°C –25°C –50°C Propagation Delay vs Input Differential Voltage 25 TA = 25°C VCM = 2.5V PROPAGATION DELAY (ns) 20 DATA RATE (Mbps) 50 40 30 20 10 0 0.3 0.5 70 60 15 10 5 1.0 1.5 2.0 INPUT DIFFERENTIAL (V) 4 UW Propagation Delay (tPLH/tPHL) vs Temperature 50 45 40 35 30 25 20 15 10 5 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 Supply Current vs Data Rate TA = 25°C VCM = 2.5V VID = 1.5V 4 RECEIVERS SWITCHING 20 15 10 1 RECEIVER SWITCHING 5 0 0 10 30 20 DATA RATE (Mbps) 40 50 15189 G03 15189 G02 Propagation Delay vs Load Capacitance 30 25 TA = 25°C VCM = 2.5V VID = 1.5V Propagation Delay vs Common Mode 25 TA = 25°C VID = 1.5V 20 15 10 5 0 –6 –4 –2 8 0 4 6 2 COMMON MODE (V) 10 12 15189 G06 Maximum Data Rate vs Input Differential Voltage TA = 25°C VCM = 2.5V 2.5 15189 G07 0 0.3 0.5 1.0 1.5 2.0 INPUT DIFFERENTIAL (V) 2.5 15189 G08 LTC1518/LTC1519 PI FU CTIO S LTC1518 B1 (Pin 1): Receiver 1 Inverting Input. A1 (Pin 2): Receiver 1 Noninverting Input. OUT 1 (Pin 3): Receiver 1 Output. EN (Pin 4): A high enables all outputs; a low on Pin 4 and a high on Pin 12 will put all outputs into a high impedance state. Do not float. OUT 2 (Pin 5): Receiver 2 Output. A2 (Pin 6): Receiver 2 Noninverting Input. B2 (Pin 7): Receiver 2 Inverting Input. GND (Pin 8): Ground Pin. A ground plane is recommended for all LTC1518 applications. B3 (Pin 9): Receiver 3 Inverting Input. A3 (Pin 10): Receiver 3 Noninverting Input. OUT 3 (Pin 11): Receiver 3 Output. EN (Pin 12): A low enables all outputs; a low on Pin 4 and a high on Pin 12 will put all outputs into a high impedance state. Do not float. OUT 4 (Pin 13): Receiver 4 Output. A4 (Pin 14): Receiver 4 Noninverting Input. B4 (Pin 15): Receiver 4 Inverting Input. VDD (Pin 16): Power Supply Input. This pin should be decoupled with a 0.1µF ceramic capacitor as close as possible to the pin. Recommended: VDD = 5V ± 5%. U U U LTC1519 B1 (Pin 1): Receiver 1 Inverting Input. A1 (Pin 2): Receiver 1 Noninverting Input. OUT 1 (Pin 3): Receiver 1 Output. EN12 (Pin 4): A high enables receivers 1 and 2; a low will put the outputs of receivers 1 and 2 into a high impedance state. Do not float. OUT 2 (Pin 5): Receiver 2 Output. A2 (Pin 6): Receiver 2 Noninverting Input. B2 (Pin 7): Receiver 2 Inverting Input. GND (Pin 8): Ground Pin. A ground plane is recommended for all LTC1519 applications. B3 (Pin 9): Receiver 3 Inverting Input. A3 (Pin 10): Receiver 3 Noninverting Input. OUT 3 (Pin 11): Receiver 3 Output. EN34 (Pin 12): A high enables receivers 3 and 4; a low will put the outputs of receivers 3 and 4 into a high impedance state. Do not float. OUT 4 (Pin 13): Receiver 4 Output. A4 (Pin 14): Receiver 4 Noninverting Input. B4 (Pin 15): Receiver 4 Inverting Input. VDD (Pin 16): Power Supply Input. This pin should be decoupled with a 0.1µF ceramic capacitor as close as possible to the pin. Recommended: VDD = 5V ± 5%. 5 LTC1518/LTC1519 SWITCHI G TI E WAVEFOR S INPUT + – 1/4 LTC1518 LTC1519 OUTPUT 5V 15pF 1518/19 F01b 2.5V 4V INPUT t PLH OUTPUT VDD/2 2.5V 2.5V t PHL VDD/2 1518/19 F01 Figure 1. Propagation Delay Test Circuit and Waveforms INPUT A1, A2 CH1 OUT t CH-CH CH2 OUT Figure 3. Any Channel to Any Channel Skew, Same Package INPUT A1, B1 VID = 1.5V SAME INPUT FOR BOTH PACKAGES PACKAGE 1 OUT 1 t PKG-PKG PACKAGE 2 OUT 1 1518/19 F04 Figure 4. Package-to-Package Propagation Delay Skew 6 W 1V W U t r = t f ≤ 3ns for all input and enable signals. 3V ENABLE 0V t ZL 2.5V VOL VOH OUT 1 0V t ZH S1 RECEIVER OUTPUT CL 1k S2 1518/19 F02 1.5V 1.5V t LZ OUTPUT NORMALLY LOW 0.2V OUT 1 2.5V OUTPUT NORMALLY HIGH t HZ 1k VDD 0.2V Figure 2. Receiver Enable and Disable Timing Test Circuit and Waveforms 4V B1, B2 = 2.5V 1V VDD/2 VDD/2 t CH-CH VDD/2 VDD/2 1518/19 F03 tPKG-PKG LTC1518/LTC1519 EQUIVALE T I PUT NETWORKS ≥ 22k A ≥ 22k B 3.3V B 3.3V A ≥ 22k ≥ 22k APPLICATIO S I FOR ATIO Theory of Operation Unlike typical line receivers whose propagation delay can vary by as much as 500% from package to package and show significant temperature drift, the LTC1518/LTC1519 employ a novel architecture that produces a tightly controlled and temperature compensated propagation delay. The differential timing skew is also minimized between rising and falling output edges, and the propagation delays of any two receivers within a package are very tightly matched. The precision timing features of the LTC1518/LTC1519 reduce overall system timing constraints by providing a narrow ± 3.5ns window during which valid data appears at the receiver output. This output timing window applies to all receivers in all packages over the commercial operating temperature range, thereby making the LTC1518/LTC1519 well suited for high speed data transmission. In clocked data systems, the low skew minimizes duty cycle distortion of the clock signal. The LTC1518/LTC1519 can propagate signals at frequencies of 26MHz (52Mbps) with less than 5% duty cycle distortion. When a clock signal is used to retime parallel data, the maximum recommended data transmission rate is 25Mbps to avoid timing errors due to clock distortion. Thermal shutdown and short-circuit protection prevent latchup damage to the LTC1518/LTC1519 during fault conditions. U W UU UU RECEIVER ENABLED, VDD = 5V RECEIVER DISABLED OR VDD = 0V 1518/19 F05 Figure 5. Input Thevenin Equivalent Fail-Safe Features The LTC1518/LTC1519 have a fail-safe feature that guarantees the output to be in a logic HIGH state when the inputs are either shorted or left open (note that when inputs are left open, any external large leakage current might override the fail-safe). The fail-safe feature detects shorted inputs over the entire common mode range. When a fault is detected, the output will typically go high in 2µs. When some of the receivers within a package are not used, the open fail-safe feature will allow the user to let the receiver inputs float and maintain a high logic state at the output. Without the open fail-safe feature, any noise at the input would cause unwanted glitches at the output. When the inputs are left “open,” one must make sure that there are no sources of leakage current connected to one or both of the inputs. This can happen if the device is being driven single-endedly and both the signal and the DC bias are disconnected. If the capacitor used to bypass the DC bias is left connected to the input of the device and is leaky (>1µA), the output of the device might not be the desired high logic state. Also keep in mind that the inputs are high impedance (≥ 22kΩ). When left open, noisy traces should be kept away from the receiver inputs to minimize capacitive coupling of undesired signals. Even with the open fail-safe feature, for maximum noise immunity, grounding the negative input of unused receivers is recommended. 7 LTC1518/LTC1519 APPLICATIO S I FOR ATIO When the inputs are accidentally shorted (by cutting through a cable, for example), the short-circuit fail-safe feature will guarantee a high output logic level. Note also that if the line driver is removed and the termination resistors are left in place, the receiver will see this as a “short” and output a logic high. Both of these fail-safe features will keep the receiver from outputting false data pulses under fault conditions. Single-Ended Applications Over short distances, the LTC1518/LTC1519 can be configured to receive single-ended data by tying one input to a fixed bias voltage and connecting the other input to the driver output. In such applications, standard high speed CMOS logic may be used as a driver for the LTC1518/LTC1519. With a 22k minimum input resistance, the receiver trip points may be easily adjusted to MC74ACT04 (TTL INPUT) PC TRACE 5V MC74AC04 (CMOS INPUT) 0.01µF 2.2k – 1/4 LTC1518 LTC1519 + 2.2k 1518/19 F06a Figure 6a. Single-Ended Receiver MC74ACT04 (TTL INPUT) PC TRACE MC74AC04 (CMOS INPUT) 0.01µF Figure 6c. Self Biased Single Ended Receiver 8 U accommodate different driver output swings by changing the resistor divider at the fixed input. Figure 6a shows a single-ended receiver configuration with the driver and receiver connected via PC traces. Note that at very high speeds, transmission line and driver ringing effects must be considered. Motorola’s MECL System Design Handbook serves as an excellent reference for transmission line and termination effects. To mitigate transmission errors and duty cycle distortion due to driver ringing, a small output filter or a dampening resistor on the driver’s VDD may be needed as shown in Figure 6b. With an open circuit voltage of 3.3V at both inputs, the receivers can be used without an external bias applied to the fixed inputs. The fixed input should be bypassed with a 0.01µF ceramic capacitor. The positive input should be driven with a 5V CMOS part in order to minimize the skew caused by the 3.3V threshold. Figure 6c shows this configuration. MC74AC04 10Ω 10Ω PC TRACE 10pF 1518/19 F06b W UU 0.01µF PC TRACE OR Figure 6b. Techniques to Minimize Driver Ringing – 1/4 LTC1518 LTC1519 + 1518/19 F06c LTC1518/LTC1519 APPLICATIO S I FOR ATIO Note that due to the increased skew, this configuration might not operate at the highest data rates. To transmit single-ended data over short to medium distances, twisted pair is recommended with the unused wire grounded at both ends (Figure 7). 5V 100Ω 10-FT TWISTED PAIR 100Ω 5V 3.3k 0.01µF 1k 1518/19 F07 MC74ACT04 MC74AC04 Figure 7. Medium Distance Single-Ended Transmission Using a CMOS Driver RE 2 RO 1 7 DI 4 3 DE LTC1685 6 100Ω 4A1 12 3 RO 2B 1/4 LTC1518 100Ω 7 Figure 8. LTC1518 Connected to LTC1685 High Speed RS485 Transceiver U Differential Transmission Data rates up to 52Mbps can be transmitted over 100 feet of high quality category 5 twisted pair. Figure 8 shows the LTC1518 receiving differential data from an LTC1685 transceiver. As in the single-ended configurations, care must be taken to properly terminate the differential data lines to avoid unwanted reflections, etc. – + 1/4 LTC1518 LTC1519 W UU RE 2 1 RO 4 6 3 DE DI EN EN LTC1685 1518/19 F08 9 LTC1518/LTC1519 APPLICATIO S I FOR ATIO Figure 9 shows a trace with 100ft category 5 UTP between an LTC1685 driver and an LTC1518 receiver. Notice that at the far end of the cable, the signal to the LTC1518 input has been reduced. Figure 10 shows a 52Mbps square wave. Output Short-Circuit Protection The LTC1518/LTC1519 employ voltage sensing shortcircuit protection at the output terminals. For a given input differential, this circuitry determines what the correct 2V/DIV 2V/DIV 5V/DIV Figure 9. 20ns Pulse Propagating Down 100ft of Category 5 UTP 1V/DIV 5V/DIV Figure 10. 52Mbps Pulse Train Over 100ft of Category 5 UTP 10 U output level should be. For example, if the input differential is ≥ 300mV, it expects the output to be a logic high. If the output is subsequently shorted to a voltage below VDD/2, this circuitry shuts off the output devices and turns on a smaller device in its place. A timeout period of about 50ns is used in order to maintain normal high frequency operation, even under heavy capacitive loads (>100mA transient current into the load). CABLE DELAY DRIVER INPUT RECEIVER INPUT NOTES: TOP TRACE: LTC1685 DRIVER INPUT MID TRACE: LTC1518 INPUT AT FAR END OF 100ft CATAGORY 5 UTP BOTTOM TRACE: LTC1518 OUTPUT RECEIVER OUTPUT 50ns/DIV LTC1518/19 • F09 W UU RECEIVER INPUT NOTES: TOP TRACE: LTC1518 INPUT AT FAR END OF 100ft CAT 5 UTP BOTTOM TRACE: LTC1518 OUTPUT RECEIVER OUTPUT 20ns/DIV LTC1518/19 • F10 LTC1518/LTC1519 PACKAGE DESCRIPTIO 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.053 – 0.069 (1.346 – 1.752) 2 3 4 5 6 7 8 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP 0.050 (1.270) BSC S16 1098 11 LTC1518/LTC1519 TYPICAL APPLICATIO BACK PLANE VCC ON/RESET CONNECTOR 2 CONNECTOR 1 GND 16 4 3 8 16 4 3 LTC1518 1 6 7 10 9 14 15 8 + 2 RELATED PARTS PART NUMBER LTC486/LTC487 LTC488/LTC489 LT®1016 LTC1520 LTC1685/LTC1686/ LTC1687 LTC1688/LTC1689 DESCRIPTION Low Power Quad RS485 Drivers Low Power Quad RS485 Receivers UltraFastTM Precision Comparator High Speed, Precision Quad Differential Line Receiver High Speed, Precision RS485 Transceivers High Speed, RS485 Quad Drivers COMMENTS 10Mbps, – 7V to 12V Common Mode Range 10Mbps, – 7V to 12V Common Mode Range Single 5V Supply, 10ns Propagation Delay 50Mbps, ±100mV Threshold, Rail-to-Rail Common Mode 52Mbps, Pin Compatible with LTC485/490/491 100Mbps, Pin Compatible with LTC486/LTC487 UltraFast is a trademark of Linear Technology Corporation. 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com – 15 – – – – + 14 – 9 + 10 – 7 + DATA BUS 6 – 1 + 8 + + + U High Speed Receiver with Hot Swap Control PLUG-IN CARD R1 0.005Ω Q1 MTB56N06V + R2 10Ω 5% C1 0.1µF 5 µP RESET TIMER 3 C2 0.33µF GND 4 1 RESET R3 6.81k 1% R4 2.43k 1% VCC 5V 5A C4 2200µF 8 2 VCC ON 7 SENSE 6 GATE FB LTC1422 3.3k LTC1518 2 3.3k D7 0.1µF 5 D6 11 D5 13 D4 D3 5 D2 11 D1 13 D0 1518 TA03 15189fa LT/TP 0900 2K REV A • PRINTED IN THE USA © LINEAR TECHNOLOGY CORPORATION 1997