LTC1531

LTC1531 Self-Powered Isolated Comparator FEATURES s s s s s s s DESCRIPTIO UL Recognized File E151738 to UL1577 Self-Powered Across Isolation Barrier 2500VRMS Isolation 2.5V Isolated Reference, ILOAD = 5mAMAX Zero-Cross Output for Line Power Dual Differential Input Comparator High Input Impedance Comparator APPLICATIO S s s s s The LTC®1531 is an isolated self-powered dual differential comparator. An internal capacitive isolation barrier provides 2500VRMS of isolation between the comparator and its output. The part provides UL-rated isolated comparisons without the need for an isolated supply since both comparator power and output data are transmitted across the capacitive barrier. The comparator data is transferred differentially across the isolation barrier to provide high common mode voltage and noise immunity. The isolated side can supply a 2.5V reference output to power external sensor circuits such as a thermistor bridge. The dual differential comparator inputs allow for comparison of two differential voltages as well as single-ended voltages. The powered side provides a latched data output as well as a pulsed zero-cross comparator output for controlling a triac. The part is available in a 28-lead SO package. Self-Powered Isolated Sensing Isolated Temperature Control Isolated Voltage Monitor Isolated Switch Control , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION Isolated Thermistor Temperature Controller AC 120V LOAD 25Ω TECCOR Q4008L4 OR EQUIVALENT NEUTRAL 150Ω 1k 2N2222 1N4004 3k 3W R1 680k R2 47k C1 0.01µF ISOLATION BARRIER 750Ω 0.5W VCC ZCDATA SHDN ZCPOS ZCNEG + + 100µF 390Ω DATA QD DANGER! LETHAL VOLTAGES IN THIS SECTION! –5.6V 20µF 50V 5.6V VALID GND LTC1531 ISOGND 1 LED U + VPW 2.5V VREG V1 V2 V3 V4 CMPOUT R5*1M R6 22k 1 1 = ISOLATED GROUND *HYSTERESIS = 1°C AT TO 1 1531 TA01 U U RTHERM = 1µF RO • eB (1/T – 1/TO) B = 3807 TO = 297°K 1 THERM 30k YSI 44008 T + – R4 50k 1 LTC1531 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW VCC SHDN ZCNEG ZCPOS 1 2 3 4 28 GND 27 ZCDATA 26 DATA 25 VALID Total Supply Voltage (VCC to GND) ............................ 7V Input Voltages Isolated Comparator (V1 to V4) .............................. – 0.3V to (VPW + 0.3V) SHDN, ZCPOS, ZCNEG ......................... – 0.3V to 12V Current Input Pins ....................................................... ± 10mA ZCDATA, VALID, DATA .................................. ± 10mA Operating Temperature Range ..................... 0°C to 70°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1531CSW VPW 11 CMPOUT 12 VREG 13 ISOGND 14 18 V1 17 V2 16 V3 15 V4 SW PACKAGE 28-LEAD PLASTIC SO (ISO) TJMAX = 125°C, θJA = 125°C/ W Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL IVCC VZCOS VHYS f SAMPLE VOS RVIN IVIN VREG RVREG ICMPOUT tVREG VPWH IVPW VISO PARAMETER Supply Current Zero-Cross Offset Zero-Cross Hysteresis Isolated Comparator Sample Rate Isolated Comparator Offset Isolated Comparator Input Impedance Isolated Comparator Input Current VREG VREG Output Impedance CMPOUT High Impedance Leakage Current VREG On-Time VPW, Power Detect Enable Voltage Current Transfer to VPW Isolation Voltage The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, VCC = 5V. CONDITIONS SHDN = VCC, No Load SHDN = 0V VCM = VCC VCM = VCC (Note 7) VREG Not Loaded (Note 2) V1 = V2, V3 = V4 V1 – V3 = 2V, V4 – V2 = 2V V1 = V3 = 2.5V, V2 = V4 = 0V V1 = V2 = 1.25V, V3 = V4 = 0V V1 = V3 – 2.5V, V2 = V4 = 0V fSAMPLE = 700Hz (Note 4) 2mA Load VPW = 3.3V (Note 5) 2mA to 5mA Load VCMPOUT = 2.5V q q q q q q q q q MIN TYP 10 0.2 ± 30 200 300 2.0 2.0 18 300 ±1 MAX 14 10 ± 120 800 4.0 4.0 UNITS mA µA mV mV Hz mV mV MΩ MΩ nA 2.40 2.50 4 1 2.55 15 130 90 108 3.3 45 30 VPW = 0V VPW = 3.3V 1 Minute (Note 6) 1 Second q q 2500 4500 2 U W U U WW W V Ω nA µs V µA µA VRMS VDC LTC1531 ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, VCC = 5V. SYMBOL VIH VIL VOH VOL IINL, IINH dV/dt CISO Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The sample rate is not continuous, but depends on VPW charging rate. See Applications Information. Note 3: See Applications Information for further description of the comparator switched-capacitor input circuit. PARAMETER SHDN Input High Voltage SHDN Input Low Voltage DATA, VALID, ZCDATA Output High Voltage DATA, VALID, ZCDATA Output Low Voltage SHDN Low or High Level Input Current Continuous dV/dt Rejection CONDITIONS VCC = 4.5V VCC = 5.5V VCC = 4.5V, IO = – 400µA VCC = 4.5V, IO = 1.6mA VIN = 5V, 0V (Note 8) q q q q q q MIN 2.4 TYP MAX 0.8 UNITS V V V V µA V/µs pF 3.0 4.3 0.2 0.4 ±1 50 70 2 Note 4: The sample rate, fSAMPLE, varies with loading on VPW and VREG. Note 5: Load on CMPOUT pulls current from VREG when CMPOUT is high. Note 6: Value derived from 1 second test. Note 7: Zero-cross hysteresis is the minimum amount of signal amplitude above or below 0V differential to retrigger the zero-cross comparator. Note 8: Parameter not tested but guaranteed by design. TYPICAL PERFORMANCE CHARACTERISTICS VCC = 5V, CVPW = 1µF IVREG = 100µA, TA = 25°C 3.3 VCC = 5V CVPW = 1µF IVREG = 5mA TA = 25°C VPW VRIPPLE VPW (V) VREG VREG (V) 0 2.5 0 100 TIME (ms) NOTES: VRIPPLE DEPENDS ON CVPW AND IVPW + IVREG tSAMPLE DEPENDS ON IVPW + IVREG 1531 F01 Figure 1. VPW Power-Up and VREG Samples vs Time UW 200 3.3 tSAMPLE 2.5 300 0 10 20 30 TIME (ms) 40 NOTE: NONPERIODIC SAMPLES DUE TO DEPENDENCE ON VPW > 3.3V AND THE POWER-LISTEN CYCLE SAMPLING 1531 F02 Figure 2. VREG and VPW vs Time (IVREG = 100µA) 3 LTC1531 TYPICAL PERFORMANCE CHARACTERISTICS 30 TA = 25°C 25 VCC = 4.5V tSAMPLE (ms) 20 15 10 VCC = 5V 5 VCC = 5.5V VRMS 0 0 1 2 IVREG (mA) Figure 3. Average tSAMPLE vs IVREG PIN FUNCTIONS VCC (Pin 1): Powered Side Power Supply. SHDN (Pin 2): Active Low Chip Shutdown. A low signal causes the circuitry to power down. DATA logic output level will be reset to zero during power-down. ZCNEG (Pin 3): Zero-Cross Comparator Negative Input. ZCPOS (Pin 4): Zero-Cross Comparator Positive Input. VPW (Pin 11): Isolated Power Supply. Connect to an external storage capacitor. CMPOUT (Pin 12): Isolated Latched Comparator Data. CMPOUT is active when VREG is on. The CMPOUT output can be used on the isolated side for hysteresis (see applications). The output will contain the result of the previous comparison. When VREG is low, the CMPOUT pin is Hi-Z. VREG (Pin 13): Isolated 2.5V Regulated Output. Pulsed on for 100µs with a maximum load current of 5mA. VREG also supplies power to the CMPOUT output (Pin 12). ISOGND (Pin 14): Isolated Side Power Ground. V4 (Pin 15): Comparator Negative Input. The comparator inputs are summed together with the comparison output equal to (V1 + V2)/2 > (V3 + V4)/2 or equivalently (V1 – V3) > (V4 – V2). V3 (Pin 16): Comparator Negative Input. V2 (Pin 17): Comparator Positive Input. V1 (Pin 18): Comparator Positive Input. VALID (Pin 25): Pulsed Output. Indicates when valid data was received from the comparator. May be used to clock DATA to external circuitry. DATA (Pin 26): Latched Comparator Result. DATA holds the value of the last valid comparison result. DATA changes only when a valid comparison was received from the isolated side. ZCDATA (Pin 27): A 24µs to 30µs Pulsed Output. The pulse occurs when the DATA output is high and the zerocross comparator inputs (ZCPLS-ZCNEG) cross zero volts differential. Typically the zero-cross input signal is an RC phase shifted AC sine wave. This output is a TTL level pulse that can be used for firing an external triac. GND (Pin 28): Power Supply Low Impedance Ground Connection. 4 UW 4500V BREAKDOWN LIMIT 2500VRMS SLEW RATE = (π)(f)(VP-P) 450V = (1.11)(f)(VRMS) 50V/µs = V RMS (1.11)(f) 45V 4.5V 450mV 3 4 1531 F03 10k 10M 100k 1M FREQUENCY (Hz) 100M 1531 F04 Figure 4. VRMS vs Frequency U U U LTC1531 TI I G DIAGRA W POWER CYCLE 960µs LISTEN CYCLE 192µs LISTEN 108µs Hi-Z 200ns POWER VREG CMPOUT POWER-LISTEN CYCLE 1152µs 1531 TD01 BLOCK DIAGRAM POWERED SIDE VCC VCC 1 VOLTAGE PUMP VALID 25 TIMING DATA 26 QD R POWER-ON RESET ZCDATA 27 CMPOUT 12 ZERO-CROSS COMPARATOR GND 28 W UW VALID DATA ISOLATION BARRIER VPW 11 3.3V DET ISOLATED SIDE V1 18 TRANSMIT AND DRIVER + LATCH COMPARE Σ Σ V2 17 V3 16 V4 15 VREG 13 – + TIMING DECODE – 2.5V REG 4 3 2 SHDN 14 ISOGND 1531 BD ZCPOS ZCNEG 5 LTC1531 APPLICATIONS INFORMATION The LTC1531 is an isolated self-powered dual differential comparator. It contains a switched-capacitor comparator that is self-powered through a capacitive isolation barrier. The capacitive isolation barrier provides 2500VRMS of isolation. The isolated comparator cycles between storing power and performing sampled comparisons. During the power delivery cycle, the nonisolated powered side delivers power through the internal isolation capacitors and rectifier onto an external storage capacitor. Periodically the isolated comparator makes a comparison if sufficient voltage has been stored on the external supply capacitor. See Timing and Block Diagrams. During a comparison, the isolated side uses the energy stored on the external capacitor to deliver a regulated 2.5V power source for 108µs followed by a sampled comparison. The result is transmitted back to the nonisolated powered side and latched as the logic level DATA output. A comparison will occur during the listen cycle if sufficient voltage (3.3V) has been stored on the isolated external capacitor. New DATA is latched only if a comparison was actually done. A zero-crossing trigger pulse output for firing a triac, ZCDATA, is available to trigger a triac when the latched DATA output is high. A VALID data output pulse is provided after each power-listen cycle in which a comparison was done to indicate that DATA has been updated. The VALID output can be used to clock external circuitry when a new comparator DATA value occurs. POWER-LISTEN CYCLE Self-Powering Through the Isolation Barrier The LTC1531 comparator powered side toggles between delivering power to the isolated side and listening for a comparison result (see Timing Diagram). During the power cycle, AC power is delivered through the isolation capacitors, formed in the lead frame, to the isolated side. During the listen cycle, the powered side receives pulses from the isolated side and determines if a valid comparison occurred. The isolated side of the LTC1531 requires an external capacitor connected to VPW whose value must be large enough to sustain less than a 300mV drop for 108µs with the internal + external VREG load current. Power is delivered to this external capacitor through the internal isolation capacitors and rectifiers during the power cycle. When this voltage reaches approximately 3.3V, the compare circuitry is enabled and a comparison will occur during the next listen cycle. With VCC = 5V, this capacitive coupled isolated power source can be modeled as an equivalent 5.3V to 6.5V source with a 100kΩ source impedance. The VPW pin will tend to self-regulate at 3.3V with a ripple determined by the discharge current supplied during the 108µs VREG output pulse and the external capacitor value. The value of the capacitor affects the initial start-up time and the ripple voltage on VPW, but it does not influence the sample rate of the comparator. This is because the sample rate is determined by the rate of power delivered through the isolation barrier and the rate it is consumed in the internal plus external isolated circuits. Any excessive external DC loading on VPW may prevent the capacitor voltage from reaching the required 3.3V enable voltage. Up to 20µA of continuous loading on VPW can be tolerated based on the 100k, 5.3V model of the power source (see Typical Applications for examples). The quiescent current of the isolated side is approximately 2µA to 3µA. SAMPLE RATE The comparator sample rate depends on the charging rate through the isolated capacitors and the external + internal load current . The power-listen cycles at 700Hz to 900Hz, however, a comparison will only occur when VPW exceeds the 3.3V enable voltage. Typical sample rate for light loading is 200Hz to 300Hz. The actual sampling is not uniform, but occurs during the listen period of the power cycle and when VPW ≥ 3.3V. Typical sample rates for various supply and load conditions are plotted in Figure 3. Continuous micropower loads will also decrease the sample rate. VREG Reference Output The VREG reference output pulses on for approximately 108µs at 2.5V. During the off time, VREG does not go high impedance. The VREG output stage is shown in Figure 5. Large capacitance should not be attached to VREG in order to avoid power loss. Charging of the VREG output capaci- 6 U W U U LTC1531 APPLICATIONS INFORMATION VPW VPW VREG 21k VGP 2k 23k 16k 1 ISOGND 16k 1 ISOGND 1531 F05 Figure 5. VREG Output Stage tance, which will subsequently be discharged between samples, will consume power from VPW. ISOLATED COMPARATOR INPUTS AND CMPOUT The LTC1531 isolated comparator has a 4-input summing comparator that performs the following comparison: (V1 + V2)/2 > (V3 + V4)/2 By rearranging the equation, for example, a dual differential comparison is performed: (V1 – V4) > (V3 – V2) or (V1 – V3) > (V4 – V2) The input has a rail-to-rail input and common mode voltage range of VPW -ISOGND. The summing nature of the inputs allows midsupply referencing. For example, connecting V3 to VREG and V4 to ISOGND sums together to provide VREG/2 for the negative comparator input. See for example, the Isolated Switch Control. Charge injection and leakage currents occur at the comparator inputs. The amount depends on how the comparator is used. Minimum leakage currents occur with V1 = V2 and V3 = V4 where the input impedance is from charge injection and is nominally 300MΩ. When V1 ≠ V2 or U W U U V3 ≠ V4, the input impedance due to leakage currents is about 15MΩ to 20MΩ. Since the comparator is turned on only for the last 10µs of the 108µs VREG period, the charge injection occurs at about the 98µs point with a coupling capacitance of 2pF per input. The CMPOUT signal is typically used to provide hysteresis, as in the Isolated Temperature Control application. CMPOUT is the latched result of the previous comparison and is active during the following VREG ON period. CMPOUT is powered by VREG, the internal 2.5V regulated output, and is in high impedance except during the 108µs VREG ON time. When active, CMPOUT is switched low to ISOGND or high to VREG depending on the stored result of the previous comparison. The stored CMPOUT data is reset during power-up. CMPOUT is not necessarily reset by the powered side SHDN pin, except when shutdown results in VPW drooping low enough to trigger a power-on reset on the isolated side between 1.5V to 2.5V. DATA, VALID, ZCDATA During a power cycle, the VALID signal goes high if a valid comparison was made during the previous listen cycle. VALID goes low at the beginning of the next listen cycle. The low-to-high transition of VALID can be used to clock DATA into external circuitry. VALID is delayed 200ns after the DATA output. In order for a comparison to occur, sufficient power must be stored on the isolated side storage capacitor. The DATA output holds the last received compare result. DATA is reset to zero on power-up and shutdown. The VALID output is held high for one power cycle following a correctly received compare result. The received DATA value from the isolated side contains redundancy to improve noise immunity. The ZCDATA is a 25µs output pulse triggered by the zerocross comparator. In order for a pulse to occur, the DATA output must be at logic 1 and the ZCPOS-ZCNEG zerocross comparator input crosses 0V after the input has exceeded the ±150mV to 800mV of hysteresis. The zerocross comparator output is typically used to trigger a triac from a 60Hz RC phase shifted AC line signal. See Typical Applications. 7 LTC1531 APPLICATIONS INFORMATION The zero-cross comparator inputs, ZCPOS and ZCNEG, have an input common mode range that allows signal swings near the positive supply rails. The ZCPOS and ZCNEG inputs contain ESD diode protection devices which will clamp input signals that go below GND. The current into the diode should be limited to less than 5mA. The Isolated Thermistor Temperature Controller shows an example phase shift network with attenuation that satisfies these conditions. The positive input voltage should not exceed the 12V maximum rating or the 5mA input current to the ESD diode clamp. ISOLATION dV/dt The maximum continuous dV/dt across the isolation barrier that will still allow the isolated comparator to operate is 50V/µs. Continuous rates of dV/dt greater than this cause the isolated side to not detect when its power cycle has stopped and a comparison should begin. Figure 4 shows the maximum continuous rate trade-off of frequency vs voltage of a sine wave: SR = (π )(f)(VP-P) where SR = slew rate, VP-P = the peak-to-peak voltage and f = frequency. Noise immunity to intermittent dV/dt rates greater than 50V/µs can be rejected by the LTC1531. AC Noise Rejection and Things to Avoid Minimizing AC noise pickup at the isolated comparator should follow the following guidelines. 1. Allow the isolated side ground to float. The isolated side should only be common with the isolated circuit. 2. Use hysteresis to decrease sensitivity by using CMPOUT. 3. Use lower impedance circuits if powered by VREG. Avoid large capacitance tied directly to VREG output, since this output does not go Hi-Z (high impedance) during the off time. PC Board Layout The PC board layout should not have copper near the lead frame isolation capacitors. The copper reduces the power coupling and power delivery to the isolated side (see Figure 6). TOP VIEW VCC SHDN ZCNEG ZCPOS 1 2 3 4 28 GND 27 ZCDATA 26 DATA 25 VALID 8 U W U U ETCH COPPER FROM THE SHADED AREA VPW 11 CMPOUT 12 VREG 13 ISOGND 14 18 V1 17 V2 16 V3 15 V4 SW PACKAGE 28-LEAD PLASTIC SO (ISO) 1531 F06 Figure 6. PC Board Layout Consideration TYPICAL APPLICATIONS DESCRIPTION The Isolated Thermistor Temperature Controller (front page) uses a simple AC power rectifier and Zener to provide 5.6V of DC power to the LTC1531. To avoid power dissipation in the 3k, 3W resistor, DC power can be provided with a charge pump circuit similar to the Isolated Switch Control. In this circuit, a thermistor half bridge is used with the 4-input comparator connected to provide the other half of the bridge, V4 = 2.5V, V3 = 0V, giving (V4 + V3)/2 = 1.25V. With the 50k pot set to about 30k, the trip point is 25°C with a hysteresis of ± 0.5°C. Here, VREG turns on and powers the half-bridge while the comparator samples the result. The zero-cross comparator, ZCPOS and ZCNEG, is used to trigger a triac at the 10° phase point. The circuit, R1, R2 and C1, provides the phase shift, θ, as determined by: R2C1 ≅ tan(θ)/2π60Hz and where the attenuation ≅ R2/R1. In this example, R1 = 680k, R2 = 47k and C1 = 0.01µF, provide a 7V peak input signal with 10° of phase lag. LTC1531 APPLICATIONS INFORMATION The Remote Light-Controlled Switch (Figure 7) is similar to the Isolated Thermistor Temperature Controller. The thermistor is replaced with a Cadmium Light Sensor. The Isolated Switch Control (Figure 8) is also similar, where a low voltage switch is isolated from the AC power control. Here, a charge pump using the 1µF nonpolar capacitor and diodes are used for powering the LTC1531. The Isolated Voltage Sense circuit (Figure 9) uses the three-state CMPOUT pin in a delta-sigma configuration. Here, the time constant of R1C1 is increased by the effective duty cycle of CMPOUT ON to OFF time. At a 300Hz sample rate and a typical ON time of 108µs, the time constant is: (1M • 0.22µF)/(300Hz • 108µs) ≈ 6.6sec The input range is 0V to 2.5V set by the VREG output voltage. The output is recovered using a rail-to-rail op amp, LT1490, averaging circuit with a 10sec time constant. The output range is 0V to VCC output for a 0V to VREG input range. The Isolated Potentiometer Transducer Sense circuit (Figure 10) uses the same principle as the Isolated Voltage Sense circuit to provide a 0V to VCC output proportional to the potentiometer sensor input. The Isolated Thermocouple Voltage circuit (Figure 11) again uses the delta-sigma approach to translate a thermocouple temperature into a 0V to VCC output. Additionally, a micropower op amp, the LT1495, is used to provide a continuous voltage amplification of the thermocouple. The LT1389 with the thermistor bridge provides cold junction compensation over a 0°C to 60°C temperature range within ± 0.5°C. The op amp gain is set to give the Ktype thermocouple a 0°C to 200°C range which translates to a 0V to VCC output signal. Reducing R3 will increase the temperature sensing range. The Over Temperature Detect circuit (Figure 12) uses the same continuous micropower cold junction compensation circuit as in the Isolated Thermocouple Voltage circuit. In this case, the comparator’s minus input is set to 1.25V, which corresponds to 100°C as set by the LT1495 op amp gain. When the thermocouple exceeds 100°C, VTRIP goes high. The Isolated Battery Cell Monitor circuit (Figure 13) uses LTC1531 isolation to both float the individual grounds on the isolated comparator and isolate the battery from the logic outputs, CELL1, CELL2, ... In this application, R1 and R2 (R3 and R4) divide the 2.5V reference down to 0.89V, while the cell voltage is divided in half by connecting V1 to the cell and V2 to 0V. Hence, when the cell voltage drops below 1.786V, CELL1 goes high. Likewise for additional cells with additional LTC1531s. The Isolated Window Comparator circuit (Figure 14) uses two LTC1531s and a logic gate to provide isolated window comparisons. In this circuit, the first LTC1531, VHIGH, does the comparison: V1 – V3 > V4 – V2 or (0V – X • VREG) > (VIN– – VIN+) or X • VREG < (VIN+ – VIN–) where X = R2/(R2 + R1). The second LTC1531, VLOW, does the comparison: (–X • VREG) > (VIN+ – VIN–) When (VIN+ – VIN–) is less than –X • VREG, VLOW goes high and when (VIN+ – VIN–) is greater than X • VREG, VHIGH goes high. In between –X • VREG and +X • VREG, VWINDOW is high. Therefore, the window width is 2 • X • VREG. The AC Line Overcurrent Detect circuit (Figure 15) uses the micropower op amps, the quad LTC1496, to peak detect the voltage across a sense resistor in series with an AC load. The two amplifiers connected to RSENSE act as half-wave rectifiers because their outputs cannot swing below ground. The gain is set to trip when the voltage on RSENSE exceeds 125mV and the minus comparator input is set to 1.25V. The peak detector has a discharge resistor of 1M plus the op amp input bias current. U W U U 9 LTC1531 TYPICAL APPLICATIONS AC 120V TECCOR Q4008L4 OR EQUIVALENT NEUTRAL LOAD 25Ω 1N4004 3k 3W 750Ω 0.5W 150Ω 1k 2N2222 + DANGER! LETHAL VOLTAGES IN THIS SECTION! 20µF 50V AC 120V LOAD 25Ω TECCOR Q4008L4 OR EQUIVALENT NEUTRAL 150Ω 2N2222 10µF 50V 1µF 275V + 1k DANGER! LETHAL VOLTAGES IN THIS SECTION! 470Ω 2W 10 U R1 680k R2 47k C1 0.01µF ISOLATION BARRIER TRIAC FIRING: θ = DESIRED PHASE LAG R2 • C1 = Tan(θ)/(2π60Hz) R2/(R1 + R2) = ATTENUATION + VCC ZCDATA SHDN ZCPOS ZCNEG VPW 2.5V VREG V1 V2 5.6V DATA + QD – V4 CMPOUT LTC1531 ISOGND 1 1 1 2.2µF CADMIUM LIGHT SENSOR 100k + V3 100µF VALID GND HYSTERESIS 560k 1 = ISOLATED GROUND 100k 1 1531 F07 Figure 7. Remote Light-Controlled Switch R1 680k R2 47k 1N4004 390Ω LED ZCDATA C1 0.01µF ISOLATION BARRIER TRIAC FIRING: θ = DESIRED PHASE LAG R2 • C1 = Tan(θ)/(2π60Hz) R2/(R1 + R2) = ATTENUATION + VCC SHDN ZCPOS ZCNEG VPW 2.5V VREG V1 V2 DATA 5.6V QD + – V3 V4 100µF VALID GND LTC1531 ISOGND 1 CMPOUT 1 1µF 1M + LOW VOLTAGE SWITCH 1 1 1531 F08 1 = ISOLATED GROUND Figure 8. Isolated Switch Control LTC1531 TYPICAL APPLICATIONS R2 10M C2, 1µF VCC VOUT 0V TO VCC FULL-SCALE OUTPUT RESOLUTION = 4mV SETTLING TIME = 10sec 10k VCC ZCDATA R3 10M VCC VALID 10k GND LTC1531 SHDN ZCPOS LT1490 R2 10M C2, 1µF VCC VOUT 0V TO VCC FULL-SCALE OUTPUT RESOLUTION = 4mV SETTLING TIME = 10sec 10k 1 = ISOLATED GROUND = EQUIPMENT GROUND VCC ZCDATA R3 10M VCC VALID 10k GND LTC1531 ISOGND 1 + – SHDN ZCPOS ZCNEG VPW 2.5V VREG V1 V2 DATA QD V3 V4 LT1490 U VCC ISOLATION BARRIER + ZCNEG VPW 2.5V VREG V1 V2 DATA QD + – V3 V4 CMPOUT R1, 1M ISOGND 1 1 = ISOLATED GROUND = EQUIPMENT GROUND 1 2.2µF 0V TO 2.5V FULL-SCALE INPUT – + – + C1 0.22µF 1 1531 F09 DELTA-SIGMA TYPE MODULATION: CMPOUT IS ON 108µs AT ~300Hz RATE THEREFORE: 108µs • 300Hz = 1/30TH TIME CONSTANT = 1M • 30 • 0.22µF = 6.6sec Figure 9. Isolated Voltage Sense VCC ISOLATION BARRIER + 1 2.2µF 100k 1 CMPOUT R1, 1M C1 0.22µF 1 1531 TA05 DELTA-SIGMA TYPE MODULATION: CMPOUT IS ON 108µs AT ~300Hz RATE THEREFORE: 108µs • 300Hz = 1/30TH TIME CONSTANT = 1M • 30 • 0.22µF = 6.6sec Figure 10. Isolated Potentiometer Transducer Sense 11 LTC1531 TYPICAL APPLICATIONS R2 10M C2, 1µF VCC VCC ZCDATA 2.5V V1 + – VCC 10M VCC VALID 10k GND LTC1531 ISOGND 1 10k VTEMP OUTPUT = 0V TO VCC = 0°C TO 200°C RESOLUTION = 0.4mV OR 0.5°C RESPONSE TIME CONSTANT = 10sec DATA QD V3 1 VTEMP LT1490 Σ 1 V4 R1 1M COLD JUNCTION COMPENSATES 0°C TO 60°C C1 0.22µF 1 VPW CMPOUT LT1495 Figure 11. Isolated Thermocouple Voltage VPW 1M + VCC ISOLATION BARRIER 1 2.2µF 0.1µF LT1389 1 1.74M THERM 30k YSI44008 11.8k 10M VCC ZCDATA SHDN ZCPOS ZCNEG VPW 2.5V 10.2k V1 + – VTRIP DATA QD V3 1 VPW 1 VALID GND LTC1531 ISOGND 1 Σ 1 V4 LT1495 1 = ISOLATED GROUND = EQUIPMENT GROUND COLD JUNCTION COMPENSATES 0°C TO 60°C VTRIP SWITCHES AT 100°C, SET BY OP AMP GAIN Figure 12. Over Temperature Detect 12 – CMPOUT UNUSED OP AMP TIED FOR MIN CURRENT DRAIN 1 1531 F12 – + + Σ LT1495 V2 – VREG 33k 1.21k + 1 = ISOLATED GROUND = EQUIPMENT GROUND UNUSED OP AMP TIED FOR MIN CURRENT DRAIN 1531 F11 1 + K – – + Σ LT1495 V2 – U VPW 1M + ISOLATION BARRIER 1 2.2µF 0.1µF LT1389 1 1.74M THERM 30k YSI44008 11.8k K R3, 10M SHDN ZCPOS ZCNEG VPW 10.2k VREG 33k 1.21k – + + LTC1531 TYPICAL APPLICATIONS 5V VCC ZCDATA SHDN CELL 1 DATA VALID GND LTC1531 ISOGND VCC ZCDATA CELL 2 DATA VALID GND LTC1531 ISOGND U ISOLATION BARRIER + ZCPOS ZCNEG VPW 2.5V VREG V1 V2 + QD – V3 V4 CMPOUT 2.2µF TO OTHER CELLS R3 180k + R4 100k + SHDN ZCPOS ZCNEG VPW 2.5V VREG V1 V2 + QD – V3 V4 CMPOUT 2.2µF R1 180k VTRIP = 1.8V R2 100k + 1531 F13 TO OTHER CELLS Figure 13. Isolated Battery Cell Monitor 13 LTC1531 TYPICAL APPLICATIONS U 5V VCC ZCDATA SHDN ZCPOS ISOLATION BARRIER + ZCNEG VPW 2.5V VREG V1 V2 2.2µF VLOW DATA + QD – V3 V4 CMPOUT VALID GND LTC1531 (2) ISOGND + VIN – 1 VWINDOW VCC ZCDATA SHDN ZCPOS ZCNEG VPW 2.5V VREG V1 V2 VHIGH DATA + QD – V3 V4 VALID GND LTC1531 (1) ISOGND 1531 F14 + 2.2µF R1 400k WIDTH/2 R2 100k CMPOUT 1 = ISOLATED GROUND = EQUIPMENT GROUND 1 WINDOW WIDTH = 1V R1 = R2 (5/WIDTH – 1) Figure 14. Isolated Window Comparator 14 LTC1531 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline Isolation Barrier (Wide 0.300) (LTC DWG # 05-08-1690) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 18 17 16 15 NOTE 1 0.394 – 0.419 (10.007 – 10.643) 1 0.291 – 0.299** (7.391 – 7.595) 0.005 (0.127) RAD MIN 0.010 – 0.029 × 45° (0.254 – 0.737) 0.093 – 0.104 (2.362 – 2.642) 2 3 4 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.050 (1.270) BSC 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) SW28 (ISO) 1098 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1531 TYPICAL APPLICATION ISOLATION BARRIER VCC VCC ZCDATA SHDN ZCPOS ZCNEG VTRIP QD V4 VALID GND LTC1531 ISOGND CMPOUT 1M 2 2 NEGATIVE COMPARATOR INPUT SET TO 1.25V RSENSE IN SERIES WITH AC LINE RSENSE TRIP VOLTAGE = 125mV 2 = LIVE AC-CONNECTED LOCAL CIRCUIT COMMON = EQUIPMENT GROUND 1N4148 LT1496 0.22µF 2 VPW 2 1M 1M 1M 51k LT1496 DANGER! LETHAL VOLTAGES IN THIS SECTION! 2 Figure 15. AC Line Overcurrent Detect RELATED PARTS PART NUMBER LTC1177 LT1389 DESCRIPTION Isolated MOSFET Driver Nanopower Reference COMMENTS No Secondary Power Supply, 2500VRMS Isolation 800nA, 0.05% Accuracy, 10ppm/°C Max Drift 2.1µA Typ, 2V to 11V Supply, Adjustable Hysteresis Low Offset 375µVMAX, 2.2V to 36V Supply 0.3µA Typ, Adjustable Hysteresis, 2V to 11V Supply LTC1440/LTC1441 Ultralow Power Single/Dual Comparators with Reference LTC1442 LT1495/LT1496 LTC1540 1.5µA Max, Dual/Quad Precision Rail-to-Rail Input and Output Op Amps Nanopower Comparator with Reference 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com 1531f, sn1531 LT/TP 0899 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1998 + UNUSED OP AMP TIED FOR MIN CURRENT DRAIN LT1496 – + – – V3 LT1496 – DATA + – + U + VPW 2.5V VREG V1 V2 + 2 2.2µF 1M AC 51k RSENSE 10k 2 AC 10k 1531 F15