LTC1594LIS

LTC1594L/LTC1598L 4- and 8-Channel, 3V Micropower Sampling 12-Bit Serial I/O A/D Converters FEATURES s s s s s DESCRIPTIO s s s s s s 12-Bit Resolution on 3V Supply Low Supply Current: 160µA Typ Auto Shutdown to 1nA Guaranteed ± 3/4LSB Max DNL Guaranteed 2.7V Operation (5V Versions Available: LTC1594/LTC1598) Multiplexer: 4-Channel MUX (LTC1594L) 8-Channel MUX (LTC1598L) Separate MUX Output and ADC Input Pins MUX and ADC May Be Controlled Separately Sampling Rate: 10.5ksps I/O Compatible with QSPI, SPI and MICROWIRETM, etc. Small Package: 16-Pin Narrow SO (LTC1594L) 24-Pin SSOP (LTC1598L) The LTC ®1594L/LTC1598L are 3V micropower, 12-bit sampling A/D converters that feature 4- and 8-channel multiplexers, respectively. They typically draw only 160µA of supply current when converting and automatically power down to a typical supply current of 1nA between conversions. The LTC1594L is available in a 16-pin SO package and the LTC1598L is packaged in a 24-pin SSOP. Both operate on a 3V supply. The 12-bit, switchedcapacitor, successive approximation ADCs include a sample-and-hold. On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three or four wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. The circuit can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. APPLICATIO S s s s s s s Pen Screen Digitizing Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Battery Monitoring Temperature Measurement TYPICAL APPLICATION 12µW, 8-Channel, 12-Bit ADC Samples at 200Hz and Runs Off a 3V Supply OPTIONAL ADC FILTER 1k 1µF 18 MUXOUT 20 21 22 ANALOG INPUTS 0V TO 3V RANGE 23 24 1 2 3 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 8-CHANNEL MUX 12-BIT SAMPLING ADC CSADC CSMUX 10 6 5, 14 7 11 12 13 1 0.1 1594L/98L TA01 3V 17 ADCIN 16 15, 19 VREF VCC 1µF SERIAL DATA LINK MICROWIRE AND SPI COMPATABLE SUPPLY CURRENT (µA) + CLK DIN DOUT MPU – LTC1598L GND 4, 9 NC NC U Supply Current vs Sample Rate 1000 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 200kHz 100 10 1 10 SAMPLE FREQUENCY (kHz) 100 1594L/98L TA02 U U 1 LTC1594L/LTC1598L ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND ................................... 12V Voltage Analog Reference .................... – 0.3V to (VCC + 0.3V) Analog Inputs .......................... – 0.3V to (VCC + 0.3V) Digital Inputs .........................................– 0.3V to 12V Digital Output .......................... – 0.3V to (VCC + 0.3V) PACKAGE/ORDER INFORMATION ORDER PART NUMBER TOP VIEW CH0 1 CH1 2 CH2 3 CH3 4 ADCIN 5 VREF 6 COM 7 GND 8 16 VCC 15 MUXOUT 14 DIN 13 CSMUX 12 CLK 11 VCC 10 DOUT 9 CSADC TOP VIEW CH5 CH6 CH7 GND CLK CSMUX DIN COM GND 1 2 3 4 5 6 7 8 9 24 CH4 23 CH3 22 CH2 21 CH1 20 CH0 19 VCC 18 MUXOUT 17 ADCIN 16 VREF 15 VCC 14 CLK 13 NC LTC1594LCS LTC1594LIS S PACKAGE 16-LEAD PLASTIC SO TJMAX = 125°C, θJA = 120°C/ W Consult factory for Military grade parts. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL VCC fCLK tCYC thDI tsuCS tsuDI tWHCLK tWLCLK tWHCS tWLCS PARAMETER Supply Voltage (Note 3) Clock Frequency Total Cycle Time Hold Time, DIN After CLK↑ Setup Time CS↓ Before First CLK↑ (See Operating Sequence) Setup Time, DIN Stable Before CLK↑ CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer CONDITIONS VCC = 2.7V fCLK = 200kHz VCC = 2.7V VCC = 2.7V VCC = 2.7V VCC = 2.7V VCC = 2.7V fCLK = 200kHz fCLK = 200kHz MIN 2.7 (Note 4) 95 450 2 600 1.5 1.5 25 70 TYP MAX 3.6 200 UNITS V kHz µs ns µs ns µs µs µs µs RECOM ENDED OPERATING CONDITIONS 2 U U U U U W WW U W Power Dissipation .............................................. 500mW Operating Temperature Range LTC1594LCS/LTC1598LCG ..................... 0°C to 70°C LTC1594LIS/LTC1598LIG ................. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1598LCG LTC1598LIG CSADC 10 DOUT 11 NC 12 G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 110°C/ W U WW LTC1594L/LTC1598L CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error REF Input Range Analog Input Range MUX Channel Input Leakage Current MUXOUT Leakage Current ADCIN Input Leakage Current CONDITIONS q The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1594LCS/LTC1598LCG LTC1594LIS/LTC1598LIG MIN TYP MAX MIN TYP MAX 12 12 ±3 ±3 ± 3/4 ±1 ±3 ±3 ±8 ±8 1.5V to VCC + 0.05V – 0.05V to VCC + 0.05V ± 200 ± 200 ± 200 ± 200 ±1 ±1 UNITS Bits LSB LSB LSB LSB V V nA nA µA DYNAMIC ACCURACY SYMBOL S/(N + D) THD SFDR PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion (Up to 5th Harmonic) Spurious-Free Dynamic Range Peak Harmonic or Spurious Noise DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK RREF IREF PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Input Resistance Reference Current CONDITIONS VCC = 3.6V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10µA VCC = 2.7V, IO = 360µA VCC = 2.7V, IO = 400µA CS = High VOUT = 0V VOUT = VCC CS = VIH CS = VIL CS = VCC tCYC ≥ 760µs, fCLK ≤ 25kHz tCYC ≥ 60µs, fCLK ≤ 200kHz CS = VCC, CLK = VCC, DIN = VCC tCYC ≥ 760µs, fCLK ≤ 25kHz tCYC ≥ 60µs, fCLK ≤ 200kHz The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) q q q q q q q q ICC Supply Current WU U WU U (Note 6) q q q q (Notes 7, 8) (Notes 7, 8) Off Channel Off Channel (Note 9) q q q TA = 25°C, fSMPL = 10.5kHz. (Note 5) CONDITIONS 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal MIN TYP 68 – 78 80 – 80 MAX UNITS dB dB dB dB MIN 2.0 TYP MAX 0.8 2.5 – 2.5 2.4 2.1 2.64 2.30 0.4 ±3 – 10 15 2700 60 0.001 50 50 0.001 160 160 q q q q 2.5 70 ±3 320 UNITS V V µA µA V V V µA mA mA MΩ kΩ µA µA µA µA µA µA 3 LTC1594L/LTC1598L AC CHARACTERISTICS SYMBOL tSMPL fSMPL(MAX) tCONV tdDO tdis ten thDO tf tr tON tOFF tOPEN CIN PARAMETER Analog Input Sample Time Maximum Sampling Frequency Conversion Time Delay Time, CLK↓ to DOUT Data Valid Delay Time, CS↑ to DOUT Hi-Z Delay Time, CLK↓ to DOUT Enabled Time Output Data Remains Valid After CLK↓ DOUT Fall Time DOUT Rise Time Enable Turn-On Time Enable Turn-Off Time Break-Before-Make Interval Input Capacitance The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.(Note 5) CONDITIONS See Figure 1 in Applications Information See Figure 1 in Applications Information See Figure 1 in Applications Information See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits See Figure 1 in Applications Information See Figure 2 in Applications Information Analog Inputs On-Channel Off-Channel Digital Input MIN 1.5 10.5 TYP MAX UNITS CLK Cycles kHz CLK Cycles ns ns ns ns ns ns ns ns ns pF pF pF q q q q q q q q q 125 12 600 220 180 520 60 80 540 190 350 20 5 5 1500 600 500 180 180 1200 500 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: These devices are specified at 3V. Consult factory for 5V specified devices (LTC1594/LTC1598). Note 4: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 200kHz at 85°C, fCLK ≥ 75kHz at 70°C and fCLK ≥ 1kHz at 25°C. Note 5: VCC = 2.7V, VREF = 2.5V and CLK = 200kHz unless otherwise specified. CSADC and CSMUX pins are tied together during the test. Note 6: Linearity error is specified between the actual end points of the A/D transfer curve. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 2.7V ≤ VCC ≤ 3.6V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 3V input voltage range, it will therefore require a minimum supply voltage of 2.950V over initial tolerance, temperature variations and loading. Note 8: Recommended operating condition. Note 9: Channel leakage current is measured after the channel selection. TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Sample Rate 1000 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 200kHz 260 REFERENCE CURRENT (µA) SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 100 10 1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100 1594L/98L G01 4 UW Supply Current vs Temperature 53 Reference Current vs Temperature 52 51 50 49 48 47 46 45 44 VCC = 2.7V VREF = 2.5V fCLK = 200kHz fSMPL = 10.5kHz 220 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 200kHz fSMPL = 10.5kHz 180 140 100 60 – 55 – 35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1594L/98L G02 43 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1594L/98L G03 LTC1594L/LTC1598L TYPICAL PERFORMANCE CHARACTERISTICS Change in Offset vs Reference Voltage 3.0 CHANGE IN OFFSET (LSB = 1/4096 × VREF) CHANGE IN LINEARITY (LSB) 2.5 2.0 1.5 1.0 0.5 0 CHANGE IN OFFSET (LSB) TA = 25°C VCC = 2.7V fCLK = 200kHz fSMPL = 10.5kHz 0.5 1.0 1.5 2.0 2.5 REFERENCE VOLTAGE (V) Change in Gain vs Reference Voltage DIFFERENTIAL NONLINEARITY ERROR (LSB) –10 –9 –8 CHANGE IN GAIN (LSB) EFFECTIVE NUMBER OF BITS (ENOBs) TA = 25°C VCC = 2.7V fCLK = 200kHz fSMPL = 10.5kHz –7 –6 –5 –4 –3 –2 –1 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 REFERENCE VOLTAGE (V) 1594L/98L G07 Spurious Free Dynamic Range vs Input Frequency 100 SIGNAL-TO-NOISE PLUS DISTORTION (dB) SPURIOUS-FREE DYNAMIC RANGE (dB) 90 80 70 60 50 40 30 20 10 0 1 10 INPUT FREQUENCY (kHz) 100 1594L/98L G10 50 40 30 20 10 0 – 45 – 40 – 35 – 30 – 25 – 20 – 15 – 10 – 5 INPUT LEVEL (dB) 0 ATTENUATION (%) TA = 25°C VCC = 2.7V VREF = 2.5V fSMPL = fSMPL(MAX) UW 1594L/98L G04 Change in Offset vs Temperature 0.20 VCC = 2.7V 0.15 VREF = 2.5V fCLK = 200kHz 0.10 fSMPL = fSMPL(MAX) 0.05 0 – 0.05 – 0.10 – 0.15 – 0.20 3.0 0 10 20 50 40 30 TEMPERATURE (°C) 60 70 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 Change in Linearity vs Reference Voltage TA = 25°C VCC = 2.7V fCLK = 200kHz fSMPL = 10.5kHz 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 REFERENCE VOLTAGE (V) 1594L/98L G06 1594L/98L G05 Differential Nonlinearity vs Code 1 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 200kHz 12 11 10 9 8 7 6 5 4 3 2 1 0 Effective Bits and S/(N + D) vs Input Frequency 74 68 62 56 50 S/(N + D) (dB) 0.5 0 – 0.5 TA = 25°C VCC = 2.7V fCLK = 200kHz fSMPL = 10.5kHz 1 10 INPUT FREQUENCY (kHz) 100 1594L/98L G09 –1 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1594L/98L G08 S/(N + D) vs Input Level TA = 25°C 70 VCC = 2.7V VREF = 2.5V 60 fIN = 1kHz fSMPL = fSMPL(MAX) 80 0 10 20 30 40 50 60 70 80 90 100 Frequency Response (MUX + ADC) TA = 25°C VCC = 2.7V VREF = 2.5V fSMPL = fSMPL(MAX) 1k 100k 1M 10k INPUT FREQUENCY (Hz) 10M 1594L/98L G12 1594L/98/ G11 5 LTC1594L/LTC1598L TYPICAL PERFORMANCE CHARACTERISTICS 4096 Point FFT Plot 0 – 20 MAGNITUDE (dB) – 40 – 60 – 80 – 100 – 120 0 – 40 – 60 – 80 – 100 – 120 FEEDTHROUGH (dB) MAGNITUDE (dB) TA = 25°C VCC = 2.7V VREF = 2.5V fIN = 3.05kHz fCLK = 120kHz fSMPL = 7.5kHz 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (kHz) Maximum Clock Frequency vs Source Resistance 200 190 180 170 160 150 140 130 120 10 100 SOURCE RESISTANCE (Ω) 1000 1594L/98L G16 S & H ACQUISITION TIME (ns) CLOCK FREQUENCY (kHz) VIN +INPUT –INPUT RSOURCE– Minimum Clock Frequency for 0.1LSB Error vs Temperature 120 100 1000 VCC = 2.7V VREF = 2.5V 100 LEAKAGE CURRENT (nA) CLOCK FREQUENCY (kHz) 80 60 40 20 2 0 0 10 6 UW 3.5 Intermodulation Distortion 0 – 20 TA = 25°C VCC = 2.7V VREF = 2.5V f1 = 2.05kHz f2 = 3.05kHz fSMPL = 7.5kHz Power Supply Feedthrough vs Ripple Frequency 0 – 10 – 20 – 30 – 40 – 50 – 60 – 70 – 80 – 90 –100 TA = 25°C VCC = 2.7V (VRIPPLE = 1mV) VREF = 2.5V fCLK = 200kHz 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (kHz) 3.5 4.0 1k 100k 1M 10k RIPPLE FREQUENCY (Hz) 10M 1594L/98L G15 1594L/98L G13 1594L/98L G14 Sample-and-Hold Acquisition Time vs Source Resistance 10000 TA = 25°C VCC = 2.7V VREF = 2.5V TA = 25°C VCC = 2.7V VREF = 2.5V 1000 RSOURCE+ VIN +INPUT –INPUT 100 1 10 100 1000 SOURCE RESISTANCE (Ω) 10000 1594L/98L G17 Input Channel Leakage Current vs Temperature VCC = 2.7V VREF = 2.5V 10 1 ON CHANNEL OFF CHANNEL 0.1 20 50 40 TEMPERATURE (°C) 30 60 70 0.01 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1594L/98L G19 1594L/98L G18 LTC1594L/LTC1598L PIN FUNCTIONS LTC1594L CH0 (Pin 1): Analog Multiplexer Input. CH1 (Pin 2): Analog Multiplexer Input. CH2 (Pin 3): Analog Multiplexer Input. CH3 (Pin 4): Analog Multiplexer Input. ADCIN (Pin 5): ADC Input. This input is the positive analog input to the ADC. Connect this pin to MUXOUT for normal operation. VREF (Pin 6): Reference Input. The reference input defines the span of the ADC. COM (Pin 7): Negative Analog Input. This input is the negative analog input to the ADC and must be free of noise with respect to GND. GND (Pin 8): Analog Ground. GND should be tied directly to an analog ground plane. CSADC (Pin 9): ADC Chip Select Input. A logic high on this input powers down the ADC and three-states DOUT. A logic low on this input enables the ADC to sample the selected channel and start the conversion. For normal operation, drive this pin in parallel with CSMUX. DOUT (Pin 10): Digital Data Output. The A/D conversion result is shifted out of this output. VCC (Pin 11): Power Supply Voltage. This pin provides power to the ADC. It must be bypassed directly to the analog ground plane. CLK (Pin 12): Shift Clock. This clock synchronizes the serial data transfer to both MUX and ADC. CSMUX (Pin 13): MUX Chip Select Input. A logic high on this input allows the MUX to receive a channel address. A logic low enables the selected MUX channel and connects it to the MUXOUT pin for A/D conversion. For normal operation, drive this pin in parallel with CSADC. DIN (Pin 14): Digital Data Input. The multiplexer address is shifted into this input. MUXOUT (Pin 15): MUX Output. This pin is the output of the multiplexer. Tie to ADCIN for normal operation. VCC (Pin 16): Power Supply Voltage. This pin should be tied to Pin 11. LTC1598L CH5 (Pin 1): Analog Multiplexer Input. CH6 (Pin 2): Analog Multiplexer Input. CH7 (Pin 3): Analog Multiplexer Input. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CLK (Pin 5): Shift Clock. This clock synchronizes the serial data transfer to both MUX and ADC. It also determines the conversion speed of the ADC. CSMUX (Pin 6): MUX Chip Select Input. A logic high on this input allows the MUX to receive a channel address. A logic low enables the selected MUX channel and connects it to the MUXOUT pin for A/D conversion. For normal operation, drive this pin in parallel with CSADC. DIN (Pin 7): Digital Data Input. The multiplexer address is shifted into this input. COM (Pin 8): Negative Analog Input. This input is the negative analog input to the ADC and must be free of noise with respect to GND. GND (Pin 9): Analog Ground. GND should be tied directly to an analog ground plane. CSADC (Pin 10): ADC Chip Select Input. A logic high on this input deselects and powers down the ADC and threestates DOUT. A logic low on this input enables the ADC to sample the selected channel and start the conversion. For normal operation drive this pin in parallel with CSMUX. DOUT (Pin 11): Digital Data Output. The A/D conversion result is shifted out of this output. NC (Pin 12): No Connection. NC (Pin 13): No Connection. CLK (Pin 14): Shift Clock. This input should be tied to Pin 5. U U U 7 LTC1594L/LTC1598L PIN FUNCTIONS VCC (Pin 15): Power Supply Voltage. This pin provides power to the A/D Converter. It must be bypassed directly to the analog ground plane. VREF (Pin 16): Reference Input. The reference input defines the span of the ADC. ADCIN (Pin 17): ADC Input. This input is the positive analog input to the ADC. Connect this pin to MUXOUT for normal operation. MUXOUT (Pin 18): MUX Output. This pin is the output of the multiplexer. Tie to ADCIN for normal operation. VCC (Pin 19): Power Supply Voltage. This pin should be tied to Pin 15. CH0 (Pin 20): Analog Multiplexer Input. CH1 (Pin 21): Analog Multiplexer Input. CH2 (Pin 22): Analog Multiplexer Input. CH3 (Pin 23): Analog Multiplexer Input. CH4 (Pin 24): Analog Multiplexer Input. BLOCK DIAGRA S LTC1594L 15 LTC1594L 1 2 3 4 7 CH0 CH1 CH2 CH3 COM 4-CHANNEL MUX MUXOUT 5 ADCIN 6 16 TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf DOUT 100pF 8 W U U U LTC1598L 18 LTC1598L 9 13 12 14 10 17 ADCIN 16 15, 19 VREF VCC CSADC CSMUX MUXOUT VREF VCC 20 CH0 21 CH1 22 CH2 23 CH3 24 CH4 1 CH5 2 CH6 8-CHANNEL MUX 12-BIT SAMPLING ADC CSADC CSMUX 10 6 5, 14 7 11 12 13 + 12-BIT SAMPLING ADC CLK DIN DOUT – GND 8 + CLK DIN DOUT NC NC – 1594L BD 3 CH7 8 COM GND 4, 9 1598L BD 1.4V DOUT VOH VOL 3k TEST POINT tr tf 1594L/98L TC02 1594L/98L TC01 LTC1594L/LTC1598L TEST CIRCUITS Voltage Waveforms for DOUT Delay Times, tdDO Voltage Waveforms for ten LTC1594L/LTC1598L CLK VIL tdDO CSADC DOUT VOH VOL 1594L/98L TC03 CLK 1 2 B11 DOUT t en VOL 1594L/98L TC06 Load Circuit for tdis and ten TEST POINT CSADC = CSMUX = CS Voltage Waveforms for tdis VIH 3k DOUT 100pF VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1 1594L/98L TC04 DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2) 90% 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1594L/98L TC05 9 LTC1594L/LTC1598L APPLICATIONS INFORMATION OVERVIEW The LTC1594L/LTC1598L are 3V micropower, 12-bit sampling A/D converters that feature 4- and 8-channel multiplexers respectively. They typically draw only 160µA of supply current when sampling at 10.5kHz. Supply current drops linearly as the sample rate is reduced (see Supply Current vs Sample Rate). The ADCs automatically power down when not performing conversions, drawing only leakage current. The LTC1594L is available in a 16-pin narrow SO package and the LTC1598L is packaged in a 24-pin SSOP. Both devices operate on a single supply from 2.7V to 3.6V. The LTC1594L/LTC1598L contain a 12-bit, switchedcapacitor ADC, sample-and-hold, serial port and an external reference input pin. In addition, the LTC1594L has a 4-channel multiplexer and the LTC1598L provides an 8-channel multiplexer (see Block Diagram). They can measure signals floating on a DC common mode voltage and can operate with reduced spans to 1.5V. Reducing the spans allow them to achieve 366µV resolution. The LTC1594L/LTC1598L provide separate MUX output and ADC input pins to form an ideal MUXOUT/ADCIN loop which economizes signal conditioning. The MUX and ADC of the devices can also be controlled individually through separate chip selects to enhance flexibility. SERIAL INTERFACE For this discussion, we will assume that CSMUX and CSADC are tied together and will refer to them as simply CS, unless otherwise specified. The LTC1594L/LTC1598L communicate with the microprocessor and other external circuitry via a synchronous, half duplex, 4-wire interface (see Operating Sequences in Figures 1 and 2). CSMUX = CSADC = CS tsuCS CLK EN DIN D2 DOUT D1 DON’T CARE D0 Hi-Z tSMPL NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z CH0 TO CH7 tON ADCIN = MUXOUT COM = GND *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY Figure 1. LTC1594L/LTC1598L Operating Sequence Example: CH2, GND 10 U W U U tCYC tCONV 1594F/98F F01 LTC1594L/LTC1598L APPLICATIONS INFORMATION tCYC CSMUX = CSADC = CS tsuCS CLK EN DIN D2 DOUT D1 D0N‘T CARE D0 Hi-Z NULL BIT DUMMY CONVERSION tCONV Hi-Z CH0 TO CH7 tOFF ADCIN = MUXOUT COM = GND 1594L/98L F02 Figure 2. LTC1594L/LTC1598L Operating Sequence Example: All Channels Off Data Transfer The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1594L/LTC1598L first receive input data and then transmit back the A/D conversion results (half duplex). Because of the half duplex operation, DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a rising chip select (CS) signal. After CS rises, the input data on the DIN pin is latched into a 4-bit register on the rising edge of the clock. More than four input bits can be sent to the DIN pin without problems, but only the last four bits clocked in before CS falls will be stored into the 4-bit register. This 4-bit input data word will select the channel in the muliplexer (see Input Data Word and Tables 1 and 2). To ensure correct operation, the CS must be pulled low before the next rising edge of the clock. Once the CS is pulled low, all channels are simultaneously switched off after a delay of tOFF to ensure a U W U U break-before-make interval, tOPEN. After a delay of tON (tOFF + tOPEN), the selected channel is switched on, allowing the ADC in the chip to acquire input signal and start the conversion (see Figures 1 and 2). After 1 null bit, the result of the conversion is output on the DOUT line. The selected channel remains on, until the next falling edge of CS. At the end of the data exchange, CS should be brought high. This resets the LTC1594L/LTC1598L and initiates the next data exchange. CS DIN1 DOUT1 SHIFT MUX ADDRESS IN tSMPL + 1 NULL BIT DIN2 DOUT2 SHIFT A/D CONVERSION RESULT OUT 1594L/98L AI01 Break-Before-Make The LTC1594L/LTC1598L provide a break-before-make interval from switching off all the channels simultaneously to switching on the next selected channel once CS is pulled low. In other words, once CS is pulled low, 11 LTC1594L/LTC1598L APPLICATIONS INFORMATION after a delay of tOFF, all the channels are switched off to ensure a break-before-make interval. After this interval, the selected channel is switched on allowing signal transmission. The selected channel remains on until the next falling edge of CS and the process repeats itself with the “EN” bit being logic high. If the “EN” bit is logic low, all the channels are switched off simultaneously after a delay of tOFF from CS being pulled low and all the channels remain off until the next falling edge of CS. Input Data Word When CS is high, the LTC1594L/LTC1598L clock data into the DIN inputs on the rising edge of the clock and store the data into a 4-bit register. The input data words are defined as follows: EN D2 D1 D0 CHANNEL SELECTION 1594L/98L AI02 “EN” Bit The first bit in the 4-bit register is an “EN” bit. If the “EN” bit is a logic high, as illustrated in Figure 1, it enables the selected channel after a delay of tON when the CS is pulled low. If the “EN” bit is logic low, as illustrated in Figure 2, it disables all channels after a delay of tOFF when the CS is pulled low. Multiplexer (MUX) Address The 3 bits of input word following the “EN” bit select the channel in the MUX for the requested conversion. For a given channel selection, the converter will measure the voltage of the selected channel with respect to the voltage on the COM pin. Tables 1 and 2 show the various bit combinations for the LTC1594L/LTC1598L channel selection. Table 1. Logic Table for the LTC1594L Channel Selection CHANNEL STATUS All Off CH0 CH1 CH2 CH3 EN 0 1 1 1 1 D2 X 0 0 0 0 D1 X 0 0 1 1 DO X 0 1 0 1 12 U W U U Table 2. Logic Table for the LTC1598L Channel Selection CHANNEL STATUS All Off CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 EN 0 1 1 1 1 1 1 1 1 D2 X 0 0 0 0 1 1 1 1 D1 X 0 0 1 1 0 0 1 1 DO X 0 1 0 1 0 1 0 1 Transfer Curve The LTC1594L/LTC1598L are permanently configured for unipolar only. The input span and code assignment for this conversion type is illustrated below. Transfer Curve 111111111111 111111111110 • • • 000000000001 000000000000 VIN OUTPUT CODE 11111111111111 11111111111110 • • • 00000000000001 00000000000000 0V 1LSB VREF–1LSB VREF VREF–2LSB 1LSB = VREF 4096 1594L/98L • AI03 Output Code INPUT VOLTAGE VREF – 1LSB VREF – 2LSB • • • 1LSB 0V INPUT VOLTAGE (VREF = 2.500V) 2.49939V 2.49878V • • • 0.00061V 0V 1594L/98L • AI04 LTC1594L/LTC1598L APPLICATIONS INFORMATION Operation with DIN and DOUT Tied Together The LTC1594L/LTC1598L can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1594L/LTC1598L will take control of the data line after CS falling and before the 6th falling CLK while the processor takes control of the data line when CS is high (see Figure 3). Therefore the processor port line must be switched to an input with CS being low to avoid a conflict. Separate Chip Selects for MUX and ADC The LTC1594L/LTC1598L provide separate chip selects, CSMUX and CSADC, to control MUX and ADC separately. This feature not only provides the flexibility to select a particular channel once for multiple conversions (see Figure 4) but also maximizes the sample rate up to 20ksps (see Figure 5). tsuCS CS 1 CLK 2 DATA (DIN/DOUT) EN D2 D1 MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1594L/LTC1598L PROCESSOR MUST RELEASE DATA LINE AFTER CS FALLING AND BEFORE THE 6TH FALLING CLK Figure 3. LTC1594L/LTC1598L Operation with DIN and DOUT Tied Together CSMUX CSADC tsuCS CLK EN DIN D2 DOUT Hi-Z tSMPL CH0 TO CH7 tON ADCIN = MUXOUT 1594L/98L F04 D1 DON’T CARE D0 NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 D0 Hi-Z tSMPL NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z DON’T CARE tCONV COM = GND Figure 4. Selecting a Channel Once for Multiple Conversions U 3 W U U 4 5 6 D0 B11 B10 ••• LTC1594L/LTC1598L CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU LTC1594L/LTC1598L TAKES CONTROL OF DATA LINE AFTER CS FALLING AND BEFORE THE 6TH FALLING CLK 1594L/98L F03 tsuCS tCONV 13 LTC1594L/LTC1598L APPLICATIONS INFORMATION CSADC CSMUX tsuCS CLK EN DIN D2 DOUT B4 B3 B2 B1 B0 tSMPL CH0 TO CH7 tON ADCIN = MUXOUT 1594L/98L F05 D1 DON’T CARE D0 NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 tCONV COM = GND Figure 5. Use Separate Chip Selects to Maximize Sample Rate MUXOUT/ADCIN Loop Economizes Signal Conditioning The MUXOUT and ADCIN pins of the LTC1594L/LTC1598L form a very flexible external loop that allows Programmable Gain Amplifier (PGA) and/or processing analog input signals prior to conversion. This loop is also a cost effective way to perform the conditioning, because only one circuit is needed instead of one for each channel. In the Typical Applications section, there are a few examples illustrating how to use the MUXOUT/ADCIN loop to form a PGA and to antialias filter several analog inputs. ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 160µA and automatic shutdown between conversions, the LTC1594L/ LTC1598L achieve extremely low power consumption over a wide range of sample rates (see Figure 6). The auto shutdown allows the supply current to drop with reduced sample rate. Several things must be taken into account to achieve such a low power consumption. Shutdown The LTC1594L/LTC1598L are equipped with automatic shutdown features. They draw power when the CS pin is low. The bias circuits and comparator of the ADC powers down and the reference input becomes high impedance at the end of each conversion leaving the CLK running to clock out the LSB first data or zeroes (see Figures 1 and 2). When the CS pin is high, the ADC powers down completely SUPPLY CURRENT (µA) 14 U W U U tsuCS EN D2 B2 B1 D1 DON’T CARE D0 B0 tSMPL NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 EN D2 B2 B1 D1 D0 B0 tCONV tON 1000 TA = 25°C VCC = 2.7V VREF = 2.5V fCLK = 200kHz 100 10 1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100 1594L/98L G01 Figure 6. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate leaving the CLK running to clock the input data word into MUX. If the CS, DIN and CLK are not running rail-to-rail, the input logic buffers will draw currents. These currents may be large compared to the typical supply current. To obtain the lowest supply current, run the CS, DIN and CLK pins rail-to-rail. DOUT Loading Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the DOUT pin can add more than 50µA to the supply current at a 200kHz clock frequency. An extra 50µA or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The (C)(V)(f) currents must be evaluated and the troublesome ones minimized. LTC1594L/LTC1598L APPLICATIONS INFORMATION BOARD LAYOUT CONSIDERATIONS Grounding and Bypassing The LTC1594L/LTC1598L are easy to use if some care is taken. They should be used with an analog ground plane and single point grounding techniques. The GND pin should be tied directly to the ground plane. The VCC pin should be bypassed to the ground plane with a 10µF tantalum capacitor with leads as short as possible. If the power supply is clean, the LTC1594L/LTC1598L can also operate with smaller 1µF or less surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. SAMPLE-AND-HOLD Both the LTC1594L/LTC1598L provide a built-in sampleand-hold (S&H) function to acquire signals through the selected channel, assuming the ADCIN and MUXOUT pins are tied together. The S & H of these parts acquire input signals through the selected channel relative to COM input during the tSMPL time (see Figure 7). Single-Ended Inputs The sample-and-hold of the LTC1594L/LTC1598L allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins after tON time once the CS is pulled low and continues until the second falling CLK edge after the CS is low (see Figure 7). On this falling CLK SAMPLE “ANALOG” INPUT MUST SETTLE DURING THIS TIME tSMPL tCONV HOLD CSADC = CSMUX = CS CLK DIN EN D2 DOUT 1ST BIT TEST “COM” INPUT MUST SETTLE DURING THIS TIME MUXOUT = ADCIN CH0 TO CH7 COM 1594L/98L F07 Figure 7. LTC1594L/LTC1598L ADCIN and COM Input Settling Windows U W U U tON D1 D0 DON‘T CARE B11 15 LTC1594L/LTC1598L APPLICATIONS INFORMATION edge, the S & H goes into hold mode and the conversion begins. The voltage on the “COM” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the conversion operation may not be performed accurately. The conversion time is 12 CLK cycles. Therefore, a change in the “COM” input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the “COM” input this error would be: VERROR(MAX) = VPEAK(2π)(f)(“COM”)12/fCLK Where f(“COM”) is the frequency of the “COM” input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. In most cases, VERROR will not be significant. For a 60Hz signal on the “COM” input to generate a 0.5LSB error (305µV) with the converter running at CLK = 200kHz, its peak value would have to be 5.266mV. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1594L/ LTC1598L have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. “Analog” Input Settling The input capacitor of the LTC1594L/LTC1598L is switched onto the selected channel input during the tSMPL time (see Figure 7) and samples the input signal within that time. The sample phase is at least 1 1/2 CLK cycles before conversion starts. The voltage on the “analog” input must settle completely within tSMPL. Minimizing RSOURCE+ and C1 will improve the input settling time. If a large “analog” input source resistance must be used, the sample time can be increased by using a slower CLK frequency. “COM” Input Settling At the end of the tSMPL, the input capacitor switches to the “COM” input and conversion starts (see Figures 1 and 7). During the conversion, the “analog” input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result. However, it is critical that the “COM” input voltage settles completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE– and C2 will improve settling time. If a large “COM” input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 7). Again, the “analog” and “COM” input sampling times can be extended as described above to accommodate slower op amps. Most op amps, including the LT ®1006 and LT1413 single supply op amps, can be made to settle well even with the minimum settling windows of 7.5µs (“analog” input) which occur at the maximum clock rate of 200kHz. Source Resistance The analog inputs of the LTC1594L/LTC1598L look like a 20pF capacitor (CIN) in series with a 1k resistor (RON) and a 90Ω channel resistance as shown in Figure 8. CIN gets switched between the selected “analog” and “COM” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. MUX “ANALOG” R ON RSOURCE + INPUT 90Ω VIN + C1 “COM” INPUT MUXOUT ADCIN 16 U W U U LTC1594L RON LTC1598L 1k CIN 20pF RSOURCE – VIN – C2 1594L/98L F08 Figure 8. Analog Input Equivalent Circuit LTC1594L/LTC1598L APPLICATIONS INFORMATION Input Leakage Current Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 200nA (at 85°C) flowing through a source resistance of 600Ω will cause a voltage drop of 120µV or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve Input Channel Leakage Current vs Temperature). REFERENCE INPUTS The reference input of the LTC1594L/LTC1598L is effectively a 50k resistor from the time CS goes low to the end of the conversion. The reference input becomes a high impedance node at any other time (see Figure 9). Since the voltage on the reference input defines the voltage span of the A/D converter, the reference input should be driven by a reference with low ROUT (ex. LT1004, LT1019 and LT1021) or a voltage source with low ROUT. REF+ 1 ROUT VREF GND 4 1594L/98L F09 LTC1594L LTC1598L Figure 9. Reference Input Equivalent Circuit Reduced Reference Operation The effective resolution of the LTC1594L/LTC1598L can be increased by reducing the input span of the converters. The LTC1594L/LTC1598L exhibit good linearity and gain over a wide range of reference voltages (see typical curves Change in Linearity vs Reference Voltage and Change in Gain vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converters. The following factors must be considered when operating at low VREF values: 1. Offset 2. Noise 3. Conversion speed (CLK frequency) U W U U Offset with Reduced VREF The offset of the LTC1594L/LTC1598L has a larger effect on the output code when the ADCs are operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Change in Offset vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122µV which is 0.2LSB with a 2.5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “COM” input of the LTC1594L/ LTC1598L. Noise with Reduced VREF The total input referred noise of the LTC1594L/LTC1598L can be reduced to approximately 400µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 2.5V reference, the 400µV noise is only 0.66LSB peak-to-peak. In this case, the LTC1594L/ LTC1598L noise will contribute virtually no uncertainty to the output code. However, for reduced references the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference this same 400µV noise is 1.32LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 1LSB. If the reference is further reduced to 1V, the 400µV noise becomes equal to 1.65LSBs and a stable code may be difficult to achieve. In this case, averaging multiple readings may be necessary. This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup. 17 LTC1594L/LTC1598L APPLICATIONS INFORMATION Conversion Speed with Reduced VREF With reduced reference voltages, the LSB step size is reduced and the LTC1594L/LTC1598L internal comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of VREF are used. DYNAMIC PERFORMANCE The LTC1594L/LTC1598L have exceptional sampling capability. Fast Fourier Transform (FFT) test techniques are used to characterize the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 10 shows a typical LTC1594L/LTC1598L plot. 0 – 20 TA = 25°C VCC = 2.7V VREF = 2.5V fIN = 3.05kHz fCLK = 120kHz fSMPL = 7.5kHz EFFECTIVE NUMBER OF BITS (ENOBs) MAGNITUDE (dB) – 40 – 60 – 80 – 100 – 120 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (kHz) 3.5 4.0 1594L/98L G13 Figure 10. LTC1594L/LTC1598L Nonaveraged, 4096 Point FFT Plot Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio (S/N + D) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the ADC’s output. The output is band limited to frequencies above DC and below one half the sampling frequency. Figure 11 shows a typical spectral content with a 10.5kHz sampling rate. 18 U W U U Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to S/(N + D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where S/(N + D) is expressed in dB. At the maximum sampling rate of 10.5kHz with a 5V supply, the LTC1594L/ LTC1598L maintain above 10.7 ENOBs at 10kHz input frequency. Above 10kHz the ENOBs gradually decline, as shown in Figure 11, due to increasing second harmonic distortion. The noise floor remains low. 12 11 10 9 8 7 6 5 4 3 2 1 0 1 10 INPUT FREQUENCY (kHz) 100 1594L/98L G09 74 68 62 56 50 S/(N + D) (dB) TA = 25°C VCC = 2.7V fCLK = 200kHz fSMPL = 10.5kHz Figure 11. Effective Bits and S/(N + D) vs Input Frequency Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is defined as: THD = 20log 2 2 2 2 V2 + V3 + V4 + ... + VN V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through the Nth harmonics. The typical THD LTC1594L/LTC1598L APPLICATIONS INFORMATION specification in the Dynamic Accuracy table includes the 2nd through 5th harmonics. With a 1kHz input signal, the LTC1594L/LTC1598L have typical THD of 78dB with VCC = 2.7V. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while 3rd order IMD terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine waves are equal in magnitudes, the value (in dB) of the 2nd order IMD products can be expressed by the following formula: TYPICAL APPLICATIONS N Microprocessor Interfaces The LTC1594L/LTC1598L can interface directly (without external hardware) to most popular microprocessors’ (MPU) synchronous serial formats including MICROWIRE, SPI and QSPI. If an MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1594L/LTC1598L. Included here is one serial interface example. Motorola SPI (MC68HC05) The MC68HC05 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSBfirst and in 8-bit increments. The DIN word sent to the data register starts the SPI process. With three 8-bit transfers the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B7 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits B6 through B0 into the MPU. ANDing the second byte with 1FHEX clears the three most significant bits and ANDing the third byte with FEHEX clears the least significant bit. Shifting the data to the right by one bit results in a right justified word. U W U U U amplitude fa ± fb IMD fa ± fb = 20log   amplitude at fa  ( ) ( )   Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dBs relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input. The full-linear bandwidth is the input frequency at which the effective bits rating of the ADC falls to 11 bits. Beyond this frequency, distortion of the sampled input signal increases. The LTC1594L/LTC1598L have been designed to optimize input bandwidth, allowing the ADCs to undersample input signals with frequencies above the converters’ Nyquist Frequency. 19 LTC1594L/LTC1598L TYPICAL APPLICATIONS N MC68HC05 CODE LDA #$52 STA $0A LDA #$FF STA STA STA LDA $04 $05 $06 #$08 Configuration data for serial peripheral control register (Interrupts disabled, output enabled, master, Norm = 0, Ph = 0, Clk/16) Load configuration data into location $0A (SPCR) Configuration data for I/O ports (all bits are set as outputs) Load configuration data into Port A DDR ($04) Load configuration data into Port B DDR ($05) Load configuration data into Port C DDR ($06) Put DIN word for LTC1598L into Accumulator (CH0 with respect to GND) Load DIN word into memory location $50 Bit 0 Port C ($02) goes high (CS goes high) Load DIN word at $50 into Accumulator Load DIN word into SPI data register ($0C) and start clocking data Test status of SPIF bit in SPI status register ($0B) BPL LOOP1 BCLR 0,$02 LDA $0C STA $0C LOOP2 TST $0B BPL LOOP2 LDA $0C STA $0C AND #$IF STA $00 LOOP3 TST $0B BPL LOOP3 LDA $0C AND #$FE STA $01 JMP START Loop if not done with transfer to previous instruction Bit 0 Port C ($02) goes low (CS goes low) Load contents of SPI data register into Accumulator Start next SPI cycle Test status of SPIF Loop if not done Load contents of SPI data register into Accumulator Start next SPI cycle Clear 3 MSBs of first DOUT word Load Port A ($00) with MSBs Test status of SPIF Loop if not done Load contents of SPI data register into Accumulator Clear LSB of second DOUT word Load Port B ($01) with LSBs Go back to start and repeat program STA $50 START BSET 0,$02 LDA $50 STA $0C LOOP1 TST $0B CSMUX = CSADC = CS CLK DIN EN D2 DOUT MPU TRANSMIT WORD MPU RECEIVED WORD 0 0 0 0 EN D2 BYTE 1 ? ? ? ? ? ? ? ? ? ? 0 BYTE 1 DOUT FROM LTC1598L STORED IN MC68HC05 RAM MSB #00 0 0 0 B11 B10 B9 B8 B7 BYTE 1 ANALOG INPUTS 0 BYTE 2 CSMUX CSADC LSB #01 B6 B5 B4 B3 B2 B1 B0 LTC1598L CLK DIN DOUT C0 MC68HC05 SCK MOSI MISO 1594L/98L TA04 20 U Data Exchange Between LTC1598L and MC68HC05 D1 DO DON‘T CARE B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 D1 D0 X X X X BYTE 2 X X X X X X X X X X X X BYTE 3 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B11 B10 BYTE 2 BYTE 3 1594L/98L TA03 Hardware and Software Interface to Motorola MC68HC05 LTC1594L/LTC1598L TYPICAL APPLICATIONS N MULTICHANNEL A/D USES A SINGLE ANTIALIASING FILTER This circuit demonstrates how the LTC1598L’s independent analog multiplexer can simplify design of a 12-bit data acquisition system. All eight channels are MUXed into a single 1kHz, 4th order Sallen-Key antialiasing filter, which is designed for single supply operation. Since the LTC1598L’s data converter accepts inputs from ground to the positive supply, rail-to-rail op amps were chosen for the filter to maximize dynamic range. The LT1368 dual railto-rail op amp is designed to operate with 0.1µF load capacitors (C1 and C2). These capacitors provide frequency compensation for the amplifiers and help reduce the amplifier’s output impedance and improve supply rejection at high frequencies. The filter contributes less than 1LSB of error due to offsets and bias currents. The filter’s noise and distortion are less than –72dB for a 100Hz, 2VP-P offset sine input. The combined MUX and A/D errors result in an integral nonlinearity error of ± 3LSB (maximum) and a differential nonlinearity error of ± 3/4LSB (maximum). The typical signal-to-noise plus distortion ratio is 68dB, with approximately –78dB of total harmonic distortion. The LTC1598L is programmed through a 4-wire serial interface that is compatible with MICROWIRE, SPI and QSPI. Maximum serial clock speed is 200kHz, which corresponds to a 10.5kHz sampling rate. The complete circuit consumes approximately 600µA from a single 3V supply. Simple Data Acquisition System Takes Advantage of the LTC1598L’s MUXOUT/ADCIN Pins to Filter Analog Signals Prior to A/D Conversion 3.3V R1 7.5k R2 7.5k C1 0.03µF C2 0.015µF C8 0.01µF 1 C3 0.1µF R3 7.5k R4 7.5k C4 0.03µF C5 0.015µF LTC1598L 20 CH0 21 CH1 22 CH2 23 CH3 24 CH4 1 CH5 2 CH6 3 CH7 8 COM MUXOUT 8-CHANNEL MUX U 3 + – 8 5 + 1/2 LT1368 7 C6 0.1µF 1/2 LT1368 2 6 – 4 3.3V 18 17 ADCIN 16 15, 19 C7 1µF VREF VCC CSADC CSMUX 10 6 5, 14 7 11 12 13 SERIAL DATA LINK MICROWIRE AND SPI COMPATIBLE + 12-BIT SAMPLING ADC CLK DIN DOUT NC – GND 4, 9 NC 1594L/98L TA05 21 LTC1594L/LTC1598L TYPICAL APPLICATIONS N Using MUXOUT/ADCIN Loop as PGA This figure shows the LTC1598L’s MUXOUT/ADCIN pins and an LT1368 being used to create a single channel PGA with eight noninverting gains. Combined with the LTC1391, the system can expand to eight channels and eight gains for each channel. Using the LTC1594L, the PGA is reduced to four gains. The output of the LT1368 drives the ADCIN and the resistor ladder. The resistors above the selected MUX channel form the feedback for the LT1368. The gain for this amplifier is RS1/RS2 + 1. RS1 is the summation of the resistors above the selected MUX channel and RS2 is the summation of the resistors below the selected MUX channel. If CH0 is selected, the gain is 1 since RS1 is 0. Table 1 shows the gain for each MUX channel. The LT1368 dual rail-to-rail op amp is designed to operate with 0.1µF load capacitors. These capacitors provide frequency compensation for the amplifiers, help reduce the amplifiers’ output impedance and improve supply rejection at high frequencies. Because the LT1368’s IB is low, the RON of the selected channel will not affect the gain given by the formula above. Using the MUXOUT/ADCIN Pins of the LTC1598L to Form a PGA. The LTC1391 MUX Allows Eight Input Channels to be Digitized 3V LTC1391 1 2 3 4 5 6 7 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 15 D 14 V– 13 12 11 10 9 64R 32R 16R 8R 4R 2R R R 20 21 22 23 24 1 2 3 18 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 LTC1598L MUXOUT COM NC GND 4, 9 NC 12 13 8-CHANNEL MUX 12-BIT SAMPLING ADC CSADC CSMUX 10 6 5, 14 11 7 µP/µC V+ 16 3(5) 1µF 3V 1µF 1(7) 0.1µF 4 17 ADCIN 16 15, 19 VREF VCC 3V 1µF + – 1/2 LT1368 2(6) DOUT DIN CS CLK GND = DAISY CHAIN CONFIGURATION FOR THE LTC1391 AND THE LTC1598L 22 U 8 + CLK DOUT DIN – 1594L/98L TA06 LTC1594L/LTC1598L PACKAGE DESCRIPTION 5.20 – 5.38** (0.205 – 0.212) 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 8.07 – 8.33* (0.318 – 0.328) 24 23 22 21 20 19 18 17 16 15 14 13 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 1.73 – 1.99 (0.068 – 0.078) 0 ° – 8° 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) 0.05 – 0.21 (0.002 – 0.008) G24 SSOP 1098 S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.053 – 0.069 (1.346 – 1.752) 2 3 4 5 6 7 8 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP 0.050 (1.270) BSC S16 1098 23 LTC1594L/LTC1598L TYPICAL APPLICATION Using the LTC1598L and LTC1391 as an 8-Channel Differential 12-Bit ADC System 3V 18 MUXOUT 20 21 3V 1µF 22 23 24 1 LTC1391 CH0 1 2 3 4 5 6 7 CH7 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 15 D – 14 V 13 12 11 10 9 V+ 16 2 3 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM LTC1598L GND 4, 9 8-CHANNEL MUX 12-BIT SAMPLING ADC CSADC CSMUX 10 6 5, 14 7 11 12 13 17 ADCIN 16 15, 19 VREF VCC 1µF DOUT DIN CS CLK GND DIN CLK CS DOUT = DAISY CHAIN CONFIGURATION FOR THE LTC1391 AND THE LTC1598L 1594L/98L TA07 RELATED PARTS PART NUMBER LTC1096/LTC1098 LTC1096L/LTC1098L LTC1196/LTC1198 LTC1282 LTC1285/LTC1288 LTC1286/LTC1298 LTC1289 LTC1296 LTC1415 LTC1594 LTC1598 DESCRIPTION 8-Pin SO, Micropower 8-Bit ADCs 8-Pin SO, 2.65V Micropower 8-Bit ADCs 8-Pin SO, 1Msps 8-Bit ADCs 3V High Speed Parallel 12-Bit ADC 8-Pin SO, 3V, Micropower ADCs 8-Pin SO, 5V, Micropower ADCs Multiplexed 3V, 12-Bit ADC Multiplexed 5V, 12-Bit ADC 5V High Speed Parallel 12-Bit ADC 4-Channel, 5V Micropower 12-Bit ADC 8-Channel, 5V Micropower 12-Bit ADC 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U + CLK DIN DOUT NC NC – COMMENTS Low Power, Small Size, Low Cost Low Power, Small Size, Low Cost Low Power, Small Size, Low Cost 140ksps, Complete with VREF, CLK, Sample-and-Hold 1- or 2-Channel, Auto Shutdown 1- or 2-Channel, Auto Shutdown 8-Channel 12-Bit Serial I/O 8-Channel 12-Bit Serial I/O 1.25Msps, Complete with VREF, CLK, Sample-and-Hold Low Power, Small Size, Low Cost Low Power, Small Size, Low Cost 15948lfa LT/TP 0500 2K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1997