LTC1605I

LTC1605 16-Bit, 100ksps, Sampling ADC FEATURES s s s s s s s s s s s DESCRIPTION The LTC ®1605 is a 100ksps, sampling 16-bit A/D converter that draws only 55mW (typical) from a single 5V supply. This easy-to-use device includes sample-andhold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock. The LTC1605’s input range is an industry standard ±10V. Maximum DC specs include ± 2.0LSB INL and 16-bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed. The ADC has a microprocessor compatible, 16-bit or two byte parallel output port. A convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LTC and LT are registered trademarks of Linear Technology Corporation. Sample Rate: 100ksps Single 5V Supply Bipolar Input Range: ±10V Power Dissipation: 55mW Typ Integral Nonlinearity: ± 2.0LSB Max Guaranteed No Missing Codes Signal-to-Noise Ratio: 86dB Typ Operates with Internal or External Reference Internal Synchronized Clock 28-Pin 0.3” PDIP, SSOP and SW Packages Improved 2nd Source to ADS7805 and AD976 APPLICATIONS s s s s Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing TYPICAL APPLICATION Low Power, 100kHz, 16-Bit Sampling ADC on 5V Supply 5V 10µF 28 27 VDIG VANA ±10V 200Ω INPUT 33.2k 4 CAP 2.2µF 3 REF 2.2µF AGND1 2 AGND2 5 DGND 14 1605 • TA01 0.1µF 1 VIN 20k 16-BIT SAMPLING ADC 4k 10k D15 TO D0 16-BIT OR 2 BYTE PARALLEL BUS INL (LSBs) 6 TO 13 15 TO 22 BUSY 26 BUFFER 4k REFERENCE CONTROL LOGIC AND TIMING CS 25 R/C 24 BYTE 23 DIGITAL CONTROL SIGNALS U U U Typical INL Curve 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 CODE 1605 • TA02 49152 65535 1 LTC1605 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW VIN 1 AGND1 2 REF 3 CAP 4 AGND2 5 D15 (MSB) 6 D14 7 D13 8 D12 9 D11 10 D10 11 D9 12 D8 13 DGND 14 28 VDIG 27 VANA 26 BUSY 25 CS 24 R/C 23 BYTE 22 D0 21 D1 20 D2 19 D3 18 D4 17 D5 16 D6 15 D7 VANA .......................................................................... 7V VDIG to VANA ........................................................... 0.3V VDIG ........................................................................... 7V Ground Voltage Difference DGND, AGND1 and AGND2 .............................. ± 0.3V Analog Inputs (Note 3) VIN ..................................................................... ± 25V CAP ............................ VANA + 0.3V to AGND2 – 0.3V REF .................................... Indefinite Short to AGND2 Momentary Short to VANA Digital Input Voltage (Note 4) ............ VSS – 0.3V to 10V Digital Output Voltage ........ VDGND – 0.3V to VDIG + 0.3V Power Dissipation.............................................. 500mW Operating Ambient Temperature Range LTC1605C................................................ 0°C to 70°C LTC1605I............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1605ACG LTC1605ACN LTC1605ACSW LTC1605AIG LTC1605AIN LTC1605AISW LTC1605CG LTC1605CN LTC1605CSW LTC1605IG LTC1605IN LTC1605ISW G PACKAGE 28-LEAD PLASTIC SSOP N PACKAGE 28-LEAD PDIP SW PACKAGE 28-LEAD PLASTIC SO WIDE TJMAX = 125°C, θJA = 95°C/W (G) TJMAX = 125°C, θJA = 130°C/W (N) TJMAX = 125°C, θJA = 130°C/W (SW) Consult factory for Military grade parts. CONVERTER CHARACTERISTICS PARAMETER Resolution No Missing Codes Transition Noise Integral Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Drift Full-Scale Error Full-Scale Error Drift Power Supply Sensitivity VANA = VDIG = VDD Ext. Reference = 2.5V (Notes 12, 13) Ext. Reference = 2.5V VDD = 5V ± 5% (Note 9) (Note 7) Ext. Reference = 2.5V (Note 8) CONDITIONS With external reference (Notes 5, 6). MIN q q LTC1605 TYP MAX MIN 16 16 LTC1605A TYP MAX UNITS Bits Bits 16 15 1.0 ±3 ±10 ±2 ±7 1.0 ±2 ±10 ±2 ±5 ± 0.50 ± 0.25 ±2 ±8 ±8 q q ppm/°C ppm/°C % ppm/°C LSB q ±2 2 U LSB LSB mV W U U WW W U LTC1605 ANALOG INPUT SYMBOL VIN IIN CIN RIN PARAMETER Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Analog Input Impedance DYNAMIC ACCURACY SYMBOL S/(N + D) PARAMETER Signal-to-(Noise + Distortion) Ratio THD Total Harmonic Distortion Peak Harmonic or Spurious Noise Full-Power Bandwidth Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery INTERNAL REFERENCE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco Internal Reference Source Current External Reference Voltage for Specified Linearity External Reference Current Drain CAP Output Voltage (Notes 9, 10) Ext. Reference = 2.5V (Note 9) IOUT = 0 CONDITIONS IOUT = 0 IOUT = 0 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage VDD = 4.75V VDD = 4.75V CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD U U U U WU U U (Note 5) CONDITIONS 4.75V ≤ VANA ≤ 5.25V, 4.75V ≤ VDIG ≤ 5.25V CS = High q q MIN LTC1605/LTC1605A TYP MAX ±10 ±1 10 20 UNITS V µA pF kΩ (Notes 5, 14) CONDITIONS 1kHz Input Signal (Note 14) 10kHz Input Signal 20kHz, – 60dB Input Signal 1kHz Input Signal, First 5 Harmonics 10kHz Input Signal, First 5 Harmonics 1kHz Input Signal 10kHz Input Signal (Note 15) MIN LTC1605/LTC1605A TYP MAX 87.5 87 30 – 102 – 94 – 102 – 94 275 40 Sufficient to Meet AC Specs Full-Scale Step (Note 9) (Note 16) 150 2 µs ns UNITS dB dB dB dB dB dB dB kHz ns U (Note 5) MIN q LTC1605/LTC1605A TYP MAX 2.500 ±5 1 2.520 UNITS V ppm/°C µA 2.470 2.30 q 2.50 2.50 2.70 100 V µA V (Note 5) MIN q q q LTC1605/LTC1605A TYP MAX 0.8 ±10 5 4.5 UNITS V V µA pF V V V 2.4 IO = –10µA IO = – 200µA IO = 160µA IO = 1.6mA q q 4.0 0.05 0.10 0.4 V 3 LTC1605 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL IOZ COZ ISOURCE ISINK PARAMETER Hi-Z Output Leakage D15 to D0 Hi-Z Output Capacitance D15 to D0 Output Source Current Output Sink Current CONDITIONS VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V VOUT = VDD TIMING CHARACTERISTICS SYMBOL fSAMPLE(MAX) tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Convert Pulse Width Data Valid Delay After R/C↓ BUSY Delay from R/C↓ BUSY Low BUSY Delay After End of Conversion Aperture Delay Bus Relinquish Time BUSY Delay After Data Valid Previous Data Valid After R/C↓ R/C to CS Setup Time Time Between Conversions Bus Access and Byte Delay POWER REQUIREMENTS SYMBOL VDD IDD PDIS PARAMETER Positive Supply Voltage Positive Supply Current Power Dissipation The q indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above VANA = VDIG = VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below ground or above VDD without latch-up. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 90mA below ground without latchup. These pins are not clamped to VDD. 4 UW U U (Note 5) MIN q q LTC1605/LTC1605A TYP MAX ±10 15 –10 10 UNITS µA pF mA mA UW (Note 5) MIN q q q CONDITIONS LTC1605/LTC1605A TYP MAX 8 2 UNITS kHz µs µs ns µs ns µs ns ns 100 (Note 11) (Note 9) CL = 50pF q q q 40 8 65 8 220 40 q q 10 50 10 10 10 35 200 7.4 83 ns ns µs ns µs (Notes 9, 10) (Notes 9, 10) 83 ns (Note 5) CONDITIONS (Notes 9, 10) q MIN 4.75 LTC1605/LTC1605A TYP MAX 5.25 11 55 16 80 UNITS V mA mW Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a VIN input with respect to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. LTC1605 ELECTRICAL CHARACTERISTICS Note 11: With CS low the falling R/C edge starts a conversion. If R/C returns high at a critical point during the conversion it can create small errors. For best results ensure that R/C returns high within 3µs after the start of the conversion. Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. Note 13: Full-scale error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. Note 14: All specifications in dB are referred to a full-scale ±10V input. Note 15: Full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of accuracy. Note 16: Recovers to specified performance after (2 • FS) input overvoltage. TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage 12.5 fSAMPLE = 100kHz 12.0 SUPPLY CURRENT (mA) POSITIVE SUPPLY CURRENT (mA) 11.5 11.5 11.0 10.5 10.0 9.5 4.50 11.0 10.5 4.75 5.00 5.25 5.50 1605 • TPC01 10.0 –50 CHANGE IN CAP VOLTAGE (V) SUPPLY VOLTAGE (V) Typical INL Curve 2.0 1.5 1.0 2.0 1.5 1.0 POWER SUPPLY FEEDTHROUGH (dB) DNL (LSBs) INL (LSBs) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 CODE 1605 • TPC04 49152 UW Supply Current vs Temperature 12.0 fSAMPLE = 100kHz Change in CAP Voltage vs Load Current 0.05 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.10 –80 –70 –60 –50 –40 –30 –20 –10 LOAD CURRENT (mA) –25 0 25 50 TEMPERATURE (°C) 75 100 0 10 1605 • TPC02 1605 • TPC03 Typical DNL Curve –20 Power Supply Feedthrough vs Ripple Frequency –30 0.5 0 –0.5 –1.0 –1.5 –40 –50 –60 65535 –2.0 0 16384 32768 CODE 1605 • TPC05 –70 49152 65535 1 10 100 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M 1605 • TPC06 5 LTC1605 TYPICAL PERFORMANCE CHARACTERISTICS LTC1605 Nonaveraged 4096 Point FFT Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 f SAMPLE = 100kHz f IN = 1kHz SINAD =87.5dB THD =–101.7dB MAGNITUDE (dB) SINAD vs Input Frequency 90 TOTAL HARMONIC DISTORTION (dB) 89 88 87 SINAD (dB) 86 85 84 83 82 81 1 10 INPUT FREQUENCY (kHz) 100 1605 • TPC08 PIN FUNCTIONS VIN (Pin 1): Analog Input. Connect through a 200Ω resistor to the analog input. Full-scale input range is ±10V. AGND1 (Pin 2): Analog Ground. Tie to analog ground plane. REF (Pin 3): 2.5V Reference Output. Bypass with 2.2µF tantalum capacitor. Can be driven with an external reference. CAP (Pin 4): Reference Buffer Output. Bypass with 2.2µF tantalum capacitor. AGND2 (Pin 5): Analog Ground. Tie to analog ground plane. D15 to D8 (Pins 6 to 13): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. DGND (Pin 14): Digital Ground. D7 to D0 (Pins 15 to 22): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. BYTE (Pin 23): Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0) being the LSB. With BYTE high the upper eight bits and the lower eight bits will be switched. The MSB is output 6 UW 5 10 15 20 25 30 FREQUENCY (kHz) 35 40 45 50 1605 • TPC07 Total Harmonic Distortion vs Input Frequency –70 –80 –90 –100 –110 1 10 INPUT FREQUENCY (kHz) 100 1605 • TPC09 U U U LTC1605 PIN FUNCTIONS on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on Pin 6 and the LSB is output on Pin 13. R/C (Pin 24): Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. With CS low, a rising edge on R/C enables the output data bits. CS (Pin 25): Chip Select. Internally OR’d with R/C. With R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data. BUSY (Pin 26): Output Shows Converter Status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. CS or R/C must be high when BUSY rises or another conversion will start without time for signal acquisition. VANA (Pin 27): 5V Analog Supply. Bypass to ground with a 0.1µF ceramic and a 10µF tantalum capacitor. VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin 27. TEST CIRCUITS Load Circuit for Access Timing 5V 1k DBN 1k CL DBN CL LTC1605 • TC01 A. HI-Z TO VOH AND VOL TO VOH FUNCTIONAL BLOCK DIAGRA VIN 20k 10k 4k 4k REF 2.5V REF REF BUF 16-BIT CAPACITIVE DAC CAP (2.5V) AGND1 AGND2 DGND INTERNAL CLOCK SUCCESSIVE APPROXIMATION REGISTER W U U U U U Load Circuit for Output Float Delay 5V 1k DBN 1k 50pF DBN 50pF LTC1605 • TC02 B. HI-Z TO VOL AND VOH TO VOL A. VOH TO HI-Z B. VOL TO HI-Z CSAMPLE CSAMPLE ZEROING SWITCHES VANA VDIG + COMP – 16 OUTPUT LATCHES • • • D15 D0 CONTROL LOGIC LTC1605 • BD CS R/C BYTE BUSY 7 LTC1605 APPLICATIONS INFORMATION Conversion Details The LTC1605 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and R/C inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, VIN is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. In this acquire phase, a minimum delay of 2µs will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the VIN input charge. The SAR contents (a 16-bit data word) that represents the VIN are loaded into the 16-bit output latches. SAMPLE CSAMPLE SI RIN1 VIN RIN2 SAMPLE HOLD – + COMPARATOR DAC VDAC S A R CDAC Figure 1. LTC1605 Simplified Equivalent Circuit 8 U W U U Driving the Analog Inputs The nominal input range for the LTC1605 is ± 10V or (± 4 • VREF) and the input is overvoltage protected to ± 25V. The input impedance is typically 20kΩ, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 1000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1605. More detailed information is available in the Linear Technology data books and LinearViewTM CD-ROM. AIN 200Ω VIN 1000pF 33.2k CAP 1605 • F02 Figure 2. Analog Input Filtering LT1007 - Low noise precision amplifier. 2.7mA supply current ± 5V to ± 15V supplies. Gain bandwidth product 8MHz. DC applications. LT1097 - Low cost, low power precision amplifier. 300µA supply current. ±5V to ± 15V supplies. Gain bandwidth product 0.7MHz. DC applications. LT1227 - 140MHz video current feedback amplifier. 10mA supply current. ± 5V to ± 15V supplies. Low noise and low distortion. LT1360 - 37MHz voltage feedback amplifier. 3.8mA supply current. ± 5V to ± 15V supplies. Good AC/DC specs. LT1363 - 50MHz voltage feedback amplifier. 6.3mA supply current. Good AC/DC specs. LT1364/LT1365 - Dual and quad 50MHz voltage feedback amplifiers. 6.3mA supply current per amplifier. Good AC/ DC specs. 16-BIT LATCH 1605 • F01 LinearView is a trademark of Linear Technology Corporation LTC1605 APPLICATIONS INFORMATION Internal Voltage Reference The LTC1605 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the ADC is equal to (± 4 • VREF) or nominally ± 10V. The output of the reference is connected to the input of a unity-gain buffer through a 4k resistor (see Figure 3). The input to the buffer or the output of the reference is available at REF (Pin 3). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at CAP (Pin 4). The CAP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. REF (2.5V) 2.2µF 3 4k VANA 33.2k 1% 5V 576k R4 50k 33.2k 1% + 2.2µF Figure 4. ±10V Input Without Trim 1 200Ω 1% 2 2.2µF 3 REF LTC1605 4 2.2µF 5 AGND2 1605 • F05 BANDGAP REFERENCE ±10V INPUT – CAP (2.5V) 2.2µF 4 INTERNAL CAPACITOR DAC 1605 • F03 R3 50k + Figure 5. ±10V Input with Offset and Gain Trim Figure 3. Internal or External Reference Source OUTPUT CODE For minimum code transition noise the REF pin and the CAP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2µF tantalum). Offset and Gain Adjustments The LTC1605 offset and full-scale errors have been trimmed at the factory with the external resistors shown in Figure 4. This allows for external adjustment of offset and full scale in applications where absolute accuracy is important. See Figure 5 for the offset and gain trim circuit. First adjust the offset to zero by adjusting resistor R3. Apply an input voltage of –152.6mV (– 0.5LSB) and adjust R3 so the code is changing between 1111 1111 1111 1111 and 0000 0000 0000 0000. The gain error is trimmed by adjusting resistor R4. An input voltage of 9.999542V (+FS – 1.5LSB) is 011...111 011...110 BIPOLAR ZERO 000...001 000...000 111...111 111...110 100...001 100...000 –FS/2 –1 0V 1 LSB LSB INPUT VOLTAGE (V) Figure 6. LTC1605 Bipolar Transfer Characteristics DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC + + + U W U U applied to VIN and R4 is adjusted until the output code is changing between 0111 1111 1111 1110 and 0111 1111 1111 1111. Figure 6 shows the bipolar transfer characteristic of the LTC1605. ±10V INPUT 1 200Ω 1% 2 2.2µF 3 4 5 VIN AGND1 LTC1605 REF CAP AGND2 1605 • F04 VIN AGND1 CAP FS = 20V 1LSB = FS/65536 FS/2 – 1LSB 1605 • F06 9 LTC1605 APPLICATIONS INFORMATION signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 7 the distribution of output code is shown for a DC input that has been digitized 10000 times. The distribution is Gaussian and the RMS code transition is about 1LSB. 4500 4000 3500 3000 COUNT 2500 2000 1500 1000 500 0 –5 –4 –3 –2 –1 0 1 CODE 2 3 4 5 1605 • F07 Figure 7. Histogram for 10000 Conversions DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 7µs. No external adjustments are required and, with the typical acquisition time of 1µs, throughput performance of 100ksps is assured. t1 R/C t 11 t2 BUSY t6 MODE ACQUIRE CONVERT t CONV t9 DATA MODE PREVIOUS DATA VALID t7 HI-Z PREVIOUS DATA VALID NOT VALID t8 DATA VALID HI-Z DATA VALID 1605 • F08 t3 Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) 10 U W U U Timing and Control Conversion start and data read are controlled by two digital inputs: CS and R/C. To start a conversion and put the sample-and-hold into the hold mode bring CS and R/C low for no less than 40ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while the conversion is in progress. There are two modes of operation. The first mode is shown in Figure 8. The digital input R/C is used to control the start of conversion. CS is tied low. When R/C goes low the sample-and-hold goes into the hold mode and a conversion is started. BUSY goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. R/C should remain low for no less than 40ns. During the time R/C is low the digital outputs are in a Hi-Z state. R/C should be brought back high within 3µs after the start of the conversion to ensure that no errors occur in the digitized result. The second mode, shown in Figure 9, uses the CS signal to control the start of a conversion and the reading of the digital output. In this mode the R/C input signal should be brought low no less than 10ns before the falling edge of CS. The minimum pulse width for CS is 40ns. When CS falls, BUSY goes low and will stay low until the end of the conversion. BUSY will go high after the conversion has been completed. The new data is valid when CS is brought back low again to initiate t4 t5 ACQUIRE t ACQ CONVERT LTC1605 APPLICATIONS INFORMATION t 10 R/C t 10 t 10 t 10 t1 CS t3 BUSY t6 MODE ACQUIRE CONVERT t CONV HI-Z DATA BUS Figure 9. Using CS to Control Conversion and Read Timing t 10 R/C t 10 CS BYTE PINS 6 TO 13 HI-Z HIGH BYTE t 12 t 12 LOW BYTE PINS 15 TO 22 HI-Z Figure 10. Using CS and BYTE to Control Data Bus Read Timing 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 MAGNITUDE (dB) f SAMPLE = 100kHz f IN = 1kHz SINAD =87.5dB THD =–101.7dB 5 10 15 Figure 11. LTC1605 Nonaveraged 4096 Point FFT Plot U W U U t1 t4 ACQUIRE DATA VALID t 12 t7 HI-Z 1605 • F09 LOW BYTE t7 HIGH BYTE HI-Z HI-Z 1605 • F03 20 25 30 FREQUENCY (kHz) 35 40 45 50 1605 • F11 11 LTC1605 APPLICATIONS INFORMATION a read. Again it is recommended that both R/C and CS return high within 3µs after the start of the conversion. Output Data The output data can be read as a 16-bit word or it can be read as two 8-bit bytes. The format of the output data is two’s complement. The digital input pin BYTE is used to control the two byte read. With the BYTE pin low the first eight MSBs are output on the D15 to D8 pins and the eight LSBs are output on the D7 to D0 pins. When the BYTE pin is taken high the eight LSBs replace the eight MSBs (Figure 10). Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 11 shows a typical LTC1605 FFT plot which yields a SINAD of 87.5dB and THD of – 102dB. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 11 shows a typical SINAD of 87.5dB with a 100kHz sampling rate and a 1kHz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20log √V22 + V32 + V42 ... + VN2 V1 12 U W U U where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Board Layout, Power Supplies and Decoupling Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1605, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. Figures 12 through 15 show a layout for a suggested evaluation circuit which will help obtain the best performance from the 16-bit ADC. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1605 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the power supply ground connection. LTC1605 APPLICATIONS INFORMATION Figure 12. Component Side Silkscreen for the Suggested LTC1605 Evaluation Circuit ANALOG GROUND PLANE DIGITAL GROUND PLANE Figure 13. Bottom Side Showing Analog Ground Plane U W U U ANALOG GROUND PLANE Figure 14. Component Side Showing Separate Analog and Digital Ground Plane 13 GND E2 D10 D9 D8 1 2 3 4 5 6 7 12 2 8 9 1 U4A 74HC04 CLK U3 74HC574 D0 D1 16 D6 17 D5 18 D4 19 D3 20 D2 D2 4 13 C8 0.1µF D1 D0 21 D1 R6, 1.2k 22 D0 R5, 1.2k R4, 1.2k U4B 74HC04 3 4 R20 1K C1 15PF U4C 74HC04 5 6 R3, 1.2k R2, 1.2k R1, 1.2k R0, 1.2k D2 D3 D4 D5 D6 D7 1 11 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 OC CLK R7, 1.2k D7 D6 D5 D4 D3 D2 D1 D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 10 11 12 13 14 15 16 17 18 19 20 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 CLK GND GND R9, 1.2k U1 LTC1605 U2 74HC574 6 D15 D0 D1 D2 D3 D4 D5 D6 D7 OC Q7 Q6 13 Q5 14 Q4 15 Q3 16 Q2 17 Q1 18 Q0 D14 D14 D13 D11 9 D12 D10 D9 5 AGND2 D11 D8 1 11 12 D9 13 D8 15 D7 9 D10 D9 D8 D7 D6 D5 D4 D3 11 D10 DGND BYTE R/C CS BUSY VANA VDIG C5 0.1µF 14 23 24 25 REVERSE 3 BYTE NORNAL 1 VKK 28 C7 10µF EXT 3 JP3 2 1 A B 3 CLK CEXT 15 RCEXT VCC VCC 3 CS GND 1 JP5 2 R21, 2k Q Q 2 U6A 74HC221 27 JP4 2 26 10 D11 8 7 6 D12 8 D13 D12 5 7 D14 D13 4 3 D15 2 19 1 VIN AGND1 REF CAP D15 C16 1000pF 2 3 EXT VREF INT 4 C4 2.2µF C2 2.2µF C17 10µF C3 0.1µF JP1 R19 33.2k 1% R8, 1.2k VIN U5 LT1121 GND 2 D12 D11 R10, 1.2k AIN 8 7 6 5 J2 1 R18 200Ω 1% 2 VKK 1 NC1 NC2 INPUT HEATER 3 TEMP OUT 4 GND TRIM APPLICATIONS INFORMATION JP2 LED ENABLE VCC U4D 74HC04 EXT_CLK 1 J1 9 8 U4E 74HC04 11 10 2 R17 51 VCC U8 1MHz, OSC INT 1 VCC U7 74HC160 1 NA 1 CLK CLR 9 LOAD 2 GND OUT 3 2 CLK 10 ENT 7 ENP RCO 15 6 D QD 11 5 C QC 12 4 B QB 13 3 A QA 14 1605_07d.eps Figure 15. LTC1605 Suggested Evaluation Circuit Schematic U U9 LT1019-2.5 W 2 U U 14 R15, 1.2k D15 D14 D13 DIGITAL I.C. BYPASSING VKK VCC VDD R16 20 C9 0.1µF C11 0.1µF R12, 1.2k R11, 1.2k C12 0.1µF C13 0.1µF C14 0.1µF C15 10µF C10 0.1µF R13, 1.2k VCC R14, 1.2k LTC1605 VIN 7V TO 15V 1 E1 VIN 3 D16 MBR0520 + C6 22µF 10V LTC1605 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.397 – 0.407* (10.07 – 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) 0.0256 (0.65) BSC *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.010 – 0.015 (0.25 – 0.38) 0.002 – 0.008 (0.05 – 0.21) G28 SSOP 0694 N Package 28-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.370* (34.789) MAX 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.255 ± 0.015* (6.477 ± 0.381) 1 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN 0.009 – 0.015 (0.229 – 0.381) 2 3 4 5 6 7 8 9 10 11 12 13 14 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.005 (0.127) MIN 0.100 ± 0.010 (2.540 ± 0.254) 0.018 ± 0.003 (0.457 ± 0.076) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.125 (3.175) MIN *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) N28 1197 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1605 PACKAGE DESCRIPTION 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER LT ® 1019-2.5 LTC1274/LTC1277 LTC1415 LTC1419 LT1460-2.5 LTC1594/LTC1598 DESCRIPTION Precision Bandgap Reference Low Power 12-Bit, 100ksps ADCs Single 5V, 12-Bit, 1.25Msps ADC Low Power 14-Bit, 800ksps ADC Micropower Precision Series Reference Micropower 4-/8-Channel 12-Bit ADCs COMMENTS 0.05% Max, 5ppm/°C Max 10mW Power Dissipation, Parallel/Byte Interface 55mW Power Dissipation, 72dB SINAD True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current Serial I/O, 3V and 5V Versions 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NOTE 1 0.394 – 0.419 (10.007 – 10.643) 1 0.093 – 0.104 (2.362 – 2.642) 2 3 4 5 6 7 8 9 10 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0.050 (1.270) TYP 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) S28 (WIDE) 0996 1605fa LT/TP 0598 2K REV A • PRINTED IN THE USA © LINEAR TECHNOLOGY CORPORATION 1997