LTC1654IGN

LTC1654 Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package FEATURES ■ ■ DESCRIPTIO ■ ■ ■ ■ ■ ■ ■ 14-Bit Monotonic Over Temperature Individually Programmable Speed/Power: 3µs Settling Time at 930µA 8.5µs Settling Time at 540µA 3V to 5V Single Supply Operation Maximum Update Rate: 0.9MHz Buffered True Rail-to-Rail Voltage Outputs User Selectable Gain Power-On Reset and Clear Function Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface Smallest Dual 14-Bit DAC: 16-Lead Narrow SSOP Package The LTC®1654 is a dual, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC). It is available in a 16-lead narrow SSOP package, making it the smallest dual 14-bit DAC available. It includes output buffer amplifiers and a flexible serial interface. The LTC1654 has REFHI pins for each DAC that can be driven up to VCC. The output will swing from 0V to VCC in a gain of 1 configuration or VCC/2 in a gain of 1/2 configuration. It operates from a single 2.7V to 5.5V supply. The LTC1654 has two programmable speeds: a FAST and SLOW mode with ±1LSB settling times of 3µs or 8.5µs respectively and supply currents of 930µA and 540µA in the two modes. The LTC1654 also has shutdown capability, power-on reset and a clear function to 0V. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245. APPLICATIO S ■ ■ ■ ■ ■ Digital Calibration Industrial Process Control Automatic Test Equipment Offset/Gain Adjustment Multiplying DAC BLOCK DIAGRA CS/LD SCK CONTROL LOGIC SDI INPUT LATCH DAC REGISTER DAC B + VOUT B – 32-BIT SHIFT REGISTER X1/X1/2 B REFHI A INPUT LATCH DAC REGISTER DAC A + VOUT A SDO POWER-ON RESET REFLO B REFLO A – X1/X1/2 A 1654 BD CLR U REFHI B 1654fb W U 1 LTC1654 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A 1 2 3 4 5 6 7 8 16 VCC 15 VOUT B 14 REFHI B 13 REFLO B 12 AGND 11 REFLO A 10 REFHI A 9 VOUT A VCC to GND .............................................. – 0.5V to 7.5V TTL Input Voltage, REFHI, REFLO, X1/X1/2 ........................................ – 0.5V to 7.5V VOUT, SDO .................................. – 0.5V to (VCC + 0.5V) Operating Temperature Range LTC1654C ............................................. 0°C to 70°C LTC1654I ........................................ – 40°C to 85°C Maximum Junction Temperature .......................... 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1654CGN LTC1654IGN GN PART MARKING 1654 1654I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. SYMBOL DAC n DNL INL ZSE VOS VOSTC PARAMETER Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Zero Scale Error Offset Error Offset Error Tempco Gain Error Gain Error Drift Power Supply VCC ICC Positive Supply Voltage Supply Current (SLOW/FAST) For Specified Performance 2.7V ≤ VCC ≤ 5.5V (Note 5) SLOW 2.7V ≤ VCC ≤ 5.5V (Note 5) FAST 2.7V ≤ VCC ≤ 3.3V (Note 5) SLOW 2.7V ≤ VCC ≤ 3.3V (Note 5) FAST In Shutdown (Note 5) VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 REFHIA, REFHIB = 4.096V (VCC = 5V ±10%) REFHIA, REFHIB = 2.048V (VCC = 3V ±10%) Input Code = 16383 ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS CONDITIONS MIN ● ● TYP MAX UNITS Bits Bits 14 14 ± 0.3 ± 1.2 0 ±1 ±4 6.5 9.0 ± 6.5 ± 9.0 ± 15 ± 24 5 2.7 540 930 350 680 3 70 80 40 5.5 850 1400 500 1000 10 120 120 200 2.5 Guaranteed Monotonic (Note 2) Integral Nonlinearity (Note 2) 0°C ≤ TA ≤ 70°C – 40°C ≤ TA ≤ 85°C 0°C ≤ TA ≤ 70°C (Note 3) – 40°C ≤ TA ≤ 85°C (Note 3) ● ● ● ● ● ● ppm/°C V µA µA µA µA µA mA mA Ω mV/V Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND PSR Power Supply Rejection 2 U LSB LSB mV mV mV mV µV/°C LSB 1654fb W U U WW W LTC1654 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Midscale Glitch Impulse Output Noise Voltage Density Digital I/O VIH VIL VOH VOL VIH VIL VOH VOL ILEAK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance Reference Input Resistance Reference Input Range Reference Input Current Switching Characteristics (VCC = 4.5V to 5.5V) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 t2 t3 t4 t5 t6 t7 SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK to CS/LD CS/LD Low to SCK SD0 Output Delay SCK Low to CS/LD Low CLR Pulse Width SDI Valid to SCK Setup SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK to CS/LD CS/LD Low to SCK (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) VCC = 5V VCC = 5V CONDITIONS AC Performance The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. MIN ● ● TYP 0.9 3.8 8.5 3.0 1 20 170 150 MAX UNITS V/µs V/µs µs µs nV•s nV•s nV/√Hz nV/√Hz V (Note 8) SLOW (Note 8) FAST (Note 4) to ±1LSB, SLOW (Note 4) to ±1LSB, FAST (Note 7) DAC Switch Between 8000 and 7FFF at 10kHz, SLOW at 10kHz, FAST 0.20 1.25 ● ● ● ● ● ● ● ● ● 2.4 0.8 VCC – 0.4 0.4 2.4 0.8 VCC – 0.4 0.4 ± 10 10 V V V V V V V µA pF kΩ VCC = 5V, IOUT = – 1mA, DOUT Only VCC = 5V, IOUT = 1mA, DOUT Only VCC = 3V VCC = 3V VCC = 3V, IOUT = – 1mA, DOUT Only VCC = 3V, IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 6) REFHI to REFLO (Note 6) In Shutdown Reference Input ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 30 0 60 VCC 1 V µA ns ns ns ns ns ns ns 30 0 15 15 15 10 10 5 10 30 45 0 20 20 20 15 15 100 CLOAD = 100pF (Note 6) (Note 6) ns ns ns ns ns ns ns ns ns ns 1654fb Switching Characteristics (VCC = 2.7V to 5.5V) 3 LTC1654 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V (VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V. SYMBOL t8 t9 t10 PARAMETER SDO Output Delay SCK Low to CS/LD Low CLR Pulse Width CONDITIONS CLOAD = 100pF (Note 6) (Note 6) ● ● ● ELECTRICAL CHARACTERISTICS MIN 5 15 45 TYP MAX 150 UNITS ns ns ns Switching Characteristics (VCC = 2.7V to 5.5V) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity is defined from low code kL to code 16383. See Applications Information (page 11). Note 3: Offset error is measured at low code kL. See Applications Information (page 11). Note 4: DAC switched between code 2 kL and code 16383. See Applications Information (page 11) for definition of low code kL. Note 5: Digital inputs at 0V or VCC. Note 6: Guaranteed by design. Note 7: CS/LD = 0, VOUT = 4.096V and data is being clocked in. Note 8: 100pF load capacitor. TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) vs Input Code 2.0 1.5 1.0 DNL (LSB) INL (LSB) 2.0 1.5 0.5 0 –0.5 –1.0 –1.5 –2.0 0 8192 INPUT CODE 1654 G01 0.5 0 –0.5 –1.0 –1.5 –2.0 OFFSET ERROR (mV) 0 8192 INPUT CODE 1654 G02 Gain Error vs Temperature 5.0 OUTPUT PULL-DOWN VOLTAGE (V) 2.5 GAIN ERROR (LSB) VCC – VOUT (V) 0 –2.5 –5.0 –55 –25 65 TEMPERATURE (°C) 5 35 4 UW 95 1654 G04 Differential Nonlinearity (DNL) vs Input Code 2.50 Offset vs Temperature 1.0 1.25 0 –1.25 16383 16383 –2.50 –55 –25 5 35 65 TEMPERATURE (°C) 95 125 1654 G03 Minimum Output Voltage vs Load Current (Output Sinking) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 125 0 0 TA = – 55°C TA = 125°C TA = 25°C Minimum Supply Headroom vs Load Current (Output Sourcing) 1.0 CODE: ALL 1s 0.9 VREFHI = 4.096V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 15 CODE: ALL ZEROS TA = 125°C TA = 25°C TA = – 55°C 10 5 OUTPUT SINK CURRENT (mA) 0 10 5 LOAD CURRENT (mA) 15 1645 G06 1645 G05 1654fb LTC1654 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Logic Input Voltage 3.0 SUPPLY CURRENT (mA) 1.5 0 0 1 3 4 2 LOGIC INPUT VOLTAGE (V) Midscale Glitch—Fast Mode VOUT 10mV/DIV CS/LD 2V/DIV TIME (1µs/DIV) UW Large-Signal Settling—Fast Mode Large-Signal Settling—Slow Mode VOUT 1V/DIV VOUT 1V/DIV CS/LD 2V/DIV CS/LD 2V/DIV 5 1654 G07 TIME (2µs/DIV) 1654 G08 TIME (2µs/DIV) 1654 G09 Midscale Glitch—Slow Mode VOUT Glitch at Power-Up VCC 0.5V/DIV VOUT 10mV/DIV CS/LD 2V/DIV VOUT 50mV/DIV 1654 G10 TIME (1µs/DIV) 1654 G11 TIME (50ms/DIV) 1654 G12 1654fb 5 LTC1654 PI FU CTIO S X1/X1/2 B, X1/X1/2 A (Pins 1, 8): The Gain of 1 or Gain of 1/2 Pin. When this pin is tied to VOUT, the output range will be REFLO to (REFLO + REFHI)/2 (0V to REFHI/2 when REFLO = 0V). When this pin is tied to REFLO, the output range will be REFLO to REFHI (0V to REFHI when REFLO = 0V). These pins should not be left floating. CLR (Pin 2): The Asynchronous Clear Input. SCK (Pin 3): The TTL Level Input for the Serial Interface Clock. SDI (Pin 4): The TTL Level Input for the Serial Interface Data. Data on the SDI pin is latched into the shift register on the rising edge of the serial clock. The LTC1654 allows either a 24-bit or 32-bit word. When a 24-bit word is used, the first 8 bits are control and address followed by 16 data bits. The last two of the 16 data bits are don’t cares. When a 32-bit word (required for daisy-chain operation) is used, the first 8-bits are don’t cares and the following 24-bits are as above. CS/LD (Pin 5): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the SCK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, the control/address bits are decoded. DGND/AGND (Pins 6, 12): Digital and Analog Grounds. SDO (Pin 7): The output of the shift register that becomes valid on the rising edge of the serial clock. VOUT A/B (Pins 9, 15): The Buffered DAC Outputs. REFHI A/B (Pins 10, 14): The Reference High Inputs of the LTC1654. There is a gain of 1 from this pin to the output in a gain of 1 configuration. In a gain of 1/2 configuration, there is a gain of 1/2 from this pin to VOUT. REFLO A/B (Pins 11, 13): The Reference Low Inputs of the LTC1654. These inputs can swing up to VCC – 1.5V. VCC (Pin 16): The Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V. Requires a 0.1µF bypass capacitor to ground. TI I G DIAGRA S t2 t1 SCK t9 SDI X X C3 B0 X X t5 CS/LD t8 SDO X (PREVIOUS WORD) X C3 X X X CURRENT WORD 1654 TD01 6 W U U UW U t6 t4 t3 t7 1654fb 24-BIT DATA STREAM CS/LD SCK 1 2 7 13 14 17 B5 B4 B3 B2 B1 B0 X X 1654TD02a 3 4 10 12 21 23 B10 B9 B8 B7 B6 DATA WORD B12 B11 5 6 8 9 11 18 24 22 16 20 19 B13 15 SDI CONTROL BITS ADDRESS BITS C3 C2 C1 C0 A3 A2 A1 A0 TI I G DIAGRA S W 29 30 31 32 B0 X X B0 X X CURRENT STREAM 1654 TD02b Figure 1a. 24-Bit Load Sequence (for Non-Daisy-Chained Applications) 32-BIT DATA STREAM CS/LD 5 6 7 13 14 17 B13 B12 B11 B10 A2 A1 A0 ADDRESS BITS C0 A3 A2 A1 A0 B13 B12 B11 B10 B9 B8 B7 A3 X X C3 C2 C1 C0 CONTROL BITS X X X C3 C2 C1 8 9 10 12 11 18 16 20 19 15 X 21 B9 22 B8 23 B7 24 B6 25 B5 DATA WORD B6 B5 B4 B3 B2 B1 26 B4 27 B3 28 B2 SCK 1 2 3 4 SDI X X X X X B1 DON’T CARE SDO X X X X X PREVIOUS STREAM t1 t2 SCK 17 t3 SDI B13 t8 SDO PREVIOUS B13 PREVIOUS B12 t4 B12 18 Figure 1b. 32-Bit Load Sequence (for Single and Daisy-Chained LTC1654s) UW LTC1654 1654fb 7 LTC1654 OPERATIO Serial Interface The data on the SDI input is loaded into the shift register on the rising edge of SCK. The MSB is loaded first. The Clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. If no daisy-chaining is required, the input word can be 24-bit wide, as shown in the timing diagrams. The 8 MSBs, which are loaded first, are the control and address bits followed by a 16-bit data word. The last two LSBs in the data word are don’t cares. The input word can be a stream of three 8-bit wide segments as shown in the “24-Bit Update” timing diagram. If daisy-chaining is required or if the input needs to be written in two 16-bit wide segments, then the input word can be 32 bits wide and the top 8 bits (MSBs) are don’t cares. The remaining 24 bits are control/address and data. This is also shown in the timing diagrams. The buffered output of the internal 32-bit shift register is available on the SDO pin, which swings from GND to VCC. Multiple LTC1654s may be daisy-chained together by connecting the SDO pin to the SDI pin of the next IC. The SCK and CS/LD signals remain common to all ICs in the daisy-chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all DACs simultaneously. Table 1 shows the truth table for the control/address bits. When the supplies are first applied, the LTC1654 uses SLOW mode, the outputs are set at 0V, and zeros are loaded into the 32-bit input shift register. About 300ns after power-up, the outputs are released from 0V (AGND) and will go to the voltage on the REFLO pin. When CLR goes active, zeros are loaded into the input and DAC latch and the outputs are forced to AGND. After CLR is forced high, the ouputs will go to the voltage on the REFLO pin. 8 U Three examples are given to illustrate the DAC’s operation: 1. Load and update DAC A in FAST mode. Leave DAC B unchanged. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in FAST mode CS/LD CS/LD CS/LD clock in 0101 0000 XXXXXXXX XXXXXXXX; Step 2: Load and update DAC A with DATA clock in 0011 0000 + DATA; CS/LD 2. Load and update DAC A in SLOW mode. Power down DAC B. Perform the following sequence for the control, address and DATA bits: Step 1: Set DAC A in SLOW mode CS/LD clock in 0110 0000 XXXXXXXX XXXXXXXX; CS/LD Step 2: Load and update DAC A with DATA CS/LD clock in 0011 0000 + DATA; CS/LD Step 3: Power down DAC B CS/LD clock in 0100 0001 XXXXXXXX XXXXXXXX; CS/LD 3. Power down both DACs at the same time. Perform the following sequence for the control, address and DATA bits: Step 1: Power down both DACs simultaneously CS/LD clock in 0100 1111 XXXXXXXX XXXXXXXX; CS/LD 1654fb LTC1654 OPERATIO Voltage Output The LTC1654 comes complete with rail-to-rail voltage output buffer amplifiers. These amplifiers will swing to within a few millivolts of either supply rail when unloaded and to within a 450mV of either supply rail when sinking or sourcing 5mA. There are two GAIN configuration modes for the LTC1654: a) GAIN of 1: (X1/X1/2 tied to REFLO) VOUT = (VREFHI – VREFLO)(CODE/16384) + VREFLO b) GAIN of 1/2: (X1/X1/2 tied to VOUT) VOUT = (1/2)(VREFHI – VREFLO)(CODE/16384) + VREFLO The LTC 1654 has two SPEED modes: A FAST mode and a SLOW mode. When operating in the FAST mode, the output amplifiers will settle in 3µs (typ) to 14 bits on a 4V output swing. In the SLOW mode, they will settle in 8.5µs. U The total supply current is 930µA in the FAST mode and 540µA in the SLOW mode. The output noise voltage density at 10kHz is 170nV/√Hz in SLOW mode and 150nV/√Hz in FAST mode. Power Down Each DAC can also be independently powered down to less than 5µA/DAC of supply current. The reference pin also goes into a high impedance state when the DAC is powered down and the reference current will drop to below 0.1µA. The amplifiers’ output stage is also three-stated but the VOUT pins still have the internal gain-setting resistors connected to them resulting in an effective resistance from VOUT to REFLO. This resistance is typically 90k when the X1/X1/2 pin is tied to VOUT and 36k when X1/X1/2 is tied to REFLO. Because of this resistance, VOUT will go to VREFLO when the DAC is powered down and VOUT is unloaded. 1654fb 9 LTC1654 OPERATIO Table 1. CONTROL C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 INPUT WORD CONTROL C3 C2 C1 C0 A3 ADDRESS A2 A1 A0 D13 D12 D11 D10 D9 DATA (14 + 2 DON'T CARE LSBs) D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1654 TABLE 10 U ADDRESS (n) A3 A2 A1 A0 Load Input Register n Update (Power-Up) DAC Register n Load Input Register n, Update (Power-Up) All Load and Update n Power Down n Fast n (Speed States are Maintained Even If DAC is Put in Power-Down Mode) Slow n (Default State is Slow When Supplies are Powered Up) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) No Operation 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC A DAC B Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Reserved (Do Not Use) Both DACs 1654fb LTC1654 APPLICATIO S I FOR ATIO Rail-to-Rail Output Considerations Rail-to-rail DACs take full advantage of the supply range available to them, but cannot produce output voltages above VCC or below ground. See Figure 2a. If REFLO is tied to GND, the output for the lowest codes may limit at 0V, as shown in Figure 2b. Similarly, limiting can occur near full scale if the REFHI pin is tied to VCC, as shown in Figure 2c. OUTPUT VOLTAGE 0 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1654 F02 Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC GAIN U The offset, gain error and linearity of the LTC1654 are defined and tested in output ranges that avoid limiting. The low code kL used in these measurements is defined as the code which gives a nominal output of 32mV above ground; see Table 2. VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC 8192 INPUT CODE (a) 16383 W UU Table 2. Low Code kL VREFHI, V 4.096 2.048 1 128 256 1/2 256 512 Note: VREFLO = O 1654fb 11 LTC1654 DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits (n). It is also the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): Normally, DAC offset is the voltage at the output when the DAC is loaded with all zeros. The DAC can have a true negative offset, but because the part is operated from a single supply, the output cannot go below 0V. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 3. Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/16383 Nominal LSBs: LTC1654 LSB = 4.09575V/16383 = 250µV Zero-Scale Error (ZSE): The output voltage when the DAC is loaded with all zeros. Since this is a single supply part, this value cannot be less than 0V. Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between low code kL and full scale. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/16383)]/LSB VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal one LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB ∆V OUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in nV • s. OUTPUT VOLTAGE NEGATIVE OFFSET Figure 3. Effect of Negative Offset Therefore, the offset of the part is measured at low code kL: VOUT (kL ) – (kL )( VFS ) 2n – 1 kL ⎞ ⎛ ⎜ 1– n ⎟ ⎝ 2 – 1⎠ VOS = 12 U U 0V DAC CODE 1654 F01 1654fb LTC1654 TYPICAL APPLICATIO S This circuit shows how to use an LTC1654 and an LT®1077 to make a wide bipolar output swing 14-bit DAC with an offset that can be digitally programmed. VOUTA, which can be set by loading the appropriate code for DAC A, sets the offset. As this value changes, the transfer curve for the output moves up and down as illustrated in the graph below. A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset 5V 0.1µF VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A 16 15 14 13 12 11 10 9 49.9k 1% 100k 1% 100k 1% 49.9k 1% 15V µP VOUT U 1 2 3 4 5 6 7 8 LTC1654 X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A + LT1077 VOUT 2 (VOUTB – VOUTA) – –15V 1654 TA02 10 VOUTA ≅ 0V 5 VOUTA ≅ 2.5V 0 VOUTA ≅ 5V –5 16383 CODE –10 1654 TA03 1654fb 13 LTC1654 TYPICAL APPLICATIO S Dual 14-Bit Voltage Output DAC 14 U µP 2.7V TO 5.5V LTC1654 0.1µF 1 2 3 4 5 6 7 8 X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A 16 15 14 13 12 11 10 9 1654 TA01 OUTPUT B: 0V TO VCC OUTPUT A: 0V TO VCC 1654fb LTC1654 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT 1 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0250 TYP .015 ± .004 × 45° (0.38 ± 0.10) 0° – 8° TYP .053 – .068 (1.351 – 1.727) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC GN16 (SSOP) 0502 1654fb 15 LTC1654 TYPICAL APPLICATIO A Wide Swing, Bipolar Output 14-Bit DAC with Digitally Controlled Offset 5V 0.1µF VCC VOUT B REFHI B REFLO B AGND REFLO A REFHI A VOUT A 16 15 14 13 12 11 10 9 49.9k 1% 100k 1% 100k 1% 49.9k 1% 15V µP RELATED PARTS PART NUMBER LTC1257 LTC1446/LTC1446L LTC1448 LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L LTC1658 LTC1659 DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality 14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 5V, Low Power Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC Low Power, Multiplying VOUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC Low Cost, 10ppm Drift Ultralow Drift 3ppm/°C, Initial Accuracy: 0.04% Low Drift 10ppm/°C, Initial Accuracy: 0.05% References LT1460 LT1461 LT1634 Micropower Precision Reference Precision Voltage Reference Micropower Precision Reference 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U LTC1654 1 2 3 4 5 6 7 8 X1/X1/2 B CLR SCK SDI CS/LD DGND SDO X1/X1/2 A + LT1077 VOUT 2 (VOUTB – VOUTA) – –15V 1654 TA02 1654fb LT/LT 0705 REV B • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2000