LTC1662C

Final Electrical Specifications LTC1662 Ultralow Power, Dual 10-Bit DAC in MSOP March 2000 FEATURES s s DESCRIPTIO s s s s s s s Ultralow Power: 1.5µA (Typ) ICC per DAC Plus 0.05µA Sleep Mode for Extended Battery Life Tiny: Two 10-Bit DACs in an 8-Lead MSOP— Half the Size of an SO-8 Wide 2.7V to 5.5V Supply Range Double Buffered for Simultaneous DAC Updates Rail-to-Rail Voltage Outputs Drive 1000pF Reference Range Includes Supply for Ratiometric 0V-to-VCC Output Reference Input Impedance Is Code-Independent (7.1MΩ Typ)—Eliminates External Buffers 3-Wire Serial Interface with Schmitt Trigger Inputs Differential Nonlinearity: ± 0.75LSB Max The LTC®1662 is an ultralow power, fully buffered voltage output, dual 10-bit digital-to-analog converter (DAC). Each DAC draws just 1.7µA (typ) total supply-plusreference operating current, yet is capable of supplying DC output currents in excess of 1mA and reliably driving capacitive loads of up to 1000pF. A programmable Sleep mode further reduces total operating current to a negligible 0.05µA. Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. The double-buffered input logic provides simultaneous update capability and can be used to write to either DAC without interrupting Sleep mode. With its ultralow operating current and exceptionally small size, the LTC1662 is ideal for use in batterypowered products. The LTC1662 is pin- and software-compatible with the LTC1661 micropower dual 10-bit DAC. It is available in 8-pin MSOP and PDIP packages and is specified over the industrial temperature range. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s Mobile Communications Portable Battery-Powered Instruments Remote Industrial Devices Digitally Controlled Amplifiers and Attenuators Automatic Calibration for Manufacturing BLOCK DIAGRA VOUT A 8 GND 7 VCC 6 VOUT B 5 TOTAL OPERATING CURRENT (µA) LATCH LATCH LATCH LATCH 10-BIT DAC A 10-BIT DAC B CONTROL LOGIC ADDRESS DECODER SHIFT REGISTER 1 CS/LD 2 SCK 3 DIN 4 REF 1662 BD Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.5 VREF = VCC TA = 25°C 3.0 3.5 W U Total Supply-Plus-Reference Operating Current CODE = 1023 CODE = 512 CODE = 0 4.0 VCC (V) 4.5 5.0 5.5 1662 G01 1 LTC1662 ABSOLUTE (Note 1) AXI U RATI GS Operating Temperature Range LTC1662C ............................................. 0°C to 70°C LTC1662I ........................................... – 40°C to 85°C Lead Temperature (Soldering, 10 sec)................ 300°C VCC to GND .............................................. – 0.3V to 7.5V Logic Inputs to GND ................................ – 0.3V to 7.5V VOUT A, VOUT B, REF to GND ......... – 0.3V to (VCC + 0.3V) Maximum Junction Temperature ......................... 125°C Storage Temperature Range ................ – 65°C to 150°C PACKAGE/ORDER I FOR ATIO TOP VIEW CS/LD SCK DIN REF 1 2 3 4 8 7 6 5 VOUT A GND VCC VOUT B ORDER PART NUMBER CS/LD 1 LTC1662CMS8 LTC1662IMS8 MS8 PART MARKING LTKB LTKC MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 150°C/W Consult factory for Military grade parts. The q denotes the specifications which apply over the full operating temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded unless otherwise noted. SYMBOL Accuracy Resolution Monotonicity DNL INL VOS VOS TC GE GE TC PSR Differential Nonlinearity Integral Nonlinearity Offset Error VOS Temperature Coefficient Gain Error Gain Error Temperature Coefficient Power Supply Rejection Input Voltage Range Input Resistance Input Capacitance Active Mode Sleep Mode VREF = 2.5V q q q ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS (Note 2) (Note 2) (Note 2) VCC = 5V, VREF = 4.096V, Measured at Code 20 VCC = 5V, VREF = 4.096V Reference Input 0 3.9 7.1 2.5 10 VCC V MΩ GΩ pF 2 U U W WW U W TOP VIEW 8 7 6 5 VOUT A GND VCC VOUT B ORDER PART NUMBER LTC1662CN8 LTC1662IN8 SCK 2 DIN 3 REF 4 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 125°C, θJA = 100°C/W MIN 10 10 TYP MAX UNITS Bits Bits q q q q ± 0.12 ± 0.8 ±5 ± 15 ±1 ± 12 0.18 ± 0.75 ±4 ± 25 ±8 LSB LSB mV µV/°C LSB µV/°C LSB/V q LTC1662 The q denotes the specifications which apply over the full operating temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded unless otherwise noted. SYMBOL VCC ICC PARAMETER Positive Supply Voltage Supply Current CONDITIONS For Specified Performance VCC = 3V (Note 3) VCC = 5V (Note 3) VCC = 3V (Note 3) VCC = 5V (Note 3) q ELECTRICAL CHARACTERISTICS MIN 2.7 TYP MAX 5.5 UNITS V µA µA µA µA µA µA mA mA V/ms V/ms ms ms pF V V Power Supply 3.0 3.5 q q 4.0 4.5 5.0 5.5 0.10 0.18 70 80 Sleep Mode Operating Current Supply Plus Reference Current, VCC = VREF = 5V, (Note 3) q 0.05 DC Performance Short-Circuit Current Low Short-Circuit Current High AC Performance Voltage Output Slew Rate Voltage Output Settling Time Capacitive Load Driving Digital I/O VIH VIL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VIN = GND to VCC (Note 6) q q q q q VOUT = 0V, VCC = VREF = 5V, Code = 1023 (Note 7) VOUT = VCC = VREF = 5V, Code = 0 (Note 7) Rising (Notes 4, 5) Falling (Notes 4, 5) 0.1VFS to 0.9VFS ± 0.5LSB (Notes 4, 5) 0.9VFS to 0.1VFS ± 0.5LSB (Notes 4, 5) q q 5 3 12 10 20 7 0.40 0.75 1000 2.4 2.0 0.8 0.6 ± 0.05 1.5 ± 1.0 V V µA pF TI I G CHARACTERISTICS range, otherwise specifications are at TA = 25°C. PARAMETER DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SCK Low to CS/LD Low CS/LD High to SCK Positive Edge SCK Frequency VCC = 2.7V to 5.5V t1 t2 t3 t4 DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time SYMBOL t1 t2 t3 t4 t5 t6 t7 t9 t11 VCC = 4.5V to 5.5V UW The q denotes the specifications which apply over the full operating temperature MIN q q CONDITIONS TYP 15 – 10 14 14 27 2 – 21 –5 0 MAX UNITS ns ns ns ns ns ns ns ns ns 55 0 30 30 100 30 20 0 20 (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) Square Wave (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) q q q q q q q q q q q q 16.7 75 0 50 50 20 – 10 15 15 MHz ns ns ns ns 3 LTC1662 TI I G CHARACTERISTICS range, otherwise specifications are at TA = 25°C. PARAMETER CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High SCK Low to CS/LD Low CS/LD High to SCK Positive Edge SCK Frequency SYMBOL t5 t6 t7 t9 t11 Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See Figure 2. Note 3: Digital inputs at 0V or VCC. TI I G DIAGRA SCK t9 DIN t5 CS/LD TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) 4 INTEGRAL NONLINEARITY (LSB) 3 2 1 0 –1 –2 –3 –4 0 256 512 CODE 768 1023 1662 G02 DIFFERENTIAL NONLINEARITY (LSB) 4 UW W UW UW The q denotes the specifications which apply over the full operating temperature CONDITIONS (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) Square Wave (Note 6) q q q q q q MIN 150 50 30 0 30 TYP 30 3 – 14 –5 0 MAX UNITS ns ns ns ns ns 10 MHz Note 4: Load is 10kΩ in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS; i.e., codes k = 102 and k = 922. Note 6: Guaranteed by design, not subject to test. Note 7: One DAC output loaded. t1 t2 t3 t4 t6 t11 A3 t7 A2 A1 X1 X0 1662 TD Differential Nonlinearity (DNL) 0.75 0.60 0.40 0.20 0 –0.20 –0.40 –0.60 – 0.80 0 256 512 CODE 768 1023 1662 G03 LTC1662 OPERATIO SCK DIN CS/LD Table 1. DAC Control Functions CONTROL A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 No Change Load DAC A INPUT REGISTER STATUS No Change Load DAC A Load DAC B DAC REGISTER STATUS No Update No Update No Update Reserved Reserved Reserved Reserved Reserved Update Outputs Update Outputs Wake Wake Load Both DAC Regs with Existing Contents of Input Regs. Outputs Update. Part Wakes Up Load Input Reg A. Load DAC Regs with New Contents of Input Reg A and Existing Contents of Reg B. Outputs Update. Part Wakes Up Load Input Reg B. Load DAC Regs with Existing Contents of Input Reg A and New Contents of Reg B. Outputs Update. Part Wakes Up POWER-DOWN STATUS (SLEEP/WAKE) No Change No Change No Change COMMENTS No Operation. Power-Down Status Unchanged (Part Stays In Wake or Sleep Mode) Load Input Register A with Data. DAC Outputs Unchanged. Power-Down Status Unchanged Load Input Register B with Data. DAC Outputs Unchanged. Power-Down Status Unchanged 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 No Change No Change Load DACs A, B with Same 10-Bit Code U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 CONTROL CODE INPUT CODE INPUT WORD W0 (SCK ENABLED) (INSTRUCTION EXECUTED) 1662 F01 DON’T CARE Figure 1. Register Loading Sequence Load DAC B Update Outputs Wake Reserved Reserved No Update No Update Update Outputs Wake Sleep Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC Outputs Reflect Existing Contents of DAC Regs Part Goes to Sleep. Input and DAC Regs Unchanged. DAC Outputs Set to High Impedance State Load Both Input Regs. Load Both DAC Regs with New Contents of Input Regs. Outputs Update. Part Wakes Up 5 LTC1662 PI FU CTIO S CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and the operation(s) specified in the Control code, A3-A0, is (are) performed. CMOS and TTL compatible. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 3): Serial Interface Data Input. Input word data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC. VOUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs. The output range is  1023  0 ≤ VOUTA , VOUTB ≤ VREF    1024  VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. GND (Pin 7): System Ground. DEFI ITIO S Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB where ∆VOUT is the measured voltage difference between two adjacent codes. Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Gain Error (GE): The deviation from the slope of the ideal DAC transfer function, expressed in LSBs at full scale. Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/1024 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. 6 U U U U U LTC1662 OPERATIO Transfer Function The transfer function for the LTC1662 is: k VOUT(IDEAL) =   VREF  1024  where k is the decimal equivalent of the binary DAC input code D9-D0 and VREF is the voltage at REF (Pin 6). Power-On Reset The LTC1662 positively clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin 4) should be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 6) is in transition. Serial Interface See Table 1. The 16-bit Input word consists of the 4-bit Control code, the 10-bit Input code and two don’t-care bits. Table 1. LTC1662 Input Word Input Word A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 Control Code Input Code Don’t Care After the Input word is loaded into the register (see Figure 1), it is internally converted from serial to parallel format. The parallel 10-bit-wide Input code data path is then buffered by two latch registers. The first of these, the Input Register, is used for loading new input codes. The second buffer, the DAC Register, is used for updating the DAC outputs. Each DAC has its own 10-bit Input Register and 10-bit DAC Register. By selecting the appropriate 4-bit Control code (see Table 2) it is possible to perform single operations, such as loading one DAC or changing Power-Down status (Sleep/Wake). U In addition, some Control codes perform two or more operations at the same time. For example, one such code loads DAC A, updates both outputs and Wakes the part up. The DACs can be loaded separately or together, but the outputs are always updated together. Register Loading Sequence See Figure 1. With CS/LD held low, data on the DIN input is shifted into the 16-bit Shift Register on the positive edge of SCK. The 4-bit Control code, A3-A0, is loaded first, then the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each case. Two don’t-care bits, X1 and X0, are loaded last. When the full 16-bit Input word has been shifted in, CS/LD is pulled high, causing the system to respond according to Table 2. The clock is disabled internally when CS/LD is high. Note: SCK must be low when CS/LD is pulled low. Sleep Mode DAC control code 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, the digital circuits remain active while the analog sections are disabled; static power consumption is greatly reduced. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence using control code 1110b (the DAC input code D9-D0 is ignored). To save instruction cycles, the DACs may be prepared with new input codes during Sleep (control codes 0001b and 0010b); then, a single command (1000b) can be used both to wake the part and to update the output values. Alternatively, one DAC may be loaded with a new input code during Sleep; then with just one command, the other DAC is loaded, the part is awakened and both outputs are updated. For example, control code 0001b is used to load DAC A during Sleep. Then Control code 0101b loads DAC B, wakes the part and simultaneously updates both DAC outputs. 7 LTC1662 OPERATIO Voltage Outputs Each of the rail-to-rail output amplifiers contained in the LTC1662 can typically source or sink up to 1mA (VCC = 5V). The outputs swing to within a few millivolts of either supply when unloaded and have an equivalent output resistance of 85Ω (typical) when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF. OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1662 F02 Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC 8 U Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 2b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE = VOS + GE) is positive, the output for the highest codes limits at VCC as shown in Figure 2c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 INPUT CODE (a) 1023 LTC1662 TYPICAL APPLICATIO Using the LTC1258 and the LTC1662 In a Portable Application Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA Li-ION BATTERY INPUT VIN ≥ 4.3V 0.1µF 6 2 LTC1258-4.1 4 1 4.096V 3 2 1 4 REF DIN LTC1662 SCK CS/LD GND 7 1662 F03 U 0.1µF VCC VOUT A 8 0V TO 4.096V (4mV/BIT) VOUT B 5 0V TO 4.096V (4mV/BIT) 9 LTC1662 PACKAGE DESCRIPTIO 0.007 (0.18) 0.021 ± 0.006 (0.53 ± 0.015) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 10 U Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 8 76 5 0.193 ± 0.006 (4.90 ± 0.15) 0.118 ± 0.004** (3.00 ± 0.102) 1 0.040 ± 0.006 (1.02 ± 0.15) 0° – 6° TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) BSC 23 4 0.034 ± 0.004 (0.86 ± 0.102) 0.006 ± 0.004 (0.15 ± 0.102) MSOP (MS8) 1098 LTC1662 PACKAGE DESCRIPTIO 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) U Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 0.100 (2.54) BSC 11 LTC1662 TYPICAL APPLICATIO 3.3V 0.1µF 3.3V 1 2.5V Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA R2 1.1M 0.1µF 3.3V 0.1µF 4 REF 6 VCC R1 COARSE 11k 8 VOUT A 0.1µF 2 8 R1 11k 2 LTC1258-2.5 4 DAC A CS/LD DIN SCK 1 3 2 LTC1662 U1 DAC B 7 GND 1662 F04 RELATED PARTS PART NUMBER LTC1661 LTC1663 LTC1664 LTC1665/LTC1660 LTC1446/LTC1446L LTC1448 LTC1454/LTC1454L LTC1458/LTC1458L LTC1659 DESCRIPTION Dual 10-Bit VOUT DAC in 8-Lead MSOP Package Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V COMMENTS VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, Internal Reference, 60µA VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U – LT1495 3 1 VOUT + 4 5 R2 FINE 1.1M VOUT = VREF CODE A + R1 • CODE B R2 1024 1024 = 2.5V CODE A + 1 • CODE B 100 1024 1024 VOUT B ( ( ) ) 1662i LT/TP 0300 4K • PRINTED IN THE USA © LINEAR TECHNOLOGY CORPORATION 2000