LTC1663IMS8

LTC1663 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface FEATURES s s s s DESCRIPTIO s s s s s s s s Micropower 10-Bit DAC in SOT-23 Low Operating Current: 60µA Ultralow Power Shutdown Mode: 10µA 2-Wire Serial Interface Compatible with SMBus and I2CTM Single 2.7V to 5.5V Operation Selectable Internal Reference or Ratiometric to VCC Buffered True Rail-to-Rail Voltage Output Maximum DNL Error: 0.75LSB Power-On Reset 8 User Selectable Addresses (MSOP Package) 0.6V VIL and 1.4V VIH for SDA and SCL Small 5-Lead SOT-23 and 8-Lead MSOP Packages The LTC®1663 is a 10-bit voltage output DAC with true buffered rail-to-rail output voltage capability. It operates from a single supply with a range of 2.7V to 5.5V. The reference for the DAC is selectable between the supply voltage or an internal bandgap reference. Selecting the internal bandgap reference will set the full-scale output voltage range to 2.5V. Selecting the supply as the reference sets the output voltage range to the supply voltage. The part features a simple 2-wire serial interface compatible with SMBus and I2C that allows communication between many devices. The internal data registers are double buffered to allow for simultaneous update of several devices at once. The DAC can be put in low current power-down mode for use in power conscious systems. Power-on reset ensures the DAC output is at 0V when power is initially applied, and all internal registers are cleared. , LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. APPLICATIO S s s s s s s Digital Calibration Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Arbitrary Function Generators Battery-Powered Data Conversion Products BLOCK DIAGRA 4 (5) VCC 1.25V BANDGAP REFERENCE 1.0 0.8 0.6 0.4 ERROR (LSB) REFERENCE SELECT 10-BIT DAC LATCH + – VOUT 3 (8) MSOP PACKAGE ONLY (6) AD0 (2) AD1 (3) AD2 COMMAND LATCH INPUT LATCH R R 2-WIRE INTERFACE SDA 1 (1) SCL 5 (4) GND 2 (7) 1663 BD NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE U Differential Nonlinearity (DNL) VREF = VCC = 5V TA = 25°C 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 0 28 156 384 512 640 768 896 1024 CODE 1663 G02 W U 1 LTC1663 ABSOLUTE AXI U RATI GS VCC to GND .............................................. – 0.3V to 7.5V SDA, SCL ..................................................– 0.3V to 7.5V AD0, AD1, AD2 (MSOP Only) ...... – 0.3V to (VCC + 0.3V) VOUT ............................................ – 0.3V to (VCC + 0.3V) PACKAGE/ORDER I FOR ATIO TOP VIEW SDA AD1 AD2 SCL 1 2 3 4 8 7 6 5 VOUT GND AD0 VCC ORDER PART NUMBER LTC1663CMS8 LTC1663IMS8 MS8 PART MARKING LTEQ LTJJ MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 150°C/W Consult factory for Military grade parts. The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted. SYMBOL DAC Resolution Monotonicity DNL INL VOS VOSTC FSE VOUT VFSTC PSRR Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Temperature Coefficient Full-Scale Error DAC Output Span Full-Scale Voltage Temperature Coefficient Power Supply Rejection Ratio Reference Set to Internal Bandgap, Code = 1023 q q ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS (Note 2) Guaranteed Monotonic (Note 2) (Note 2) Measured at Code 20 Reference Set to VCC Reference Set to Internal Bandgap Reference Set to VCC Reference Set to Internal Bandgap Power Supply VCC ICC ISD Positive Supply Voltage Supply Current Supply Current in Shutdown Mode Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) Output Impedance to GND VCC = 3V (Note 3) VCC = 5V (Note 3) (Note 3) VOUT Shorted to GND, Input Code = 1023 VOUT Shorted to VCC, Input Code = 0 Input Code = 0, VCC = 5V Input Code = 0, VCC = 3V In Shutdown Mode 2.7 60 75 10 25 30 65 150 500 5.5 100 125 16 100 120 V µA µA µA mA mA Ω Ω kΩ q q q Op Amp DC Performance q q 2 U U W WW U W (Note 1) Operating Temperature Range LTC1663C .............................................. 0°C to 70°C LTC1663I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C TOP VIEW SDA 1 GND 2 VOUT 3 4 VCC 5 SCL ORDER PART NUMBER LTC1663CS5 S5 PART MARKING LTEP S5 PACKAGE 5-LEAD PLASTIC SOT-23 TJMAX = 125°C, θJA = 250°C/W MIN 10 10 TYP MAX UNITS Bits Bits q q q q ± 0.2 ±0.5 ± 10 ± 15 ±3 ±3 0 to VCC 0 to 2.5 ± 30 ±0.4 ± 0.75 ± 2.5 ± 30 ± 15 ± 15 LSB LSB mV µV/°C LSB LSB V V µV/°C LSB/V q q LTC1663 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER Output Impedance to VCC AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital-to-Analog Glitch Impulse Digital Inputs SCL, SDA VIH VIL VLTH ILEAK CIN VOL IUP VIH VIL High Level Input Voltage Low Level Input Voltage Logic Threshold Voltage Digital Input Leakage Digital Input Capacitance Digital Output Low Voltage Address Pin Pull-Up Current High Level Input Voltage Low Level Input Voltage VCC = 5.5V and 0V, VIN = GND to VCC (Note 7) IPULLUP = 350µA VIN = 0V q q q q ELECTRICAL CHARACTERISTICS CONDITIONS Input Code = 1023, VCC = 5V Input Code = 1023, VCC = 3V Rising (Notes 4, 5) Falling (Notes 4, 5) To ± 0.5LSB (Notes 4, 5) 1LSB Change Around Major Carry MIN TYP 80 120 0.75 0.25 30 0.75 70 MAX UNITS Ω Ω V/µs V/µs µs nV • s nV • s V 1.4 0.6 1 ±1 10 0.4 0.5 1.5 0.8 V V µA pF V µA V V Digital Output SDA q q q VCC – 0.3 q Address Inputs AD0, AD1, AD2 (MSOP Only) TI I G CHARACTERISTICS SYMBOL fSMB tBUF tHD, STA tSU, STA tSU, STO tHD, DAT tSU, DAT tLOW tHIGH tf tr PARAMETER SMBus Operating Frequency SMBus Timing Characteristics (Notes 6, 7) The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC set as reference, VOUT unloaded, unless otherwise noted. MIN q q q q q q q q q q q Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined from code 20 to code 1003 (full scale). See Applications Information. Note 3: Digital inputs at 0V or VCC. UW TYP MAX 100 UNITS kHz µs µs µs µs ns ns µs 10 4.7 4.0 4.7 4.0 300 250 4.7 4.0 Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock, Data Fall Time Clock, Data Rise Time 50 300 1000 µs ns ns Note 4: Load is 10kΩ in parallel with 100pF. Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes k = 102 and k = 922. Note 6: All values are referenced to VIH and VIL levels. Note 7: Guaranteed by design and not subject to test. 3 LTC1663 TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 ERROR (LSB) ERROR (LSB) VREF = VCC = 5V TA = 25°C 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 0 28 156 384 512 640 768 896 1024 CODE 1663 G01 OUTPUT VOLTAGE (V) 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 Large-Signal Step Response 5 SDA (VOLTS) 0 5 CODE = 990 4 3 VOUT (VOLTS) 2 1 CODE = 32 0 5µs/DIV 1663 G04 ∆VOUT (LSB) VCC = 5V RL = 4.7k CL = 100pF TA = 25°C Load Regulation vs Output Current 1.0 0.8 0.6 0.4 ∆VOUT (LSB) OFFSET ERROR VOLTAGE (mV) 2 1 0 –1 –2 –3 –4 –5 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 OUTPUT VOLTAGE (V) VCC = VREF = 3V VOUT = 1.5V CODE = 512 TA = 25°C 0.2 0 SOURCE SINK – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –1.0 – 0.8– 0.6– 0.4– 0.2 0 0.2 0.4 0.6 0.8 1.0 IOUT (mA) 1663 G07 4 UW Differential Nonlinearity (DNL) 1.0 0.8 0.6 VREF = VCC = 5V TA = 25°C 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Source and Sink Current Capability with VCC = 5V TA = 25°C DAC CODE = 1023 DAC CODE = 0 0 28 156 384 512 640 768 896 1024 CODE 1663 G02 0 0 1 2 3 4 5 6 7 8 9 10 OUTPUT CURRENT SOURCE/SINK (mA) 1011 G03 Midscale Glitch 1.0 5V SDA 0V CODE = 512 TO 511 0.8 0.6 0.4 0.2 0 Load Regulation vs Output Current VCC = VREF = 5V VOUT = 2.5V CODE = 512 TA = 25°C VOUT 10mV/DIV VCC = 5V RL = 4.7k CL = 100pF TA = 25°C 2µs/DIV 1663 G05 – 0.2 – 0.4 – 0.6 – 0.8 –1.0 –4 –3 –2 –1 0 1 IOUT (mA) 2 3 4 SOURCE SINK 1663 G06 Offset Error Voltage vs Temperature 5 4 3 2.510 2.508 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 Full-Scale Output Voltage vs Temperature REFERENCE SET TO INTERNAL BANDGAP 2.490 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 1663 G08 1663 G09 LTC1663 PIN FUNCTIONS SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. High impedance pin while data is shifted in. Open-drain N-channel output during acknowledgment. Requires a pull-up resistor or current source to VCC. AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to either VCC or GND to modify the corresponding bit of the LTC1663’s slave address. AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to either VCC or GND to modify the corresponding bit of the LTC1663’s slave address. SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. VCC (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ VCC ≤ 5.5V. Also used as the reference voltage input when the part is programmed to use VCC as the reference. AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to either VCC or GND to modify the corresponding bit of the LTC1663’s slave address. GND (Pin 7, Pin 2 on SOT-23): System Ground. VOUT (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered rail-to-rail DAC output. DEFINITIONS Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB Where ∆VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code that guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/1024 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. U U U U U 5 UW LTC1663 tLOW tHD, DAT 1663 TD tHD, STA tBUF tSU, STO SCL tHIGH tr START CONDITION REPEATED START CONDITION STOP CONDITION tf tHD, STA START CONDITION Typical Input Waveform—Programming DAC Output for Full Scale (AD2 to AD0 Set High) STOP 1 0 ACK X X X X X 0 0 0 ACK 1 1 1 1 1 1 1 1 ACK X X X X X X 1 1 ACK START SDA 0 1 0 0 1 1 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 1663 TA02 VOUT NOTE: X = DON’T CARE COMMAND LS DATA MS DATA ADDRESS W 6 TI I G DIAGRA tSU, DAT tSU, STA SDA LTC1663 APPLICATIONS INFORMATION Write Word Protocol Used by the LTC1663 1 S 7 Slave Address 1 Wr 1 A 8 Command Byte 1 A 8 LSData Byte 1 A 8 MSData Byte 1 A 1 P 1663 TA03 S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition Serial Digital Interface The LTC1663 communicates with a host (master) using the standard 2-wire interface. The Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus Accelerator, are required on these lines. The LTC1663 is a receive-only (slave) device. The master can communicate with the LTC1663 using the Quick Command, Send Byte or Write Word protocols as explained later. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another SMBus device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. U W U U Write Word Protocol The master initiates communication with the LTC1663 with a START condition and a 7-bit address followed by the Write Bit (Wr) = 0. The LTC1663 acknowledges and the master delivers the command byte. The LTC1663 acknowledges and latches the command byte into the command byte input register. The master then delivers the least significant data byte. Again the LTC1663 acknowledges and the data is latched into the least significant data byte input register. The master then delivers the most significant data byte. The LTC1663 acknowledges once more and latches the data into the most significant data byte input register. Lastly, the master terminates the communication with a STOP condition. On the reception of the STOP condition, the LTC1663 transfers the input register information to output registers and the DAC output is updated. Slave Address (MSOP Package Only) The LTC1663 can respond to one of eight 7-bit addresses. The first 4 bits (MSBs) have been factory programmed to 0100. The three address bits, AD2, AD1 and AD0 are programmed by the user and determine the LSBs of the slave address, as shown in the table below: AD2 L L L L H H H H AD1 L L H H L L H H AD0 L H L H L H L H 0100 xxx 0100 000 0100 001 0100 010 0100 011 0100 100 0100 101 0100 110 0100 111 7 LTC1663 APPLICATIONS INFORMATION Slave Address (SOT-23 Package) The slave address for the SOT-23 package has been factory programmed to be “0100 000.” If another address is required, please consult the factory. Command Byte 7 X SY SD 1 0 1 0 1 0 X 6 X 5 X 4 X 3 X 2 BG 1 SD 0 SY Allows update on Acknowledge of SYNC Address only Update on Stop condition only (Power-On Default) Puts the device in power-down mode Puts the device in standard operating mode (Power-On Default) Selects the internal bandgap reference Selects the supply as the reference (Power-On Default) Don’t Care BG X The stop condition normally initiates the update of the DAC’s output latches. This allows for simultaneous update of more than one DAC or other devices on the bus. This can be overridden by setting the “SY” bit of the command byte. Setting this bit sets the device to update the DAC output latches at the reception of a SYNC address quick command. The actual update occurs on the rising edge of SCL during the Acknowledge. In this way, all devices can update on the reception of the SYNC address quick command instead of the STOP condition. A Shutdown (SD) bit = HIGH will put the device in a low power state but retain all data latch information. Shutdown will occur at the reception of a STOP condition. This way shutdown could be synchronized to other devices. The output impedance of the DAC will go to a high impedance state (≈ 500kΩ to GND). 8 U W U U The Bandgap (BG) bit when set to “0” selects the DAC supply voltage as its voltage reference. The full-scale output of the DAC with this setting is equal to the supply voltage. When the BG bit is set to “1,” the internal bandgap reference (≈ 1.25V) is selected as the DAC’s reference. The full-scale output voltage for this setting is 2.5V. Data Bytes Least Significant Data Byte 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Most Significant Data Byte 7 X 6 X 5 X 4 X 3 X 2 X 1 D9 0 D8 X = Don’t care Send Byte Protocol The Send Byte protocol used on the LTC1663 is actually a subset of the Write Word protocol described previously. The Send Byte protocol can only be used to send the command byte information to the LTC1663. 1 S 7 Slave Address 1 Wr 1 A 8 Command Byte 1 A 1 P 1663 TA04 S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition The Send Byte protocol is also used whenever the Write Word protocol is interrupted for any reason. Reception of a START or STOP condition after the Acknowledge of the command byte, but before the Acknowledge of the last data byte, will cause both data bytes to be ignored and the command byte to be accepted. Reception of a START or STOP condition before the Acknowledge of the command byte will cause the interrupted command byte to be ignored. LTC1663 APPLICATIONS INFORMATION SYNC Address/Quick Command In addition to the slave address, the LTC1663 has an address that can be shared by other devices so that they may be updated synchronously. The address is called to the SYNC address and uses the quick command protocol. The SYNC Address is 1111 110 1 Start 7 1111 110 SYNC Address 1 SY/CLR 1 Ack 1 Stop 1663 TA05 SY/CLR 1 0 Update output latches on rising edge of SCL during Acknowledge of SYNC Address Clear all internal latches on rising edge of SCL during Acknowledge of SYNC Address The SY/CLR bit set high only has meaning when the “SY” bit of the command byte was previously set HIGH. On the otherhand, the SY/CLR bit set LOW will always clear the part, independent of the state of the “SY” bit in the command byte. Input Threshold Anticipating the trend toward lower supply voltages, the SMBus is specified with a VIH of 1.4V and a VIL of 0.6V. While some SMBus parts may violate this stringent SMBus specification by allowing a higher VIH value for a correspondingly higher input supply voltage, the LTC1663 meets and maintains the constant SMBus input threshold specification across the entire supply voltage range of 2.7V to 5.5V. The logic input threshold is designed to be 1V with 50mV of hysteresis. Voltage Output The output amplifier contained in the LTC1663 can source or sink up to 5mA. The output stage swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 85Ω when driving a load to the rails. The output amplifier is stable driving capacitive loads up to 1000pF. U W U U A small resistor placed in series with the output can be used to achieve stability for any load capacitance greater than 1000pF. For example, a 0.1µF load can be driven by the LTC1663 if a 110Ω series resistance is used. The phase margin of the resulting circuit is 45° and increases monotonically from this point if larger values of resistance, capacitance or both are substituted for the values given. Rail-to-Rail Output Considerations As in any rail-to-rail device, the output is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1b. Similarly, limiting can occur near full scale when VCC is used as the reference. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 1c. No full-scale limiting can occur if the internal reference is used. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Internal Reference In applications where a predictable output is required that is independent of supply voltage, the LTC1663 has a userselectable internal reference. Selecting the internal reference will set the full-scale output voltage to 2.5V. This can be useful in applications where the supply voltage is poorly regulated. Using the LT®1460 Micropower Series Reference as a Power Supply for the LTC1663 In applications where the advantages of using the internal reference are required but the full-scale range needs to be greater than 2.5V, an external series reference can be used. The LT1460 is ideal for use as a power supply for the LTC1663 and can provide 3V, 3.3V and 5V full-scale output voltage ranges. The LT1460 provides accuracy, noise immunity and extended supply range to the LTC1663 when the LTC1663 is operated ratiometric to VCC. Since both parts are available in SOT-23 packages, the PC board space for this application is extremely small. See Figure 2. 9 LTC1663 APPLICATIONS INFORMATION VREF = VCC POSITIVE FSE OUTPUT VOLTAGE 0 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1663 F01 Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC 3.9V TO 20V 0.1µF 1 IN LT1460S3-3 2 OUT + GND 3 5 (4) TO µP 1 (1) LTC1663 PIN NUMBERS IN PARENTHESES REFER TO MSOP PACKAGE Figure 2. LT1460 As Power Supply for the LTC1663 10 U W U U OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC 512 INPUT CODE (a) 1023 3V 0.01µF 4 (5) VCC SCL SDA GND 2 (7) 1663 F02 LTC1663 OUT 3 (8) 0V ≤ VOUT ≤ 3V LTC1663 PACKAGE DESCRIPTION 0.007 (0.18) 0.021 ± 0.006 (0.53 ± 0.015) 0° – 6° TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) BSC 0.193 ± 0.006 (4.90 ± 0.15) 0.118 ± 0.004** (3.00 ± 0.102) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.35 – 0.55 (0.014 – 0.022) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DIMENSIONS ARE INCLUSIVE OF PLATING 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 4. MOLD FLASH SHALL NOT EXCEED 0.254mm 5. PACKAGE EIAJ REFERENCE IS SC-74A (EIAJ) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 0.040 ± 0.006 (1.02 ± 0.15) 0.034 ± 0.004 (0.86 ± 0.102) 8 76 5 0.006 ± 0.004 (0.15 ± 0.102) MSOP (MS8) 1098 1 23 4 S5 Package 5-Lead Plastic SOT-23 (LTC DWG # 05-08-1633) 2.80 – 3.00 (0.110 – 0.118) (NOTE 3) 2.60 – 3.00 (0.102 – 0.118) 1.50 – 1.75 (0.059 – 0.069) 1.90 (0.074) REF 0.00 – 0.15 (0.00 – 0.006) 0.95 (0.037) REF 0.90 – 1.45 (0.035 – 0.057) 0.09 – 0.20 (0.004 – 0.008) (NOTE 2) 0.35 – 0.50 0.90 – 1.30 (0.014 – 0.020) (0.035 – 0.051) FIVE PLACES (NOTE 2) S5 SOT-23 0599 11 LTC1663 TYPICAL APPLICATION Program Up to 8 Control Outputs Per BUS and Place Them Where They Are Needed VCC = 2.7V TO 5.5V 1 VCC SMBus 1 LTC1694 SMBus 2 GND 2 SCL µP SDA RELATED PARTS PART NUMBER LTC1694 LTC1694-1 DACs LTC1659 LTC1660/LTC1664 LTC1661 ADCs LTC1285/LTC1288 LTC1286/LTC1298 LTC1594/LTC1598 8-Pin SO, 3V Micropower ADCs 8-Pin SO, 5V Micropower ADCs 4/8-Channel, 5V Micropower 12-Bit ADCs 1- or 2-Channel, Autoshutdown 1- or 2-Channel, Autoshutdown Low Power, Small Size, Low Cost 1663f LT/TP 0300 4K • PRINTED IN THE USA DESCRIPTION SMBus I2C Accelerator SMBus I2C Accelerator Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package. VCC = 2.7V to 5.5V Octal/Quad 10-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface. Dual 10-Bit VOUT in 8-Lead MSOP Package VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface. 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U 5 4 + 0.1µF + 5 4 VCC SCL 1 SDA LTC1663CMS8 8 6 VOUT AD0 2 AD1 3 AD2 GND 7 0.1µF CONTROL OUTPUT 0 0V ≤ VOUT0 < VCC 5 4 SCL 1 SDA 6 AD0 2 AD1 3 AD2 VCC LTC1663CMS8 VOUT + 8 0.1µF CONTROL OUTPUT 1 0V ≤ VOUT1 < VCC GND 7 5 4 SCL 1 SDA 6 AD0 2 AD1 3 AD2 TO OTHER SMBus DEVICES + 8 VCC LTC1663CMS8 VOUT 0.1µF CONTROL OUTPUT 7 0V ≤ VOUT7 < VCC GND 7 1663 TA06 COMMENTS Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources Dual SMBus Accelerator with Active AC Pull-Up Current Only Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC. 3-Wire Interface. © LINEAR TECHNOLOGY CORPORATION 1999