LTC1665/LTC1660 Micropower Octal 8-Bit and 10-Bit DACs DESCRIPTIO
The 8-bit LTC®1665 and 10-bit LTC1660 integrate eight accurate, serially addressable digital-to-analog converters (DACs) in tiny 16-pin narrow SSOP packages. Each buffered DAC draws just 56µA total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads to 1000pF. Sleep mode further reduces total supply current to 1µA. Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1665 and LTC1660 ideal for battery-powered applications, while their ease of use, high performance and wide supply range make them excellent choices as general purpose converters.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
s s
s s s s
s
Tiny: 8 DACs in the Board Space of an SO-8 Micropower: 56µA per DAC Plus 1µA Sleep Mode for Extended Battery Life Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660 Wide 2.7V to 5.5V Supply Range Rail-to-Rail Voltage Outputs Drive 1000pF Reference Range Includes Supply for Ratiometric 0V-to-VCC Output Reference Input Impedance is Constant— Eliminates External Buffer
APPLICATIO S
s s s s s
Mobile Communications Remote Industrial Devices Automatic Calibration for Manufacturing Portable Battery-Powered Instruments Trim/Adjust Applications
BLOCK DIAGRA
GND 1
LTC1665 Differential Nonlinearity (DNL)
0.5
16 VCC
0.4 0.3 0.2
VCC = 5V VREF = 4.096V
VOUT A
2
DAC A
DAC H
15 VOUT H
LSB
0.1 0 –0.1 –0.2
VOUT B
3
DAC B
DAC G
14 VOUT G
–0.3 –0.4 –0.5 0 64 128 CODE 192 255
1665/60 G09
VOUT C
4
DAC C
DAC F
13 VOUT F
LTC1660 Differential Nonlinearity (DNL)
1
VOUT D
5
DAC D
DAC E
12 VOUT E
0.8 0.6 0.4
VCC = 5V VREF = 4.096V
REF
6 CONTROL LOGIC ADDRESS DECODER
11
CLR
0.2
LSB
0 –0.2 –0.4
CS/LD
7
10
DOUT
SCK
8
SHIFT REGISTER
9
DIN
–0.6 –0.8 –1 0 256 512 CODE 768 1023
1665/60 G13
1665/60 BD
U
W
U
1
LTC1665/LTC1660 ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VOUT A VOUT B VOUT C VOUT D REF CS/LD SCK 1 2 3 4 5 6 7 8 16 VCC 15 VOUT H 14 VOUT G 13 VOUT F 12 VOUT E 11 CLR 10 DOUT 9 DIN
VCC to GND .............................................. – 0.2V to 7.5V Logic Inputs to GND ................................ – 0.2V to 7.5V VOUT A, VOUT B…VOUT H, REF to GND ................................. – 0.2V to (VCC + 0.2V) Maximum Junction Temperature ......................... 125°C Operating Temperature Range LTC1665C/LTC1660C ............................ 0°C to 70°C LTC1665I/LTC1660I .......................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C
ORDER PART NUMBER LTC1665CGN LTC1665CN LTC1665IGN LTC1665IN LTC1660CGN LTC1660CN LTC1660IGN LTC1660IN GN PART MARKING 1665 1665I 1660 1660I
GN PACKAGE 16-LEAD PLASTIC SSOP
N PACKAGE 16-LEAD PDIP
TJMAX = 125°C, θJA = 150°C/W (GN) TJMAX = 125°C, θJA = 100°C/W (N)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL Accuracy Resolution Monotonicity DNL INL VOS FSE PSR Differential Nonlinearity Integral Nonlinearity Offset Error VOS Temperature Coefficient Full-Scale Error Full-Scale Error Temperature Coefficient Power Supply Rejection VREF = 2.5V VCC = 5V, VREF = 4.096V VREF ≤ VCC – 0.1V (Note 2) VREF ≤ VCC – 0.1V (Note 2) VREF ≤ VCC – 0.1V (Note 2) (Note 7)
q q q q q q q q
PARAMETER
CONDITIONS
MIN 8 8
LTC1665 TYP MAX
MIN 10 10
LTC1660 TYP MAX
UNITS Bits Bits
± 0.1 ± 0.2 ± 10 ± 15 ±1 ± 30 0.045
± 0.5 ± 1.0 ± 30 ±4
± 0.2 ± 0.6 ± 10 ± 15 ±3 ± 30 0.18
± 0.75 ± 2.5 ± 30 ± 15
µV/°C LSB µV/°C LSB/V
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current Positive Supply Voltage Supply Current Power Supply For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) Sleep Mode (Note 3)
q q q q
CONDITONS
q
MIN 0 35
TYP
MAX VCC
UNITS V kΩ pF
Reference Input Not in Sleep Mode (Note 6) Sleep Mode
q q
65 15 0.001 1 5.5 450 340 1 730 550 3
2.7
2
U
LSB LSB mV µA V µA µA µA
W
U
U
WW
W
LTC1665/LTC1660
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Short-Circuit Current Low Short-Circuit Current High AC Performance Voltage Output Slew Rate Voltage Output Settling Time Capacitive Load Driving Digital I/O VIH VIL VOH VOL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V IOUT = – 1mA, DOUT Only IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 6)
q q q q q q q q
CONDITIONS VOUT = 0V, VCC = 5.5V, VREF = 5.1V, Code = Full Scale VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0 Rising (Notes 4, 5) Falling (Notes 4, 5) To ± 0.5LSB (Notes 4, 5)
q q
MIN 10 10
TYP 30 27 0.60 0.25 30 1000
MAX 100 120
UNITS mA mA V/µs V/µs µs pF V V
DC Performance
2.4 2.0 0.8 0.6 VCC – 1 0.4 ± 10 10
V V V V µA pF
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 PARAMETER DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High DOUT Propagation Delay SCK Low to CS/LD Low CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6) (Note 6) Continuous Square Wave (Note 6) Continuous 23% Duty Cycle Pulse (Note 6) Gated Square Wave (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CONDITIONS
q q q q q q q q q q q q q q
TI I G CHARACTERISTICS
VCC = 4.5V to 5.5V 40 0 30 30 80 30 80 5 20 100 30 15 –11 5 7 30 4 26 26 0 37 0 5.00 7.69 16.7 60 0 50 50 100 20 –14 8 12 30 80 ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns
VCC = 2.7V to 5.5V t1 t2 t3 t4 t5 DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width
q q q q q
UW
MIN
TYP
MAX
UNITS
3
LTC1665/LTC1660
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL t6 t7 t8 t9 t10 t11 PARAMETER LSB SCK High to CS/LD High CS/LD Low to SCK High DOUT Propagation Delay SCK Low to CS/LD Low CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency CONDITIONS (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6) (Note 6) Continuous Square Wave (Note 6) Continuous 28% Duty Cycle Pulse Gated Square Wave
q q q q q q q q q
TI I G CHARACTERISTICS
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined from code 4 to code 255 for the LTC1665 and from code 20 to code 1023 for the LTC1660. See Applications Information. Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10kΩ in parallel with 100pF.
TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Output Voltage vs Load Current
3 2.9 2.8 2.7 VCC = 5.5V 2.6 2.5 2.4 2.3 2.2 2.1 2 –30 –20 SOURCE –10 SINK 20 30 VCC = 4.5V VCC = 5V VREF = VCC CODE = 128 (LTC1665) CODE = 512 (LTC1660) 2 1.9 1.8 1.7
VOUT (V)
VOUT (V)
4
UW
UW
MIN 50 100 5 30 120 30
TYP 5 27 47 0 41 0
MAX
UNITS ns ns
150
ns ns ns ns
3.85 5.55 10
MHz MHz MHz
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS, i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the LTC1660. Note 6: Guaranteed by design and not production tested. Note 7: Measured at code 4 for the LTC1665 and code 20 for the LTC1660.
(LTC1665/LTC1660) Midscale Output Voltage vs Load Current
VREF = VCC CODE = 128 (LTC1665) CODE = 512 (LTC1660) VCC = 3.6V VCC = 3V
1.6 1.5 1.4 1.3 1.2 1.1 1 –15 –12 –8 SOURCE SINK 8 12 15
1665/60 G02
VCC = 2.7V
0 10 IOUT (mA)
–4 0 4 IOUT (mA)
1665/60 G01
LTC1665/LTC1660 TYPICAL PERFOR A CE CHARACTERISTICS (LTC1665/LTC1660)
Minimum Supply Headroom vs Load Current (Output Sourcing)
1400 1200 1000 VREF = 4.096V ∆VOUT < 1LSB CODE = 255 (LTC1665) CODE = 1023 (LTC1660) 125°C 1400 1200 1000
VCC – VOUT (mV)
800 600
VOUT (mV)
400 200 0 0 2
|
4 6 IOUT (mA) (Sourcing)
Large-Signal Step Response
5 VCC = VREF = 5V 10% TO 90% STEP
SUPPLY CURRENT (µA)
4
440 420 400 380 360 340 320
VCC = 4.5V VCC = 3.6V
VOUT (V)
3
SUPPLY CURRENT (mA)
2
1
0 0 20 40 60 TIME (µs) 80 100
1665/60 G05
TYPICAL PERFOR A CE CHARACTERISTICS (LTC1665)
Integral Nonlinearity (INL)
1 0.8 0.6 0.4 0.2
LSB LSB
VCC = 5V VREF = 4.096V
0 –0.2 –0.4 –0.6 –0.8 –1 0 64 128 CODE 192 255
1665/60 G08
UW
UW
|
Minimum VOUT vs Load Current (Output Sinking)
VCC = 5V CODE = 0 125°C
25°C –55°C
800 600
25°C –55°C
400 200 0 8 10
1665/60 G03
0
2
|IOUT| (mA) (Sinking)
4
6
8
10
1665/60 G04
Supply Current vs Temperature
500 480 460 VCC = 5.5V 1.6 2
Supply Current vs Logic Input Voltage
ALL DIGITAL INPUTS SHORTED TOGETHER
1.2
0.8
VCC = 2.7V
0.4
300 –55 –35 –15
0 5 25 45 65 85 105 125 TEMPERATURE (°C)
1665/60 G06
0
1 2 3 4 LOGIC INPUT VOLTAGE (V)
5
1665/60 G07
Differential Nonlinearity (DNL)
0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 64 128 CODE 192 255
1665/60 G09
VCC = 5V VREF = 4.096V
5
LTC1665/LTC1660 TYPICAL PERFOR A CE CHARACTERISTICS (LTC1665)
Load Regulation vs Output Current
0.5 VCC = VREF = 5V CODE = 128 0.5
0.25
∆VOUT (LSB)
∆VOUT (LSB)
0
–0.25
–0.5 –2
SOURCE –1 0 IOUT (mA)
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
2.5 2.0 1.5 1.0 0.5 VCC = 5V VREF = 4.096V
LSB
0 – 0.5 –1.0 –1.5 – 2.0 – 2.5 0 256 512 CODE 768 1023
1665/60 G12
LSB
Load Regulation vs Output Current
2 1.5 1
∆VOUT (LSB)
VCC = VREF = 5V CODE = 512
0.5 0 –0.5 –1 –1.5 –2 –2 SOURCE –1 0 IOUT (mA) SINK 1 2
1665/60 G14
∆VOUT (LSB)
6
UW
UW
Load Regulation vs Output Current
VCC = VREF = 3V CODE = 128
0.25
0
–0.25
SINK 1 2
1665/60 G10
–0.5 –500
SOURCE 0 IOUT (µA)
SINK 500
1665/60 G11
(LTC1660)
Differential Nonlinearity (DNL)
1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 256 512 CODE 768 1023
1665/60 G13
VCC = 5V VREF = 4.096V
Load Regulation vs Output Current
2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 –500 SOURCE 0 IOUT (µA) SINK 500
1665/60 G15
VCC = VREF = 3V CODE = 512
LTC1665/LTC1660
PIN FUNCTIONS
GND (Pin 1): System Ground. VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Outputs. The output range is
255 0 to V for the LTC1665 256 REF 1023 0 to V for the LTC1660 1024 REF
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible.
BLOCK DIAGRA
VOUT A
VOUT B
VOUT C
VOUT D
W
U
U
U
(LTC1665/LTC1660)
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. DOUT (Pin 10): Serial Interface Data Output. Data appears on DOUT 16 positive SCK edges after being applied to DIN. May be tied to DIN of another LTC1665/LTC1660 for daisychain operaton. CMOS and TTL compatible. CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible. VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND
1
16 VCC
2
DAC A
DAC H
15 VOUT H
3
DAC B
DAC G
14 VOUT G
4
DAC C
DAC F
13 VOUT F
5
DAC D
DAC E
12 VOUT E
REF
6 CONTROL LOGIC ADDRESS DECODER
11
CLR
CS/LD
7
10
DOUT
SCK
8
SHIFT REGISTER
9
DIN
1665/60 BD
7
LTC1665/LTC1660 TI I G DIAGRA
SCK t9 DIN t5 CS/LD t8 DOUT A3 A2 A1 X1 X0 A3
1665/60 F01
OPERATIO
Transfer Function The transfer function is
k VOUT(IDEAL) = V for the LTC1665 256 REF k VOUT(IDEAL) = V for the LTC1660 1024 REF
where k is the decimal equivalent of the binary DAC input code and VREF is the voltage at REF (Pin 6). Power-On Reset The LTC1665 clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range – 0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition.
8
W
t1 t2 t3 t4 t6 t11 A3 t7 A2 A1 X1 X0
U
UW
Figure 1
Serial Interface Referring to Figure 2a (2b): With CS/LD held low, data on the DIN input is shifted into the 16-bit shift register on the positive edge of SCK. The 4-bit DAC address, A3-A0, is loaded first (see Table 2), then the 8-bit (10-bit) input code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case. Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last. When the full 16-bit input word has been shifted in, CS/LD is pulled high, loading the DAC register with the word and causing the addressed DAC output(s) to update. The clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low. The buffered serial output of the shift register is available on the DOUT pin, which swings from GND to VCC. Data appears on DOUT 16 positive SCK edges after being applied to DIN. Multiple LTC1665/LTC1660’s can be controlled from a single 3-wire serial port (i.e., SCK, DIN and CS/LD) by using the included “daisy-chain” facility. A series of m chips is configured by connecting each DOUT (except the last) to DIN of the next chip, forming a single 16m-bit shift register. The SCK and CS/LD signals are common to all
LTC1665/LTC1660
OPERATIO
SCK
DIN
CS/LD
(ENABLE CLK)
DOUT
SCK
DIN
CS/LD
(ENABLE CLK)
DOUT
Table 1a. LTC1665 Input Word
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0 Address/Control Input Code Don’t Care
Table 1b. LTC1660 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 Address/Control Input Code Don’t Care
U
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0 ADDRESS/CONTROL INPUT CODE INPUT WORD W0 (UPDATE OUTPUT) DON’T CARE A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0 A3 INPUT WORD W–1 INPUT WORD W0
1665/60 F02a
Figure 2a. LTC1665 Register Loading Sequence
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
ADDRESS/CONTROL
INPUT CODE INPUT WORD W0
DON’T CARE
(UPDATE OUTPUT)
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
A3
INPUT WORD W–1
INPUT WORD W0
1665/60 F02b
Figure 2b. LTC1660 Register Loading Sequence
chips in the chain. In use, CS/LD is held low while m 16-bit words are clocked to DIN of the first chip; CS/LD is then pulled high, updating all of them simultaneously. Sleep Mode DAC address 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, the digital interface stays active while the analog circuits are disabled; static power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance
9
LTC1665/LTC1660
OPERATIO
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC STATUS No Change Load DAC A Load DAC B Load DAC C Load DAC D Load DAC E Load DAC F Load DAC G Load DAC H No Change No Change No Change No Change No Change No Change Load ALL DACs with Same 8/10-Bit Code SLEEP STATUS Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Wake Sleep Wake
state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence to address 1110b (the DAC input word D7-D0 [D9-D0] is ignored). Once in Sleep mode, a load sequence to any other address (including “No Change” addresses 0000b and 1001-1101b) causes the LTC1665/LTC1660 to Wake. It is possible to keep one or more chips of a daisy chain in continuous Sleep mode by giving the Sleep instruction to these chips each time the active chips in the chain are updated.
10
U
Voltage Outputs Each of the eight rail-to-rail output amplifiers contained in these parts can source or sink up to 5mA. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85Ω when driving a load to the rails. The output amplifiers are stable driving capacitive loads up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A 1µF load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case, larger values of resistance, capacitance or both may be safely substituted for the values given. Rail-to-Rail Output Considerations In any rail-to-rail output voltage DAC, the output is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
LTC1665/LTC1660
OPERATIO
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1665/60 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
U
VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 128 INPUT CODE (a) 255
11
LTC1665/LTC1660
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
3.3V R1 0.1µF 4 2 GND R1 COARSE V OUT A U1 LTC1665 R2 0.1µF
1 VOUT1
U2A LT®1491 11
2
DAC A
DAC H
15
0.1µF R1 6 R1 COARSE VOUT C R1 COARSE R2 R2 FINE VOUT B VOUT G R2 FINE R2
0.1µF R1 9
3
DAC B
DAC G
14
7 VOUT2
U2B LT1491
4
DAC C
DAC F
13
0.1µF 3.3V 2 LTC1258-2.5 4 CS/LD 7 1 REF 6 CONTROL LOGIC ADDRESS DECODER 11 CLR 0.1µF R2 FINE VOUT D VOUT E R2 FINE
0.1µF
5
DAC D
DAC E
12
10
DOUT
TO OTHER LTC1665s
3-WIRE SERIAL INTERFACE
SCK
8
SHIFT REGISTER
9
DIN
1665/60 TA01
R2 >> R1 VOUT 1 = VOUT A + R1 VOUT B R2 Similarly VOUT 2, VOUT 3, VOUT 4 Example: For R1 = 110Ω and R2 = 11k, VOUT 1 = VOUT A + 0.01 VOUT B
))
12
+
5
VOUT F
10
+
3
VOUT H
R1 COARSE
12
–
–
1
U
3.3V
R2 16 VCC 13
R1
– – + +
U2D LT1491
14 VOUT4
U2C LT1491
8 VOUT3
LTC1665/LTC1660
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
5V R 0.1µF VS+ 4 VOUT A ′ 1 0.1µF 11 VS– R 6 U2A LT1491 R 0.1µF VS+ U1 LTC1660 VCC R R 0.1µF
± 5V
2
DAC A
DAC H
15
R
R 6
VOUT B ′
7
± 5V
U2B LT1491
3
DAC B
DAC G
14
R 9
R
R 9
VOUT C ′
8
± 5V
U2C LT1491
4
DAC C
DAC F
13
R 13
R
R 13
VOUT D ′
14
± 5V
U2D LT1491
5
DAC D
DAC E
12
REF
6 CONTROL LOGIC ADDRESS DECODER
11
CLR
CS/LD
7
10
DOUT DIN
3-WIRE SERIAL INTERFACE
CLK
8
SHIFT REGISTER
9
1665/60 TA01
+
12
VOUT D
VOUT E
12
+
10
VOUT C
VOUT F
10
+
5
VOUT B
VOUT G
5
+
3
VOUT A
VOUT H
3
–
2
GND
–
–
–
U
1
16
2
4 U3A LT1491 1 11 0.1µF VS– R VOUT H ′
± 5V
– – – – + + + +
U3B LT1491
7
VOUT G ′
± 5V
R
U3C LT1491
8
VOUT F ′
± 5V
R
U3D LT1491
14
VOUT E ′
± 5V
CODE VOUT X – 5V 0 0V 512 1023 +4.99V
13
LTC1665/LTC1660
PACKAGE DESCRIPTION
0.007 – 0.0098 (0.178 – 0.249) 0.016 – 0.050 (0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
14
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9
0.009 (0.229) REF
0.229 – 0.244 (5.817 – 6.198)
0.150 – 0.157** (3.810 – 3.988)
1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0° – 8° TYP 0.053 – 0.068 (1.351 – 1.727)
23
4
56
7
8 0.004 – 0.0098 (0.102 – 0.249)
0.008 – 0.012 (0.203 – 0.305)
0.0250 (0.635) BSC
GN16 (SSOP) 1098
LTC1665/LTC1660
PACKAGE DESCRIPTION U
Dimensions in inches (millimeters) unless otherwise noted.
N Package 16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.255 ± 0.015* (6.477 ± 0.381)
1
2
3
4
5
6
7
8
0.300 – 0.325 (7.620 – 8.255)
0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN
0.045 – 0.065 (1.143 – 1.651)
0.009 – 0.015 (0.229 – 0.381)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076)
(
+0.035 0.325 –0.015 8.255 +0.889 –0.381
)
0.100 (2.54) BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N16 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1665/LTC1660
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
5V 0.1µF
11 CLR
16 VCC U1 LTC1660
DAC H
DAC G
DAC F
DAC E CS/LD DIN SCK 7 9 8 GND 1
Note: DACs E Through H Can Be Configured for a Second Pin Driver With U2C and U2D of the LT1369
RELATED PARTS
PART NUMBER LTC1661 LTC1663 LTC1446/LTC1446L LTC1448 LTC1454/LTC1454L LTC1458/LTC1458L LTC1590 LTC1659 LT1460 DESCRIPTION Dual 10-Bit VOUT DAC in 8-Lead MSOP Package Single 10-Bit VOUT DAC in SOT-23 Package Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 12-Bit IOUT DAC in SO-16 Package Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V Micropower Precision Series Reference, 2.5V, 5V, 10V Versions COMMENTS VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output VCC = 2.7V to 5.5V, Internal Reference, 60µA LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 4.5V to 5.5V, 4-Quadrant Multiplication Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
166560f LT/TP 0999 4K • PRINTED IN THE USA
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
6 REF VH (FROM MAIN DAC) RG VA 50k RF 5k 3 10V 0.1µF VH′ VL′
DAC A
2
+ U2A –
LT1369 QUAD
1
VH′ = VH + ∆VH 0.1µF
2 RG VB 50k
DAC B
3
– 5V
0.1µF RF 5k VH VL VOUT
VL (FROM MAIN DAC) RG VC 50k RF 5k 5
DAC C
4
+ U2B –
LT1369 QUAD
7
VL′ = VL + ∆VL 0.1µF
PIN DRIVER (1 OF 2)
6 RG VD 50k
RF 5k
1665/60 TA03
LOGIC DRIVE
DAC D
5
VA = VC = 2.5V VH′ = VH + RF (V – V ) B RG A VL′ = VL + RF (V – V ) D RG C For Resistor Values Shown: Adjustment Range = ± 250mV Adjustment Step Size = 500µV
CODE A CODE B ∆VH, ∆VL 512 1023 – 250mV 512 0 512 512 + 250mV 0
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