LTC1695

LTC1695 SMBus/I2C Fan Speed Controller in SOT-23 FEATURES s s DESCRIPTIO s s s s s Complete SMBus/I2CTM Brushless DC Fan Speed Control System in a 5-Pin SOT-23 package 0.75Ω PMOS Linear Regulator with 180mA Output Current Rating 0V to 4.922V Output Voltage Range Controlled by a 6-Bit DAC Simple 2-Wire SMBus/I2C Interface 250ms Internal Timer Ensures Fan Start-Up Current Limit and Thermal Shutdown Fault Status Indication via SMBus Host Readback The LTC®1695 fan speed controller provides all the functions necessary for a power management microprocessor to regulate the speed of a 5V brushless DC fan via a 2-wire SMBus/I2C interface. Fan speed is controlled according to the system’s required temperature profile and permits lower fan power consumption, longer battery run time and lower acoustical generated noise versus systems that only provide simple on-off control for the fan. The LTC1695 incorporates a 180mA low dropout linear regulator, a 2-wire SMBus/I2C interface and a 6-bit DAC. Fan speed is controlled by varying the fan’s terminal voltage through the output voltage of the LTC1695’s linear regulator. The LTC1695’s output voltage is programmed by sending a 6-bit digital code to the LTC1695 DAC via the SMBus. To eliminate fan start-up problems at lower fan voltages, users can enable the LTC1695’s boost start feature that provides the DAC’s full-scale output voltage for 250ms before decreasing to the programmed output voltage. The LTC1695 includes output current limiting and thermal shutdown as well as status monitors that can be read back by the microprocessor during fault conditions. The LTC1695 is available in a 5-lead SOT-23 package. APPLICATIO S s s s s s s s Notebook Computers Spot Cooling Portable Instruments Battery-Powered Systems DC Motor Control White LED Power Supplies Programmable Low Dropout Regulator , LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. TYPICAL APPLICATION 5V 1 10µF VCC VOUT 5 LOAD CURRENT (mA) Fan Voltage and Current vs DAC Code 120 100 80 ILOAD 60 40 20 1695 • TA01 VCC = 5V TA = 25°C + 2 LTC1695 GND 4 4.7µF + 5V DC FAN SUNON KDE0502PFB2-8 0.6W, 1.7 CFM (25 • 25 • 10)mm3 3 SYSTEM CONTROLLER SCL SDA 0 0 10 U 6 5 OUTPUT VOLTAGE (V) U U 4 VOUT 3 2 1 0 70 20 40 30 DAC CODE 50 60 1695 • TA02 1 LTC1695 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW VCC 1 GND 2 SCL 3 4 SDA 5 VOUT Terminal Voltages Supply Voltage (VCC) ............................................. 7V All Other Inputs ........................ –0.3V to (VCC + 0.3V) Operating Temperature Range ..................... 0°C to 70°C Junction Temperature ........................................... 125°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1695CS5 S5 PART MARKING LTIY S5 PACKAGE 5-LEAD PLASTIC SOT-23 TJMAX = 125°C, θJA = 256°C/W SEE THE APPLICATIONS INFORMATION SECTION. Consult factory for Industrial and Military grade parts. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise stated. SYMBOL VCC ICC DAC DAC Resolution VLSB VOS DNL INL VFS VZS RON(P) VUVLO TBST_ST TTHERMAL IFAULT VIH VIL IIN CIN tON tOFF VOL 1LSB Resolution Offset Error Differential Nonlinearity Integral Nonlinearity VOUT, DAC Full Scale VOUT, DAC Zero Scale P-Channel On Resistance Undervoltage Lockout Voltage Boost Start Timer Thermal Shutdown Temperature Output Current Limit Threshold Input High Threshold Input Low Threshold Input Current Input Capacitance Switch On Time from Stop Condition (fSMBus = 100kHz) Switch Off Time from Stop Condition (fSMBus = 100kHz) SDA Output Low Voltage SCL, SDA = 0V or 5V (Note 3) VOUT from Zero Scale to Full Scale, ILOAD = 1mA, CLOAD = 4.7µF VOUT from Full Scale to Zero Scale, ILOAD = 150mA, CLOAD = 4.7µF IPULLUP = 3mA q q q ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Range Supply Current, Operating Supply Current, Shutdown CONDITIONS VOUT = Full Scale, ILOAD = 150mA DAC Code = 0 Guaranteed Monotonic ILOAD = 1mA ILOAD = 1mA ILOAD = 1mA (Note 2) ILOAD = 1mA (Note 2) ILOAD = 20mA ILOAD = 150mA RLOAD = 1kΩ ILOAD = 150mA Rising VCC ILOAD = 10mA, CLOAD = 4.7µF (Note 3) VOUT = 0V, DAC Code = 63 q q q q q MIN 4.5 TYP 5 150.7 80 6 MAX 5.5 155 200 UNITS V mA µA Bits q q q q q q q q 73 78 83 ±1 ± 0.75 ±0.75 4.5 4.5 4.93 4.9 0 0.75 85 Timer and Thermal Shutdown 2.3 75 180 2.1 0.8 ±0.1 3 50 150 150 500 500 400 ±5 2.9 250 155 390 850 3.5 1000 V ms °C mA V V µA pF µs µs mV SMBus SCL, SDA Inputs q q q 2 U mV LSB LSB LSB V V mV Ω W U U WW W LTC1695 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise stated. SYMBOL fSMB tBUF tHD(STA) tSU(STA) tSU(STO) tHD(DAT) tSU(DAT) tLOW tHIGH tf tr PARAMETER SMBus Operating Frequency Bus Free Time Between Stop and Start Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall Time Clock/Data Rise Time CONDITIONS q q q q q q q q q q q ELECTRICAL CHARACTERISTICS SMBus TIMING (Note 4) MIN 10 4.7 4.0 4.7 4.0 300 250 4.7 4.0 TYP MAX 100 UNITS kHz µs µs µs µs ns ns µs 50 300 1000 µs ns ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: INL, DNL specs are specified under a 1mA ILOAD condition to keep the linear regulator from operating in dropout at higher DAC codes. DNL is measured from code 0 to code 63, taking into account the untrimmed offset at code 0. Please refer to the Definitions section for more details. Note 3: This typical specification is based on lab measurements and is not production tested. Note 4: Guaranteed by design and not tested. Please refer to the Timing Diagram section for additional information. TYPICAL PERFOR A CE CHARACTERISTICS Output Voltage vs DAC Code 6 5 OUTPUT VOLTAGE (V) 250 VCC = 5V TA = 25°C ILOAD = 1mA SUPPLY CURRENT (µA) 4 3 2 1 0 SUPPLY CURRENT (µA) 0 10 20 30 40 DAC CODE UW 50 1695 • G01 No Load Supply Current vs Supply Voltage 250 No Load Supply Current vs Temperature VCC = 5V TA = 25°C CODE 63 200 200 CODE 63 150 150 100 CODE 0 100 CODE 0 50 50 60 63 0 4.0 5.0 4.5 5.5 SUPPLY VOLTAGE (V) 6.0 1695 • G02 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1695 • G03 3 LTC1695 TYPICAL PERFOR A CE CHARACTERISTICS Ground Current (Dropout Mode) vs Supply Voltage 900 TA =25°C ILOAD = 180mA CODE 63 700 GROUND CURRENT (µA) DROPOUT VOLTAGE (mV) GROUND CURRENT (µA) 800 600 500 400 4.0 5.0 4.5 5.5 SUPPLY VOLTAGE (V) Output Voltage (Full Scale) vs Load Current 4.930 4.920 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.910 CODE 63 4.900 4.890 4.880 4.870 4.860 OUTPUT VOLTAGE (V) 0 20 40 60 80 100 120 140 160 180 LOAD CURRENT (mA) 1695 • G07 Output Voltage (Midscale) vs Temperature 2.510 2.505 OUTPUT VOLTAGE (V) VCC = 5V CODE 32 ILOAD = 1mA 2.500 2.495 2.490 DNL (LSB) INL (LSB) ILOAD = 150mA 2.485 2.480 –50 –25 50 25 75 0 TEMPERATURE (°C) 4 UW 1695 • G04 Ground Current (Dropout Mode) vs Temperature 900 850 800 CODE 63 750 700 650 600 –50 –25 VCC = 5V ILOAD = 180mA 175 150 125 100 75 50 25 0 Dropout Voltage vs Load Current VCC = 5V TA = 85°C TA = 25°C TA = – 40°C 6.0 50 25 75 0 TEMPERATURE (°C) 100 125 0 20 40 60 80 100 120 140 160 180 LOAD CURRENT (mA) 1695 • G06 1695 • G05 Output Voltage (Midscale) vs Load Current 2.505 4.95 Output Voltage (Full Scale) vs Temperature VCC = 5V CODE 63 4.93 ILOAD = 1mA VCC = 5V TA = 25°C VCC = 5V TA = 25°C 2.500 2.495 CODE 32 2.490 4.91 ILOAD = 150mA 4.89 2.485 4.87 2.480 0 20 40 60 80 100 120 140 160 180 LOAD CURRENT (mA) 1695 • G08 4.85 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 1695 • G09 Differential Nonlinearity (DNL) 0.25 VCC = 5V ILOAD = 1mA 0.25 Integral Nonlinearity (INL) VCC = 5V ILOAD = 1mA 0.15 0.15 0.05 0.05 –0.05 –0.05 –0.15 –0.15 100 125 –0.25 0 10 20 30 40 CODE 50 60 63 1695 • G11 –0.25 0 10 20 30 40 CODE 50 60 63 1695 • G12 1695 • G10 LTC1695 TYPICAL PERFOR A CE CHARACTERISTICS POR and UVLO vs Temperature 3.00 350 TA = 25°C ILOAD = 10mA BOOST START TIMER (ms) SUPPLY VOLTAGE (V) 2.90 300 BOOST START TIMER (ms) POR (RISING VCC) 2.80 UVLO (FALLING VCC) 2.70 2.60 –50 –25 0 25 50 75 TEMPERATURE (°C) Current Limit Threshold vs Supply Voltage 425 JUNCTION TEMPERATURE INCREASE (°C) TA = 25°C 400 CURRENT LIMIT (mA) CURRENT LIMIT (mA) 375 350 325 300 4.5 5.0 4.75 5.25 SUPPLY VOLTAGE (V) Load Transient Response Code 32, 5mA to 55mA VOUT (AC) 20mV/DIV ILOAD 50mA/DIV 100µs/DIV VCC = 5V COUT = 4.7µF TANTALUM UW 100 1695 • G13 1695 • G16 Boost Start Timer vs Supply Voltage 600 500 400 300 200 100 150 4.0 Boost Start Timer vs Temperature VCC = 5V ILOAD = 10mA 250 200 125 5.0 5.5 4.5 SUPPLY VOLTAGE (V) 6.0 1695 • G14 0 –25 0 25 50 TEMPERATURE (°C) 75 100 1695 • G15 Current Limit Threshold vs Temperature 600 VCC = 5V 500 400 300 200 100 0 –40 120 100 80 60 40 20 0 Junction Temperature Increase vs Load Current VCC = 5V, TA = 25°C, SOT-23 THERMAL RESISTANCE = 150°C/W (PCB SOLDERED) SEE APPLICATIONS INFORMATION. CODE 16 (1.25V) CODE 32 (2.5V) CODE 48 (3.75V) CODE 63 (4.922V) 0 20 40 60 80 100 120 140 160 180 LOAD CURRENT (mA) 1695 • G18 5.5 –20 0 20 40 TEMPERATURE (°C) 60 80 90 1695 • G17 Load Transient Response Code 32, 50mA to 100mA VOUT (AC) 10mV/DIV ILOAD 50mA/DIV 100µs/DIV VCC = 5V COUT = 4.7µF TANTALUM 1695 • G19 1695 • G20 5 LTC1695 TYPICAL PERFOR A CE CHARACTERISTICS Load Transient Response Dropout (Code 63), 5mA to 55mA Load Transient Response Dropout (Code 63), 50mA to 100mA Boost Start Timer VOUT (AC) 20mV/DIV ILOAD 50mA/DIV 100µs/DIV VCC = 5V COUT = 4.7µF TANTALUM PIN FUNCTIONS VCC (Pin 1): Power Supply Input. VCC supplies current to the internal control circuitry, serves as the reference for the 6-bit DAC and acts as the power path for the P-channel low dropout linear regulator. Bypass VCC directly to ground with a low ESR capacitor ≥ 10µF. GND (Pin 2): Ground. Tie GND to the ground plane. SCL (Pin 3): SMBus Clock Input. Data is shifted into SDA on the rising edge of the SCL clock signal during data transfer. SDA (Pin 4): SMBus Bidirectional Data Input/Digital Output. SDA is an open drain output and requires a pull-up resistor or current source to VCC. Data is shifted into SDA and acknowledged by SDA. VOUT (Pin 5): Linear Regulator Output. Connect directly to the fan’s +VE terminal. VOUT is set to VZS (code 0) on power-up. For good transient response and stability, use a general purpose, low cost, medium ESR (0.1Ω to 1Ω) tantalum or electrolytic capacitor. LTC recommends a surface mount tantalum capacitor of ≥ 4.7µF. 6 UW VOUT (AC) 20mV/DIV VOUT 2V/DIV ILOAD 50mA/DIV 100µs/DIV VCC = 5V COUT = 4.7µF TANTALUM VCC = 5V CIN = 10µF COUT = 4.7µF ILOAD = 1mA 100ms/DIV 1695 • G21 1695 • G22 1695 • G23 U U U LTC1695 BLOCK DIAGRA SCL SDA W POWER ON RESET AND UVLO VCC SHUTDOWN CONTROL BOOST START TIMER PULL-DOWN/UP LOGIC THERMAL SHUTDOWN 6-BIT DAC (RESISTORS, SWITCHES) 6 COMMAND REGISTER CURRENT LIMIT VOUT DATA REGISTER R1 50k GND R2 50k 1695 • BD – OP AMP + P1 0.75Ω SMBus INTERFACE (BUFFERS, LOGIC) 7 LTC1695 SWITCHING WAVEFORMS Boost Start Timer Measurement ILOAD = 10mA, CLOAD = 4.7µF VOUT = VFS 90% VFS 90% VFS VOUT = VZS Output Switch On Time Measurement Code = 63, ILOAD = 1mA, CLOAD = 4.7µF fSMBus =100kHz STOP CONDITION 12 12 13 14 15 COMMAND BYTE D4 D3 D2 16 17 18 19 D5 D1 D0 ACK VOUT = VFS 90% VFS D4 D3 D2 D1 D0 ACK 13 14 15 COMMAND BYTE 16 17 18 19 D5 VOUT = VFS VOUT = VZS tON 1695 • SW02 8 W U VOUT = V(CODE 32) tBST_ST 1695 • SW01 Output Switch Off Time Measurement Code = 0, ILOAD = 150mA, CLOAD = 4.7µF fSMBus =100kHz STOP CONDITION VOUT = VZS 10% VFS tOFF 1695 • SW03 LTC1695 TI I G DIAGRA W Operating Sequence S SCL 1 2 3 4 5 6 SLAVE ADDRESS 0 1 0 7 8 9 10 11 12 13 14 15 COMMAND BYTE D4 D3 D2 16 17 18 19 SMBus SEND BYTE PROTOCOL, WITH SMBus ADDRESS = 1110100B P 1 1 0 WR ACK X BST D5 D1 D0 ACK SMBus RECEIVE BYTE PROTOCOL, WITH SMBus ADDRESS = 1110100B P 2 3 4 5 6 SLAVE ADDRESS 0 1 0 7 8 9 10 11 12 13 14 15 COMMAND BYTE 0 0 0 16 17 18 19 1 1 0 WR ACK OCF THE 0 0 0 ACK 1695 • TD01 UW SDA 1 S = SMBus START BIT P = SMBus STOP BIT BST = 1 ENABLES THE BOOST START TIMER D5 TO D0 = 6-BIT INPUT CODE FOR THE DAC (D5 = MSB) X = DON'T CARE S SCL 1 SDA 1 S = SMBus START BIT P = SMBus STOP BIT OCF = 1 SIGNALS THAT THE LTC1695 IS IN CURRENT LIMIT THE = 1 SIGNALS THAT THE LTC1695 IS IN THERMAL SHUTDOWN Timing for SMBus Interface STOP START tBUF SDA tHD(STA) SCL tLOW tHIGH tHD(DAT) tSU(STA) tSU(DAT) tSU(STO) 1695 • TD02 START STOP tr tf tHD(STA) 9 LTC1695 DEFINITIONS Resolution: The number of DAC output states (2N) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): The regulator output voltage (VOUT) if all DAC bits are set to ones (code 63). Voltage Offset Error (VOS): The regulator output voltage if all DAC bits are set to zeros. The LDO amplifier can have a true negative offset, but due to the LTC1695’s single supply operation, VOUT cannot go below ground. If the offset is negative, VOUT will remain near 0V resulting in the transfer curve shown in Figure 1. Table 1. Nominal VLSB and VFS values VCC VLSB 4.5V 5.0V 5.5V 70.3mV 78.1mV 85.9mV VFS 4.430V 4.922V 5.414V INL: Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the DAC transfer curve. Due to the LTC1695’s single supply operation and the fact that VOUT cannot go below ground, linearity is measured between full scale and the first code (code 01) that guarantees a positive output. The INL error at a given input code is calculated as follows: INL = (VOUT – VIDEAL))/VLSB VIDEAL = (Code • VLSB) + VOS OUTPUT VOLTAGE NEGATIVE OFFSET 0V VOUT = The output voltage of the DAC measured at the given input code DAC CODE 1695 • F01 Figure 1. Effect of Negative Offset DNL: Differential nonlinearity is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as below: DNL = (∆VOUT – VLSB)/VLSB ∆VOUT = The measured voltage difference between two adjacent codes The ∆VOUT calculation includes the VOS values to account for the effect of negative offset in Figure 1. This is relevant for code 1’s DNL. The offset of the part is measured at the first code (code 1) that produces an output voltage 0.5LSB greater than the previous code. VOS = VOUT – [(Code • VFS)/(2N – 1)] Least Significant Bit (VLSB): The least significant bit or the ideal voltage difference between two successive codes. VLSB = (VFS – VOS)/(2N – 1) 10 LTC1695 APPLICATIONS INFORMATION OVERVIEW The LTC1695 is a 5V brushless DC fan speed controller. Fan speed is controlled by linear regulating the applied voltage to the fan. To program fan speed, a system controller or microprocessor first sends a 6-bit digital code to the LTC1695 via a 2-wire SMBus/I2C interface. The LTC1695’s DAC then converts this digital code into a voltage reference. Finally, the LTC1695’s op amp loop regulates the gate bias of the internal P-channel pass transistor to control the corresponding output voltage. The LTC1695 is designed for portable, power-conscious systems that utilize small 5V brushless DC fans. These fans are increasingly popular in providing efficient cooling solutions in a small footprint. Smaller fans allow a user to employ multiple fans at strategic physical locations to govern a system’s thermal airflow (“air duct” concept). These brushless DC fans also make use of the 5V supply used by the main digital/analog circuitry, removing the need for a 12V supply required by higher power fans. The LTC1695’s P-channel linear regulator control approach offers the lowest solution component count, the smallest PCB board space consumed, wide fan speed control range and low acoustical/electrical generated noise. Thermal concerns over the use of a linear regulator topology are eliminated by the fan’s generally resistive behavior. As the LTC1695 DAC codes are changed to lower the output voltage, the voltage across the internal P-channel pass transistor increases. However, the fan’s load current decreases almost linearly, thereby controlling power dissipation in the regulator. For example, a Micronel 5V, 0.7W fan (40mm2 • 12mm) draws 80mA at 4V and 20mA at 2V. Thus the P-channel pass transistor’s power loss decreases from 80mW to 60mW. The LTC1695 incorporates several features to simplify the overall solution including a boost start timer to ensure fan start-up, output current limiting and thermal shutdown. The boost start timer is enabled via the SMBus commands and programs VOUT to full scale for 250ms before regulating at the user programmed output voltage. This eliminates potential fan start-up problems at lower output voltage DAC codes. The LTC1695’s thermal shutdown circuit trips if die temperature exceeds 155°C. The P-channel pass transistor is shut off and bit D6 in the LTC1695’s SMBus data register is set high. If an overload or short-circuit condition occurs, the LTC1695’s current-limit circuitry limits output current to 390mA typically. In addition, bit D7 in the SMBus data register is set high. The readback capability of the LTC1695 allows the host controller to monitor the status of the D6 and D7 bits for fault conditions. SMBus Serial Interface The LTC1695 is an SMBus slave device that supports both SMBus send byte and receive byte protocol (Figure 2) with two interface signals, SCL and SDA. The SMBus host initiates communication with the LTC1695 through a start bit followed by a 7-bit address code and a write bit. Each SMBus slave device in the system compares the address code with its specific address. For send byte and receive byte protocol, the write bit is LOW and HIGH respectively. If selected, the LTC1695 acknowledges by pulling SDA low. If send byte protocol is used, the host issues an 8-bit command code. After receiving the entire command byte, the LTC1695 again acknowledges by pulling SDA low. At the falling edge of the acknowledge pulse, the LTC1695’s DAC latches in the new command byte from its shift register. If receive byte protocol is used, the LTC1695 acknowledges by pulling SDA low after the write bit. The LTC1695 then transmits the data byte. After the host receives the entire data byte, the cycle is terminated by a “NOT Acknowledge” bit and a stop bit. U W U U 11 LTC1695 APPLICATIONS INFORMATION SMBus SEND BYTE PROTOCOL 1 S 1 2 1 3 1 4 0 5 1 6 0 7 0 8 0 9 0 A 10 11 12 13 14 15 16 17 18 19 X BST D5 D4 D3 D2 D1 D0 0 MSB LSB A STOP P A6 A5 A4 A3 A2 A1 A0 W START SLAVE ADDRESS COMMAND BYTE SMBus RECEIVE BYTE PROTOCOL 1 S 1 2 1 3 1 4 0 5 1 6 0 7 0 8 1 9 10 11 12 13 14 15 16 17 18 19 0 0 0 0 0 1 A STOP P 0 OCF THE 0 A A6 A5 A4 A3 A2 A1 A0 W START SLAVE ADDRESS DATA BYTE S = SMBus START BIT P = SMBus STOP BIT BST = 1 ENABLES THE BOOST START TIMER D5 TO D0 = 6-BIT INPUT CODE FOR THE DAC (D5 = MSB) OCF = 1 SIGNALS THAT THE LTC1695 IS IN CURRENT LIMIT THE = 1 SIGNALS THAT THE LTC1695 IS IN THERMAL SHUTDOWN BIT 18 = 1 IS A NOT ACKNOWLEDGE FOR RECEIVE BYTE PROTOCOL NOTE: DURING POWER UP AND UVLO, DAC INPUT BITS (D5 TO D0) AND THE BST BIT ARE RESET TO ZERO 1695 • F02 Figure 2. SMBus Interface Bit Definition SCL and SDA SCL is the synchronizing clock signal generated by the host. SDA is the bidirectional data transfer line between the host and a slave device. The host initiates a start bit by pulling SDA from high to low while SCL is high. The stop bit is initiated by changing SDA from low to high while SCL is high. All address, command and acknowledge signals must be valid and should not change while SCL is high. The acknowledge bit signals to the host the acceptance of a correct address byte or command byte. The SCL and SDA input threshold voltages are typically 1.4V with 40mV of hysteresis. Connect the SCL and SDA open-drain lines to either a resistive or current source pull up. The LTC1695 SDA has an open-drain N-channel tran- 12 U W U U sistor capable of sinking 3mA at less than 0.4V during the slave acknowledge sequence. The LTC1695 is compatible with the Philips/Signetics I2C Bus Interface. The 1.4V threshold for SCL and SDA does not create any I2C application problems. Early Stop Conditions If a stop condition occurs before the data byte is acknowledged in the write byte protocol, the LTC1695’s DAC is not updated. Otherwise, the internal register is updated with the new data and VOUT changes accordingly to the new programmed value. Address, Command, Data Selection The LTC1695’s address is hard-wired internally as 1110100 (MSB to LSB, A6 to A0). Consult LTC for parts with alternate address codes. Consult the Address, Command and Data Byte Tables for further information and as a concise reference. As shown in Figure 2, D5 to D0 in the command code, control the linear regulator’s output voltage and thus fan speed. D5 to D0 are sent from the host to the LTC1695 during send byte protocol. The LTC1695 latches D5 to D0 as DAC input data at the falling edge of the data acknowledge signal. The host must set “BST” (boost start enable bit) to high if the LTC1695’s 250ms boost start timer option is used. All bits are reset to zero during power-on reset and UVLO. As shown in the Timing Diagram, bit 6 and bit 7 in the data byte register are defined as thermal shutdown status (THE) and over current fault (OCF) status respectively. The LTC1695 sets OCF high if ILOAD exceeds 390mA typically and “THE” high if junction temperature exceeds 155°C typically. The remaining bits of the data byte’s register (bit 5 to 0) are set low during host read back. LTC1695 APPLICATIONS INFORMATION VCC VCC/2 64 RESISTOR VOLTAGE TABS 720 SWITCHES REFERENCE OP AMP “000000” = 0V “111111” = 0.984 • VCC/2 GND 6 SMBus COMMAND D5 to D0 Figure 3. Ladder DAC DAC The LTC1695 uses a 128-segment resistor ladder to implement the monotonic 6-bit voltage DAC (Figure 3). Guaranteeing monotonicity (no missing codes) permits the use of the LTC1695 in thermal feedback control applications. As the typical application uses a 5V supply for VCC, the reference for the 6-bit DAC is VCC. LTC recommends a 10µF or greater tantalum capacitor to bypass VCC. Users must account for the variation in the DAC’s output absolute accuracy as VCC varies. VCC voltage should not exceed the absolute maximum rating of 7V or drop below the typical 2.8V undervoltage lockout threshold (UVLO) during normal operation. The LTC1695’s DAC specifications (INL, DNL, VOS) account for the offset and gain errors of the linear regulator with respect to ILOAD. Consult the Definitions section for more details. The worst-case condition occurs if the LTC1695 P-channel pass transistor enters dropout at full-scale VOUT and ILOAD. Full-scale VOUT (VFS) is 4.922V with VCC = 5V. In this condition, loop gain drops and gain error increases. The LTC1695 is designed for monotonicity up to VFS with DNL and INL less than 0.75 LSB. Refer to the Electrical Characteristics and Typical Performance Characteristics for more information. U W U U Linear Regulator Loop Compensation The LTC1695’s linear regulator approach is a simple and practical scheme for fan speed control featuring a wide and linear dynamic range. It also introduces less noise into the system supply rail, compared with a PWM scheme (fixed frequency, variable duty cycle), switching regulator topology or simple ON-OFF control. The LTC1695 linear regulator feedback loop requires a capacitor at its output to stabilize the loop over the output voltage and load current range. The output capacitor value and the capacitor’s ESR value are critical in stabilizing the LTC1695 feedback loop. A ≥ 1µF general purpose, low to medium ESR (0.1Ω to 5Ω) tantalum or aluminium electrolytic capacitor is sufficient for most applications. These capacitor types offer a lowcost advantage, particularly for fan speed control applications. As the output capacitance value increases, stability improves. A typical 4.7µF, 1Ω ESR surface mount tantalum capacitor is recommended for the optimum transient response and frequency stability across temperature, VOUT and ILOAD. Refer to the load transient response waveforms in the Typical Performance Characteristics section. The selection of the capacitor for COUT must be evaluated by the user for temperature variation of the capacitance and ESR value and the voltage coefficient of the capacitor value. For example, the ESR of aluminium electrolytic capacitors can increase dramatically at cold temperature. Therefore, the regulator may be stable at room temperature but oscillate at cold temperature. Ceramic capacitors with Z5U and Y5 dielectrics provide high capacitance values in a small package, but exhibit strong voltage and temperature coefficients (–80% in some cases). In addition, the ESR of surface mount ceramic capacitors is too low (