LTC1700

LTC1700 No RSENSE Synchronous Step-Up DC/DC Controller FEATURES s s s DESCRIPTIO s s s s s s s s s s High Efficiency: Up to 95% No Current Sense Resistor Required Constant Frequency 530kHz Operation Allows Small Size, Surface Mount Inductors OPTI-LOOPTM Compensation Minimizes COUT Selectable Burst ModeTM Operation Minimum Start-Up Voltage as low as 0.9V Synchronizable Between 400kHz and 750kHz Micropower Shutdown: 10µA Current Mode Operation for Excellent Line and Load Transient Response Soft-Start Reduces Supply Current Transients 1.5% Output Voltage Accuracy Uses Low Value, Small Size, Surface Mount Inductors Available in 10-Lead MSOP Package The LTC®1700 is a current mode synchronous step-up DC/DC controller that drives external N-channel and P-channel power MOSFETs using a constant frequency PWM architecture. Current limiting is provided by sensing the voltage drop across the main MOSFET, eliminating the need of a sense resistor. This No RSENSETM technique helps the LTC1700 maintain high efficiency at heavy loads while Burst Mode operation ensures high efficiency at light loads, thus providing high efficiencies over a wide range of load currents. The LTC1700 operates at a minimum input voltage as low as 0.9V. The device boasts a ±1.5% output voltage accuracy and consumes only 200µA of quiescent current. In shutdown, it only draws 10µA. To prevent inductor current runaway, the duty cycle is limited to 90%. Overvoltage protection is also provided which shuts both the external MOSFETs off when tripped. High constant operating frequency of 530kHz allows the use of small inductors and output capacitors. The LTC1700 can also be synchronized between 400kHz to 750kHz. Burst Mode operation is inhibited when the device is externally clocked or when the SYNC/MODE pin is pulled low to reduce noise and RF interference. APPLICATIO S s s s s s s Cellular Telephones Wireless Modems RF Communications 2.5V to 3.3V, 2.5V to 5V Converters Battery-Powered Equipment Telecom/Network Systems , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode, OPTI-LOOP and No RSENSE are trademarks of Linear Technology Corporation. TYPICAL APPLICATIO 2 R3 2200Ω C3 220pF 4 C4 0.1µF 1 3 R2 100k 5 R1 316k ITH RUN/SS L1 1.8µH SW BG 10 8 M1 C1 22µF M2 + VIN 3.3V to 4.2V C2 68µF 6.3V 5V 2A C6 10µF LTC1700 SGND VFB PGND TG 9 6 7 + C7 330µF 6V EFFICIENCY (%) C5 220pF SYNC/MODE VOUT 1700 • F01a C1: CERAMIC TAIYO YUDEN LMK432BJ226MM C2: AVX TAJB686K006R L1: TOKO 919AS-IR8N (D104C TYPE) C6: CERAMIC TAIYO YUDEN JMK316BJ106ML C7: SANYO POSCAP 6TPB330M M1: SILICONIX Si9804 M2: SILICONIX Si9803 Figure 1. High Efficiency Step-Up Converter U Efficiency vs Load Current 100 90 80 70 60 50 40 0.001 VIN = 4.2V VIN = 3.3V 0.01 0.1 LOAD CURRENT (A) 1.0 1700 F01b U U 1 LTC1700 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW SGND ITH VFB RUN/SS SYNC/MODE 1 2 3 4 5 10 9 8 7 6 SW PGND BG VOUT TG Output Supply Voltage (VOUT) .....................– 0.3V to 6V RUN/SS, VFB Voltages ..............................– 0.3V to 2.4V SYNC/MODE, ITH Voltages ...........................– 0.3V to 6V SWITCH Voltage (SW) ..............................– 0.3V to 6.5V TG, BG Peak Output Current ( 36% Use LMINBURST for Duty Cycle ≤ 36% A smaller value than LMIN could be used in the circuit; however, the inductor current will not be continuous during burst periods. The advantage of using a smaller inductance than LMIN is primarily size. The disadvantage is higher output ripple. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will Kool Mµ is a registered trademark of Magnetics, Inc. LTC1700 APPLICATIONS INFORMATION increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available which do not increase the height significantly. COUT Selection During continuous operation, the output capacitor has a trapezoidal current profile. The RMS current into the capacitor is then given by:   V ICOUT (RMS) ≅  IOUT OUT – 1 VIN   The RMS current is greatest at IOUT(MAX) and minimum input working voltage. Therefore the output capacitor should be chosen with a rating at least ICOUT(RMS). Several capacitors can also be paralleled to meet this requirement. Besides RMS current rating, the selection of COUT is also driven by the required effective series resistance (ESR). The ESR of the capacitor together with its capacitance determines the output ripple voltage and can be expressed as: ∆VOUT ≈ IPK ESR + () 2IOUT C OUT tON where COUT = output capacitance, tON = on time of main MOSFET and IPK = peak inductor current. A common technique to lower the total ESR at the output is to parallel the output capacitor with a 10µF ceramic capacitor. U W U U The choice of using a smaller output capacitance increases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitors of very low ESR to maintain low ripple voltage. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR (size) product of any aluminum electrolytic at a somewhat higher price. Multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Setting Output Voltage The LTC1700 develops a 1.205V reference voltage between the feedback (Pin 3) terminal and ground (see Figure 6). By selecting resistor R1, a constant current is caused to flow through R1 and R2 to set the overall output voltage. The regulated output voltage is determined by: VOUT = 1.205(1 + R2/R1) For most applications, a 30k resistor is suggested for R1. To prevent stray pickup, a 100pF capacitor is suggested across R1 located close to LTC1700. VOUT LTC1700 VFB R1 1700 • F06 R2 Figure 6. Setting Output Voltage 11 LTC1700 APPLICATIONS INFORMATION Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power (× 100%). Percent efficiency can be expressed as: % Efficiency = 100%–(L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1700 circuits: 1. LTC1700 supply current. This DC supply current, given in the electrical characteristics, excludes MOSFET drivers and control current. This supply current results in a small loss which increases with VOUT. 2. MOSFETs gate charge current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched on and then off, a packet of gate charge Qg moves from VOUT to ground. The resulting current out from VOUT is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(Qg(TOP) + Qg(BOT)). At high switching frequencies, this loss becomes increasing important. 3. DC I2R Losses. Since there is no sense resistor needed, DC I2R losses arise only from the resistances of the MOSFETs and inductor. In continuous mode, the average current flows through the inductor but is “chopped” between the synchronous P-channel MOSFET and the main N-channel MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistance of the inductor to obtain the DC I2R loss. For example, if each RDS(ON) = 0.05Ω and RL = 0.15Ω, then the total resistance is 0.2Ω. This results in losses ranging from 2% to 8% as the output current increases from 0.5A to 2A for a 5V output. I2R losses cause the efficiency to drop at high output currents. 4. Transition losses apply to the main external MOSFET and increase at higher operating frequencies and output voltages. Transition losses can be estimated from: Transition Loss = 2.5(VOUT)2IO(MAX)CRSS(f) Other losses including CIN and COUT ESR dissipative losses, and inductor core losses, generally account for less than 2% total loss. Run/Soft Start Function The RUN/SS pin is a dual purpose pin that provides the soft-start function and a means to shut down the LTC1700. Soft-start reduces input surge current from VIN by gradually increasing the internal current limit. Power supply sequencing can also be accomplished using this pin. An internal 3.8µA current source charges up an external capacitor CSS. When the voltage on the RUN/SS pin reaches 0.7V, the LTC1700 begins operating. As the voltage on RUN/SS continues to ramp from 0.7V to 1V, the internal current limit is also ramped at a proportional linear rate. The current limit begins near 0A (at VRUN/SS = 0.7V) and ends at 0.078/RDS(ON) (VRUN/SS ≈ 2.2V). The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If the RUN/ SS has been pulled all the way to ground, there will be a delay before the current limit starts increasing and is given by: tDELAY = 1.13CSS/ICHG For input voltages less than 2.3V during the start-up duration, the soft-start function has no effect on the internal 60mA current limit. Therefore to fully take advantage of this feature, the soft-start capacitor has to be sized accordingly to account for the time it takes VOUT to reach 2.3V. An approximate mathematical representation for the time it takes VOUT to reach 2.3V upon powering up is given by: 12 U W U U tPOWER−UP = C OUT (2.3 – VIN – VD ) 260(L) – IOUT 2.3 – VIN LTC1700 APPLICATIONS INFORMATION where: VD = Voltage drop of P-channel parasitic diode IOUT = Initial load current during start-up COUT = Output capacitance Hence you would select the start-up capacitor, CSS, to ensure tDELAY > tPOWERUP. Remember that the above equation is only valid for VIN < 2.3V. If VIN is greater than 2.3V, then tPOWERUP = 0ns. Design Example Assume the LTC1700 is used to convert a 3.3V input to 5V output. Load current requirement is a maximum 3A and a minimum of 100mA. Efficiency at both low and high load currents is important. Ambient temperature = 25°C. Since low load current efficiency is important, Burst Mode operation is enabled by connecting pin 5 to VOUT. Duty Cycle = 1 – VIN/VOUT = 0.34 Since the duty cycle is less than 36%, the value of the inductor is chosen based on the LMINBURST equation. LMINBURST = 0.8µH. In the application, (Figure 7) a 4.6µH inductor is used to further reduce ripple current. The actual ripple current is now: Accounting for the peak current reduction due to slope compensation (see Figure 5), the RDS(ON) of the N-channel should be: RDS(ON) = (13.2)(0.9) = 11.9mΩ The factor, 0.9, is obtained from Figure 5 using a duty cycle of 34%. The peak current of the inductor is 5A. Select an inductor that does not saturate at this current level. The average current through the N-channel MOSFET is 1.62A while the average current through the synchronous Pchannel MOSFET is 3A. The FDS6670A and FDS6375 are chosen for the N-channel and P-channel MOSFET respectively. We can now calculate the temperature rise in the FDS6670A. RMS current flowing through the FDS6670A is 2.78A. Hence power dissipated is: PDISS = (2.78)2 (8 × 10–3) = 61.82mW The θJA of the FDS6670A is 50°C/W. Therefore temperature rise is: TRISE = 61.82mW × 50 = 3.1°C This is an insignificant temperature rise and therefore the omission of the ρT in calculating the required RDS(ON) does not generate a large error. At 3A load, the RMS current into the output capacitor is given by: ICOUT(RMS) = 3(5/3.3 – 1)0.5 = 2.15A To meet the RMS current requirement, two SANYO POSCAP 100µF capacitors are paralleled. These capacitors have low ESR (55mΩ) and to futher reduce the overall ESR, a 10µF ceramic capacitor is placed in parallel with the POSCAP capacitor. Figure 7 shows the complete circuit.   0.34 ∆IL = 3.3V  = 0.46A  530kHz(4.6µH) For the main N-channel MOSFET, the RDS(ON) should be: RDS(ON)(N−CHANNEL) = 63mV IO(MAX) 1– D + 0.5(∆IL ) = 13.2mΩ U W U U 13 LTC1700 APPLICATIONS INFORMATION L1 4.6µH 1 220pF 270pF 470pF 4 30k 3 5 95k 2.2k 2 10 8 M2 FDS6375 M1 FDS6670A C3 22µF C1 10µF SGND ITH LTC1700 RUN/SS VFB SYNC/MODE VOUT C1: TAIYO YUDEN CERAMIC JMK316BJ106ML C2: AVX TAJB68K006R C3: TAIYO YUDEN CERAMIC JMK325BJ226M Figure 7. Design Example Schematic PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1700. These items are illustrated graphically in the layout diagram in Figure 8. Check the following in your layout: 1. Are all the components connected close to the SW node (Pin 10)? The SW pin is the input to the VDS sense amplifier and the current reverse comparator. 2. Connect the VOUT lead directly to the source of the P-channel MOSFET. Besides supplying current to the LTC1700, it also serves as the other input to the current reverse comparator. VIN 1 C3 R3 2 SGND ITH LTC1700 R1 C4 4 R2 5 3 VFB RUN/SS SYNC/MODE BG VOUT TG 8 7 6 M1 Figure 8. LTC1700 Layout Diagram (See PC Board Layout Checklist) 14 U W U U + C2 68µF 6.3V VIN 3.3V SW BG + VOUT 5V/3A C4 150µF 6.3V ×2 PGND TG 9 6 7 C4: SANYO POSCAP 6TPA150M L1: SUMIDA CEP1234R6 1700 • F07 3. Connect the (+) plate of C2 to the source of the P-channel MOSFET. This capacitor supports the load current when the inductor is being “recharged”. 4. Connect the (–) plate of C2 to the source of the N-channel MOSFET. Connect the power and signal ground to this node. 5. Does the VFB pin connects directly to the feedback resistors? The resistive divider R1 and R2 must be connected between the (+) plate of C2 and signal ground. 6. Keep the switching node SW away from sensitive small signal nodes. 7. Switched currents flow in M1, M2 and C2, keep the loop formed by these components as small as possible. L1 C1 SW PGND 10 9 M2 VOUT + C2 1700 • F08 LTC1700 TYPICAL APPLICATIO LTC1700 3.3V/1A Regulator with External Frequency Synchronization VIN 2V TO 2.4V 100pF 2.2k 470pF 4 30k 3 5 53.6k 650kHz 180pF 2 C1: AVX TAJB686K006R C2: TAIYO YUDEN CERAMIC JMK316BJ106ML C3: AVX TPSD227M006R0100 PACKAGE DESCRIPTIO 0.007 (0.18) 0.021 ± 0.006 (0.53 ± 0.015) 0° – 6° TYP SEATING PLANE 0.007 – 0.011 (0.17 – 0.27) 0.193 ± 0.006 (4.90 ± 0.15) 0.118 ± 0.004** (3.00 ± 0.102) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U L1 1.5µH 1 10 M1 C4 22µF BG PGND TG 8 9 6 7 M1 C2 10µF + C1 68µF 6.3V SGND LTC1700 ITH RUN/SS VFB SW + C3 220µF 6.3V 3.3V/1A SYNC/MODE VOUT 1700 • TA01 C4: TAIYO YUDEN CERAMIC JMK325BJ226MM L1: MURATA LQN6C M1: SILICONIX Si6562DQ Dimensions in inches (millimeters) unless otherwise noted. MS10 Package 10-Lead Plastic MSOP (LTC DWG # 05-08-1661) 0.118 ± 0.004* (3.00 ± 0.102) 0.043 (1.10) MAX 0.034 (0.86) REF 10 9 8 7 6 0.0197 (0.50) BSC 0.005 ± 0.002 (0.13 ± 0.05) 12345 MSOP (MS10) 1100 15 LTC1700 TYPICAL APPLICATIO 300pF 33k 470pF 2 470pF 4 30k 3 5 53.6k C1: TAIYO YUDEN CERAMIC JMK316BJ106ML C2: AVX TAJB68K006R C3: TAIYO YUDEN CERAMIC JMK325BJ226M C4: KEMET T520D227M006AS RELATED PARTS PART NUMBER LT1302 LT1304 Series LT1307/LT1307B LT1316 LT1317 LT1517-5 LT1610 LT1611 LT1613 LT1619 LTC1625 LTC1871 LTC1872 LTC3401/LTC3402 DESCRIPTION Micropower Step-Up Regulator 2-Cell Micropower Step-Up Regulator Single Cell Micropower Step-Up Regulator Burst Mode Operation DC/DC with Programmable Current Limit 2-Cell Micropower Step-Up Regulator Micropower, Regulated Charge Pump 1.7MHz Single Cell Micropower Step-Up Regulator Inverting 1.4MHz Switching Regulator 1.4MHz Single Cell Micropower Regulator Micropower Step-Up Regulator Controller No RSENSE Synchronous Step-Down Controller Boost, Flyback and SEPIC Controller SOT-23, 550kHz Step-Up Controller Integrated 1A and 2A Synchronous Step-Up Regulators 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U LTC1700 2.5V VIN 3.3V/1.8A Output Regulator VIN 2.5V L1 2.2µH 1 10 M2 C3 22µF BG PGND TG 8 9 6 7 M1 C1 10µF + C2 68µF 6.3V SGND LTC1700 ITH RUN/SS VFB SW + VOUT 3.3V/1.8A C4 220µF 6.3V SYNC/MODE VOUT L1: MURATA LQN6C M1: Si9802 M2: Si9803 1700 • TA02 COMMENTS 5V/600mA from 2V, 2A Internal Switch, 200µA IQ Low-Battery Detector Active in Shutdown 3.3V/75mA From 1V; 600kHz Fixed Frequency 1.5V Minimum VIN; Precise Control of Peak Switch Current 3.3V/200mA From Two Cells; 600kHz Fixed Frequency 3-Cells to 5V at 20mA, SOT-23 Package, 6µA IQ 30µA IQ, MSOP Package, Internal Compensation 5V to -5V at 150mA, Low Output Noise 5-Lead SOT-23 Package Drives External NMOS; 3.3V to 5V at up to 8A Up to 97% Efficiency; 3.7V ≤ VIN ≤ 36V; 1.19V ≤ VOUT ≤ VIN; IOUT up to 15A 5V ≤ VIN ≤ 30V; No RSENSE, Programmable Frequency 50kHz to 1MHz; 10-Lead MSOP Minimum Board Area; Drives External NMOS Up to 97% Efficiency; up to 3MHz Operation; No External Diode; 0.85V Start-Up Voltage 1700f LT/TP 0801 2K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2000