LTC1735-1

FEATURES s s s s s s s s s s s LTC1735-1 High Efficiency Synchronous Step-Down Switching Regulator DESCRIPTIO The LTC®1735-1 is a synchronous step-down switching regulator controller optimized for CPU power. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The operating frequency (synchronizable up to 500kHz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. The output voltage is monitored by a power good window comparator that indicates when the output is within 7.5% of its programmed value, conforming to Intel Mobile CPU Specifications. Protection features include internal foldback current limiting, output overvoltage crowbar and optional shortcircuit shutdown. Soft-start is provided by an external capacitor that can be used to properly sequence supplies. The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum). Pin defeatable Burst ModeTM operation provides high efficiency at low load currents while 99% duty cycle provides low dropout operation. s s s s Dual N-Channel MOSFET Synchronous Drive Programmable/Synchronizable Fixed Frequency VOUT Range: 0.8V to 7V Wide VIN Range: 3.5V to 36V Operation Very Low Dropout Operation: 99% Duty Cycle OPTI-LOOPTM Compensation Minimizes COUT ±1% Output Voltage Accuracy Power Good Output Voltage Monitor Internal Current Foldback Output Overvoltage Crowbar Protection Latched Short-Circuit Shutdown Timer with Defeat Option Optional Programmable Soft-Start Remote Output Voltage Sense Logic Controlled Micropower Shutdown: IQ < 25µA Available in 16-Lead Narrow SSOP and SO Packages APPLICATIO S s s s Notebook and Palmtop Computers, PDAs Power Supply for Mobile Pentium® III Processor with SpeedStepTM Technology Cellular Telephones and Wireless Modems , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. SpeedStep is a trademark of Intel Corporation. TYPICAL APPLICATIO PGOOD COSC 47pF CSS 0.1µF CC2 330pF RC1 33k CC1 47pF 1 2 3 4 5 47pF 1000pF 6 7 8 VIN 4.5V TO 24V COSC RUN/SS ITH TG BOOST SW VIN INTVCC BG PGND EXTVCC 10Ω 10Ω 16 15 14 13 12 11 10 9 5V (OPTIONAL) D1 CMDSH-3 CB 0.22µF Q1 FDS6680A L1 1.2µH D2 MBRS340T3 Q2, Q3 FDS6680A ×2 CIN 22µF 50V CERAMIC ×2 RSENSE 0.004Ω LTC1735-1 PGOOD SENSE – SENSE + VOSENSE SGND + 4.7µF Figure 1. CPU Core DC/DC Converter with Dynamic Voltage Selection from SpeedStep Enabled Processors U U U CIN: MARCON THCR70E1H226ZT COUT: PANASONIC EEFUE06181R L1: PANASONIC ETQP6RZ1R20HFA RSENSE: IRC CRF2010-01-R004J VOUT 1.35V TO 1.60V 12A COUT 180µF 4V PANASONIC SP ×4 VSEL = 1: VOUT = 1.60V VSEL = 0: VOUT = 1.35V GND 1735-1 F01 47pF R1 10k 0.5% + 47pF R2 14.3k 0.5% R3 33.2k 1% Q4 2N7002 1 LTC1735-1 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW COSC 1 RUN/SS 2 ITH 3 PGOOD 4 SENSE – 5 SENSE + 6 VOSENSE 7 SGND 8 16 TG 15 BOOST 14 SW 13 VIN 12 INTVCC 11 BG 10 PGND 9 EXTVCC Input Supply Voltage (VIN)........................ 36V to – 0.3V Topside Driver Supply Voltage (BOOST)... 42V to – 0.3V Switch Voltage (SW) ................................... 36V to – 5V INTVCC, EXTVCC (BOOST, SW) Voltages ..... 7V to – 0.3V SENSE +, SENSE –, PGOOD Voltages ................ 1.1(INTVCC + 0.3V) to – 0.3V ITH, VOSENSE, COSC Voltages .....................2.7V to – 0.3V RUN/SS Voltage ....................(INTVCC + 0.3V) to – 0.3V Peak Driver Output Current 40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Oscillator frequency is tested by measuring the COSC charge current (IOSC) and applying the formula: –1  8.477(108 )   1 1 fOSC (kHz) =  +    COSC(pF) + 11  ICHG IDIS  Note 7: Rise and fall times are measured using 10% to 90% levels. Delay times are measured using 50% levels. 3 LTC1735-1 TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Load Current (3 Operating Modes) 100 90 80 EFFICIENCY (%) EXTVCC OPEN BURST 70 CONT 60 50 40 30 20 0.001 VIN = 10V VOUT = 3.3V RS = 0.01Ω fO = 300kHz 0.1 0.01 1 LOAD CURRENT (A) 10 1735-1 G01 EFFICIENCY (%) EFFICIENCY (%) SYNC Efficiency vs Input Voltage 100 EXTVCC OPEN VOUT = 1.6V 95 FIGURE 1 90 IOUT = 5A 85 IOUT = 0.5A 80 75 70 –0.4 0 NORMALIZED VOUT (%) EFFICIENCY (%) VIN – VOUT (mV) 0 5 10 15 20 INPUT VOLTAGE (V) Input and Shutdown Currents vs Input Voltage 500 EXTVCC OPEN 400 80 100 4 3 2 1 0 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35 300 60 EXTVCC – INTVCC (mV) INPUT CURRENT (µA) INTVCC VOLTAGE (V) 200 SHUTDOWN 100 EXTVCC = 5V 0 0 5 20 15 10 25 INPUT VOLTAGE (V) 30 35 4 UW 25 1735-1 G04 1735-1 G07 Efficiency vs Load Current 100 90 VIN = 5V 80 70 60 50 40 10mA VIN = 24V VIN = 15V 90 EXTVCC = 5V VOUT = 1.6V 100 95 Efficiency vs Input Voltage EXTVCC = 5V VOUT = 1.6V FIGURE 1 IOUT = 5A 85 IOUT = 0.5A 80 75 70 100mA 1A LOAD CURRENT (A) 10A 1735-1 G02 0 5 10 15 20 INPUT VOLTAGE (V) 25 30 1735-1 G03 Load Regulation 500 FCB = 0V VIN = 15V FIGURE 1 VIN – VOUT Dropout Voltage vs Load Current RSENSE = 0.005Ω VOUT = 5V – 5% DROP 400 –0.1 300 –0.2 200 –0.3 100 0 0 2 6 4 LOAD CURRENT (A) 8 10 1735-1 G05 30 0 2 4 6 LOAD CURRENT (A) 8 10 1735-1 G06 INTVCC Line Regulation 6 5 1mA LOAD 500 EXTVCC Switch Drop vs INTVCC Load Current 400 SHUTDOWN CURRENT (µA) 300 40 200 20 100 0 0 0 10 30 40 20 INTVCC LOAD CURRENT (mA) 50 1735-1 G09 1735-1 G08 LTC1735-1 TYPICAL PERFOR A CE CHARACTERISTICS Maximum Current Sense Threshold vs Normalized Output Voltage (Foldback) MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) VSENSE(CM) = 1.6V 70 60 50 40 30 20 10 0 0 50 25 75 NORMALIZED OUTPUT VOLTAGE (%) 100 MAXIMUM CURRENT SENSE THRESHOLD (mV) 80 Maximum Current Sense Voltage vs ITH Voltage MAXIMUM CURRENT SENSE THRESHOLD (mV) 90 MAXIMUM CURRENT SENSE VOLTAGE (V) 80 70 60 50 40 30 20 10 0 –10 –20 –30 0 0.5 1 1.5 VITH (V) 2 2.5 1735-1 G13 70 VITH (V) SENSE Pins Total Source Current 100 50 2.0 ITH VOLTAGE (V) VIN = 10V VOUT = 3.3V RSENSE = 0.01Ω fO = 300kHz CONTINUOUS MODE SYNCHRONIZED f = fO AVERAGE OUTPUT CURRENT IOUT/IMAX (%) ISENSE (µA) 0 –50 –100 0 2 4 VSENSE COMMON MODE VOLTAGE (V) 1735-1 G16 UW 1735-1 G10 Maximum Current Sense Threshold vs VRUN/SS 80 80 Maximum Current Sense Threshold vs Sense Common Mode Voltage 60 76 72 40 68 20 64 0 0 1 2 3 4 VRUN/SS (V) 5 6 1735-1 G11 60 0 1 3 4 2 COMMON MODE VOLTAGE (V) 5 1735-1 G12 Maximum Current Sense Threshold vs Temperature 80 2.5 VSENSE(CM) = 1.6V 2.0 VITH vs VRUN/SS VOSENSE = 0.7V 75 1.5 1.0 65 0.5 60 –40 –15 85 10 35 60 TEMPERATURE (°C) 110 135 0 0 1 2 3 4 VRUN/SS (V) 5 6 1735-1 G15 1735-1 G18 ITH Voltage vs Load Current 2.5 100 Output Current vs Duty Cycle IOUT/IMAX (SYNCHRONIZED) 80 IOUT/IMAX (FREE RUN) 1.5 60 1.0 Burst Mode OPERATION 40 0.5 20 fSYNC = fO 0 0 20 40 60 DUTY CYCLE (%) 80 100 1735-1 G14 0 6 0 1 2 3 4 LOAD CURRENT (A) 5 6 1735-1 G17 5 LTC1735-1 TYPICAL PERFOR A CE CHARACTERISTICS Oscillator Frequency vs Temperature 300 COSC = 47pF 280 –2 270 –3 PGOOD PIN CURRENT (µA) 290 RUN/SS CURRENT (µA) FREQUENCY (kHz) 260 250 –40 –15 60 35 10 85 TEMPERATURE (°C) Start-Up VOUT 1V/DIV VRUN/SS 5V/DIV IL 5A/DIV VOUT 10mV/DIV VIN = 15V VOUT = 1.6V RLOAD = 0.16Ω 5ms/DIV VOUT(RIPPLE) (Burst Mode Operation) ILOAD = 1.5A VOUT 20mV/DIV FIGURE 1 VOUT 50mV/DIV IL 5A/DIV VIN = 15V VOUT = 1.6V 5µs/DIV 6 UW 110 1735-1 G19 RUN/SS Pin Current vs Temperature 0 VRUN/SS = 0V 0 PGOOD Pin Current vs Temperature VPGOOD = 0.85V –1 –0.2 –0.4 –0.6 –4 –0.8 135 –5 –40 –15 60 35 10 85 TEMPERATURE (°C) 110 135 –1.0 –40 –15 60 35 10 85 TEMPERATURE (°C) 110 135 1735-1 G20 1735-1 G21 VOUT(RIPPLE) (Synchronized) ILOAD = 10mA FIGURE 1 VOUT 20mV/DIV VOUT(RIPPLE) (Burst Mode Operation) ILOAD = 50mA FIGURE 1 IL 5A/DIV 1735-1 G22 IL 5A/DIV EXT SYNC f = fO VIN = 15V VOUT = 1.6V 10µs/DIV 1735-1 G23 VIN = 15V VOUT = 1.6V 50µs/DIV 1735-1 G24 Load Step (Burst Mode Operation) FIGURE 1 VOUT 50mV/DIV Load Step (Continuous Mode) FIGURE 1 IL 5A/DIV IL 5A/DIV 1735-1 G25 10mA TO 11A LOAD STEP VIN = 15V VOUT = 1.6V 10µs/DIV 1735-1 G26 0A TO 11A LOAD STEP PGOOD = 0V VIN = 15V VOUT = 1.6V 10µs/DIV 1735-1 G27 LTC1735-1 PI FU CTIO S COSC (Pin 1): External capacitor COSC from this pin to ground sets the operating frequency. RUN/SS (Pin 2): Combination of Soft-Start and Run Control Inputs. A capacitor to ground at this pin sets the ramp time to full current output. The time is approximately 1.25s/µF. Forcing this pin below 1.5V causes the device to be shut down. In shutdown all functions are disabled. Latchoff overcurrent protection is also invoked via this pin as described in the Applications Information section. ITH (Pin 3): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 2.4V. PGOOD (Pin 4): Open-Drain Logic Output and Forced Continuous/Synchronization Input. The PGOOD pin is pulled to ground when the voltage on the VOSENSE pin is not within ± 7.5% of its nominal set point. If power good indication is not needed, this pin can be tied to ground to force continuous synchronous operation. Clocking this pin with a signal above 1.5VP-P synchronizes the internal oscillator to the external clock. Synchronization only occurs while the main output is in regulation (PGOOD not internally pulled low). When synchronized, Burst Mode operation is disabled but cycle skipping is allowed at low load currents. This pin requires a pull-up resistor for power good indication. Do not connect this pin directly to an external source (or INTVCC). Do not exceed INTVCC on this pin. SENSE – (Pin 5): The (–) Input to the Current Comparator. SENSE + (Pin 6): The (+) Input to the Current Comparator. Built-in offsets between SENSE + and SENSE – pins in conjunction with RSENSE set the inductor current trip threshold. VOSENSE (Pin 7): Receives the feedback voltage from an external resistive divider across the output. SGND (Pin 8): Small-Signal Ground. All small-signal components such as COSC, CSS, the feedback divider plus the loop compensation resistors and capacitor(s) should single-point tie to this pin. This pin should, in turn, connect to PGND. EXTVCC (Pin 9): Input to the Internal Switch Connected to INTVCC. This switch closes and supplies VCC power whenever EXTVCC is higher than 4.7V. See EXTVCC connection in Applications Information section. Do not exceed 7V on this pin and ensure EXTVCC is ≤ VIN. PGND (Pin 10): Driver Power Ground. This pin connects to the source of the bottom N-channel MOSFET, the anode of the Schottky diode and the (–) terminal of CIN. BG (Pin 11): High Current Gate Drive for the Bottom N-Channel MOSFET. Voltage swing at this pin is from ground to INTVCC . INTVCC (Pin 12): Output of the Internal 5.2V Low Dropout Regulator and EXTVCC Switch. The driver and control circuits are powered from this voltage. Decouple to power ground with a 1µF ceramic capacitor placed directly adjacent to the IC together with a minimum of 4.7µF tantalum or other low ESR capacitor. VIN (Pin 13): Main Supply Pin. This pin must be closely decoupled to power ground. SW (Pin 14): Switch Node Connection to Inductor and Bootstrap Capacitor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. BOOST (Pin 15): Supply to Topside Floating Driver. The bootstrap capacitor is returned to this pin. Voltage swing at this pin is from a diode drop below INTVCC to VIN + INTVCC. TG (Pin 16): High Current Gate Drive for Top N-Channel MOSFET. This is the output of a floating driver with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. U U U 7 LTC1735-1 FU CTIO AL DIAGRA INTVCC 100k PGOOD 4 COSC 1 COSC SGND 8 SYNC C – + 1.2V FORCE BOT DROP OUT DET 0.74V 0.86V + – OV S Q R TOP ON 0.55V + – 2.4V 2k 7 R1 R2 – + EA 0.86V SD RUN SOFTSTART + OVERCURRENT LATCHOFF RC RUN/SS CSS 2 CC 3 ITH gm =1.3m Ω VOSENSE VFB 0.8V ICMP I1 – + 45k 45k SD – + I2 IREV B 0.8V 0.17µA FC – + TOP F BOOST 15 TG 16 SW BOT SWITCH LOGIC 14 D1 L RSENSE CB INTVCC OSC – + 1.2µA 4(VFB) 6V SLOPE COMP OPERATIO (Refer to Functional Diagram) Main Control Loop: The LTC1735-1 uses a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator I1 resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on Pin ITH, which is the output of error amplifier EA. Pin VOSENSE, described in the Pin Functions, allows EA to receive an output feedback voltage VFB from the external resistive divider. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until 8 W VIN 13 VIN 0.8V REF UVL INTVCC DB U U U + CIN + VOUT COUT – + + 3mV – BOT INTVCC VIN 5.2V LDO REG + – 12 BURST DISABLE FC A + CINTVCC INTVCC BUFFERED ITH 30k 30k 4.8V BG 11 PGND SENSE + 6 5 SENSE – EXTVCC 9 10 1735-1 FD the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from INTVCC through an external Schottky diode when the top MOSFET is turned off. As VIN decreases towards VOUT, the converter will attempt to turn on the top MOSFET continuously (“dropout’’). A dropout counter detects this condition and forces the top MOSFET to turn off for about 500ns every tenth cycle to recharge the bootstrap capacitor. LTC1735-1 OPERATIO The main control loop is shut down by pulling Pin 2 (RUN/ SS) low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. If VOUT has not reached 70% of its final value when CSS has charged to 4.1V, latchoff can be invoked as described in the Applications Information section. The internal oscillator can be synchronized to an external clock applied though a series resistor to the PGOOD pin and can lock to a frequency between 90% and 130% of its nominal rate set by capacitor COSC. An overvoltage comparator OV guards against transient overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Foldback current limiting for an output shorted to ground is provided by amplifier A. As VOSENSE drops below 0.6V, the buffered ITH input to the current comparator is gradually pulled down to a 0.86V clamp. This reduces peak inductor current to about 1/4 of its maximum value. Low Current Operation The LTC1735-1 has three low current modes controlled by the PGOOD pin. Burst Mode operation is selected when the PGOOD pin is above 0.8V (typically tied through a resistor to INTVCC). During Burst Mode operation, if the error amplifier drives the ITH voltage below 0.86V, the buffered ITH input to the current comparator will be clamped at 0.86V. The inductor current peak is then held at approximately 20mV/RSENSE (about 1/4 of maximum output current). If ITH then drops below 0.5V, the Burst Mode comparator B will turn off both MOSFETs to maximize efficiency. The load current will be supplied solely by the output capacitor until ITH rises above the 60mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by comparator F when the PGOOD pin is brought below 0.8V. This forces U (Refer to Functional Diagram) continuous operation and assists in controlling voltage regulation. If the output voltage is not within 7.5% of its nominal value the PGOOD open-drain output will be pulled low and Burst Mode operation will be disabled. Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff The RUN/SS capacitor, CSS, is used initially to limit the inrush current of the switching regulator. After the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, CSS is used as a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal output voltage, CSS begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing a current > 5µA at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of CSS during an overcurrent and/or shortcircuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the internal circuitry of the LTC1735-1 is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5.2V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC is raised above 4.7V, the internal regulator is turned off and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source, such as the primary or a secondary output of the converter itself, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. To provide clean start-up and to protect the MOSFETs, undervoltage lockout is used to keep both MOSFETs off until the input voltage is above 3.5V. 9 LTC1735-1 OPERATIO POWER GOOD A window comparator monitors the output voltage and its open-drain output is pulled low when the divided down output voltage (appearing at the VOSENSE pin) is not within ± 7.5% of the reference voltage of 0.8V. During a programmed output voltage transition (i.e., a transition from 1.55V to 1.3V) the PGOOD open-drain output will be pulled low and Burst Mode operation will be disabled until the output voltage is within 7.5% of its newly programmed value. When the PGOOD pin is driven by an external oscillator through a series resistor, cycle-skipping operation is invoked and the internal oscillator is synchronized to the external clock by comparator C. In this mode, the 25% minimum inductor current clamp is removed, providing low noise, constant frequency discontinuous operation APPLICATIO S I FOR ATIO The basic LTC1735-1 application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, COSC and L can be chosen. Next, the power MOSFETs and D1 are selected. The operating frequency and the inductor are chosen based largely on the desired amount of ripple current. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specifications. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection For Output Current RSENSE is chosen based on the required output current. The LTC1735-1 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. 10 U W U U U (Refer to Functional Diagram) over the widest possible output current range. This constant frequency operation is not quite as efficient as Burst Mode operation, but does provide a lower noise, constant frequency operation. When the power good window comparator indicates the output is not in regulation, the PGOOD pin is pulled to ground and synchronization is inhibited. Obviously when driving the PGOOD pin with an external clock the power good indication is not available unless additional circuitry is added. If the PGOOD pin is tied to ground, continuous operation is forced. This operation is the least efficient mode, but is desirable in certain applications. The output can source or sink current in this mode. When forcing continuous operation and sinking current, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels—BEWARE. Allowing a margin for variations in the LTC1735-1 and external component values yields: RSENSE = 50mV IMAX COSC Selection for Operating Frequency and Synchronization The choice of operating frequency and inductor value is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The LTC1735-1 uses a constant frequency architecture with the frequency determined by an external oscillator capacitor COSC. Each time the topside MOSFET turns on, the voltage on COSC is reset to ground. During the on-time, COSC is charged by a fixed current. When the voltage on the capacitor reaches 1.19V, COSC is reset to ground. The process then repeats. LTC1735-1 APPLICATIO S I FOR ATIO The value of COSC is calculated from the desired operating frequency assuming no external clock input on the PGOOD pin:  1.61(107 )  COSC(pF) =   – 11    Frequency  A graph for selecting COSC versus frequency is given in Figure 2. The maximum recommended switching frequency is 550kHz . The internal oscillator runs at its nominal frequency (fO) when the PGOOD pin is pulled high (to INTVCC) though a series resistor or connected to ground. Clocking the PGOOD pin above and below 1.2V will cause the internal oscillator to injection-lock to an external clock signal applied to the PGOOD pin with a frequency between 0.9fO and 1.3fO. The clock high level must exceed 1.3V for at least 0.3µs, and the clock low level must be less than 0.3V for at least 0.3µs. The top MOSFET turn-on will synchronize with the rising edge of the external clock. Attempting to synchronize to too high of an external frequency (above 1.3fO) can result in inadequate slope compensation and possible loop instability at high duty cycles. If this condition exists, simply lower the value of COSC so (fEXT = fO) according to Figure 2. 100.0 87.5 75.0 COSC VALUE (pF) 62.5 50.0 37.5 25.0 12.5 0 0 100 200 300 400 500 OPERATING FREQUENCY (kHZ) 600 1735-1 F02 Figure 2. Timing Capacitor Value When synchronized to an external clock, Burst Mode operation is disabled but the inductor current is not allowed to reverse. The 25% minimum inductor current U clamp present in Burst Mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. In this mode the synchronous MOSFET is forced on once every 10 clock cycles to recharge the bootstrap capacitor. This minimizes audible noise while maintaining reasonably high efficiency. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL = V 1 VOUT 1 – OUT  ( f)(L) VIN   Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.3 to 0.4(IMAX). Remember, the maximum ∆IL occurs at the maximum input voltage. The inductor value also has an effect on low current operation. The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on. Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. W U U 11 LTC1735-1 APPLICATIO S I FOR ATIO Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1735-1: an N-channel MOSFET for the top (main) switch, and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.2V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1735-1 applications. The only exception is when low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Kool Mµ is a registered trademark of Magnetics, Inc. 12 U Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1735-1 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN VIN – VOUT VIN Synchronous Switch Duty Cycle = The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT (IMAX )2 (1+ δ)RDS(ON) + VIN k(VIN ) (IMAX )(C RSS )( f) 2 W U U PSYNC = VIN – VOUT (IMAX )2 (1+ δ)RDS(ON) VIN where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom LTC1735-1 APPLICATIO S I FOR ATIO MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 3A Schottky is generally a good size for 10A to 12A regulators due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. CIN Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT / VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS V  V ≅ IO(MAX) OUT  IN – 1 VIN  VOUT  1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. COUT Selection The selection of COUT is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. The output ripple (∆VOUT) in continuous mode is determined by:  1 ∆VOUT ≈ ∆IL  ESR +  8 fCOUT   where f = operating frequency, COUT = output capacitance, and ∆IL= ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. With ∆IL = 0.3IOUT(MAX) and allowing for 2/3 of the ripple due to ESR, U the output ripple will be less than 50mV at max VIN assuming: COUT required ESR < 2.2 RSENSE COUT > 1/(8fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output voltage does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. The selection of output capacitors for CPU or other applications with large load current transients is primarily determined by the voltage tolerance specifications of the load. The resistive component of the capacitor, ESR, multiplied by the load current change plus any output voltage ripple must be within the voltage tolerance of the load (CPU). The required ESR due to a load current step is: RESR < ∆V/∆I where ∆I is the change in current from full load to zero load (or minimum load) and ∆V is the allowed voltage deviation (not including any droop due to finite capacitance). The amount of capacitance needed is determined by the maximum energy stored in the inductor. The capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. The opposite load current transition is generally determined by the control loop OPTI-LOOP components, so make sure not to over compensate and slow down the response. The minimum capacitance to assure the inductors’ energy is adequately absorbed is: W U U () COUT > 2( ∆V )VOUT L ∆I 2 where ∆I is the change in load current. 13 LTC1735-1 APPLICATIO S I FOR ATIO Manufacturers such as Nichicon, United Chemicon and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications, multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very costeffective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult manufacturers for other specific recommendations. INTVCC Regulator An internal P-channel low dropout regulator produces the 5.2V supply that powers the drivers and internal circuitry within the LTC1735-1. The INTVCC pin can supply a maximum RMS current of 50mA and must be bypassed to ground with a minimum of 4.7µF tantalum, 10µF special polymer or low ESR type electrolytic capacitor. A 1µF ceramic capacitor placed directly adjacent to the 14 U INTVCC and PGND IC pins is highly recommended. Good bypassing is required to supply the high transient currents required by the MOSFET gate drivers. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1735-1 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional loading of INTVCC also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 5.2V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC current is supplied by the internal 5.2V linear regulator. Power dissipation for the IC in this case is highest, (VIN)(IINTVCC), and overall efficiency is lowered. The gate charge current is dependant on operating frequency as discussed in the Efficiency Consideration section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC1735CS-1 is limited to less than 17mA from a 30V supply when not using the EXTVCC pin as follows: TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. EXTVCC Connection The LTC1735-1 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. Whenever the EXTVCC pin is above 4.7V the internal 5.2V regulator shuts off, the switch closes and INTVCC power is supplied via EXTVCC until EXTVCC drops below 4.5V. This allows the MOSFET gate drive and control power to be derived from the output or other external source during normal operation. When the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN. W U U LTC1735-1 APPLICATIO S I FOR ATIO Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 5V regulators this simply means connecting the EXTVCC pin directly to VOUT. However, for dynamic (VID-like) programmed regulators and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5.2V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V to 7V output regulator and provides the highest efficiency. For output voltages > 5V, EXTVCC is required to connect to VOUT so the SENSE pins absolute maximum ratings are not exceeded. 3. EXTVCC Connected to an External Supply (This Option is the Most Likely Used). If an external supply is available in the 5V to 7V range, such as notebook main 5V system power, it may be used to power EXTV CC providing it is compatible with the MOSFET gate drive requirements. This is the typical case as the 5V power is almost always present and is derived by another high efficiency regulator. 4. EXTVCC Connected to an Output-Derived Boost Network. For low output voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive boost winding or capacitive charge pump circuits. Refer to the LTC1735 data sheet for details. The charge pump has the advantage of simple magnetics. Output Voltage Programming The output voltage is set by an external resistive divider according to the following formula:  R2 VOUT = 0.8V 1 +   R1 U VOUT R2 VOSENSE LTC1735-1 SGND 1735-1 F03 W U U 47pF R1 Figure 3. Setting the LTC1735-1 Output Voltage The resistive divider is connected to the output as shown in Figure 3 allowing remote voltage sensing. The output voltage can be digitally set to voltages between any two levels with the addition of a resistor and small signal N-channel MOSFET as shown in the circuit of Figure 1. Dynamic output voltage selection can be accomplished with this technique. Output voltages of 1.30V and 1.55V are set by the resistors R1 to R3. With the gate of the MOSFET low, (VG = 0), the output voltage is set by the ratio of R1 to R2. When the MOSFET is on (VG = high), the output voltage is the ratio of R1 to the parallel combination of R2 and R3. With the available power good output (PGOOD), the circuit in Figure 1 creates a low cost Intel Pentium III mobile processor compliant supply. The LTC1735-1 has remote sense capability. The top of the internal resistive divider is connected to VOSENSE and is referenced to the SGND pin. This allows a kelvin connection for remotely sensing the output voltage directly across the load, eliminating any PC board trace resistance errors. Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. Note that the voltage across CB is about a diode drop below INTVCC. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage SW rises to VIN and the BOOST pin rises to VIN + INTVCC. The value of the boost capacitor CB needs to be 100 times greater than the total input capacitance of the topside MOSFET. In most applications 0.1µF to 0.33µF is adequate. The reverse breakdown on DB must be greater than VIN(MAX) . 15 LTC1735-1 APPLICATIO S I FOR ATIO When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. SENSE +/ SENSE – Pins The common mode input range of the current comparator is from 0V to 1.1(INTVCC). Continuous linear operation is guaranteed throughout this range allowing output voltages anywhere from 0.8V to 7V. A differential NPN input stage is used and is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This causes current either to be sourced or sunk by these pins depending on the output voltage. If the output voltage is below 2.4V, current will flow out of both SENSE pins to the main output. This forces a minimum load current that can be fulfilled by the VOUT resistive divider. The maximum current flowing out of the SENSE pins is: ISENSE+ + ISENSE– = (2.4V – VOUT)/24k Since VOSENSE is servoed to the 0.8V reference voltage, we can choose R1 in Figure 3 to have a maximum value to absorb this current:  0.8V  R1(Max) = 24k    2.4V – VOUT  Regulating an output voltage of 1.8V, the maximum value of R1 should be 32k. Note that for output voltages above 2.4V no maximum value of R1 is necessary to absorb the sense currents; however, R1 is still bounded by the VOSENSE feedback current. Soft-Start/Run Function The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC1735-1. Soft-start reduces surge currents from VIN by gradually increasing the controller’s current limit ITH(MAX). This pin can also be used for power supply sequencing. Pulling the RUN/SS pin below 1.5V puts the LTC1735-1 into a low quiescent current shutdown (IQ < 25µA). This pin can be driven directly from logic as shown in Figures 4 and 5. Releasing the RUN/SS pin allows an internal 1.2µA current source to charge up the external soft-start 16 U capacitor CSS. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: W U U TDELAY = 1.5V CSS = 1.25s/µF CSS 1.2µA ( ) When the voltage on RUN/SS reaches 1.5V the LTC1735-1 begins operating with a current limit at approximately 25mV/RSENSE. As the voltage on RUN/SS increases from 1.5V to 3V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.25s/µF to reach full current. Ramping the output current slowly reduces the starting surge current required from the input supply. Diode D1 in Figure 4 and Figure 5 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. This diode and CSS can be deleted if soft-start is not needed. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram). 3.3V OR 5V D1 CSS CSS RUN/SS RUN/SS 1735-1 F04 Figure 4. RUN/SS Pin Interfacing VIN 3.3V OR 5V D1 RSS RUN/SS RSS D1 CSS CSS RUN/SS INTVCC (a) (b) 1735-1 F05 Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to shut off the controller and latchoff when an overcurrent condition is detected. The RUN/SS capacitor CSS is used initially to turn on and limit the inrush current of the controller. After the controller has been started and given adequate time to charge up the output capacitor and provide full load LTC1735-1 APPLICATIO S I FOR ATIO current, CSS is used as a short-circuit timer. If the output voltage falls to less than 70% of its nominal output voltage after CSS reaches 4.1V, the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and CSS begins discharging. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing a current > 5µA at a compliance of 5V to the RUN/SS pin as shown in Figure 5a. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit conditions. When deriving the 5µA current from VIN as in Figure 5a, current latchoff is always defeated. The diode connecting this pull-up resistor to INTVCC , as in Figure 5b, eliminates any extra supply current during shutdown while eliminating the INTVCC loading from preventing controller start-up. If the voltage on CSS does not exceed 4.1V, the overcurrent latch is not armed and the function is disabled. Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. Defeating this feature will easily allow troubleshooting of the circuit and PC layout. The internal short circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. After the design is complete, a decision can be made whether to enable the latchoff feature. The value of the soft-start capacitor CSS will need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT) (10 –4) (RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. Fault Conditions: Current Limit and Current Foldback The LTC1735-1 current comparator has a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. U The LTC1735-1 includes current foldback to help further limit load current when the output is shorted to ground. If the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mV to 30mV. Under short-circuit conditions with very low duty cycles, the LTC1735-1 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be conducting the peak current. The shortcircuit ripple current is determined by the minimum ontime tON(MIN) of the LTC1735-1 (less than 200ns), the input voltage, and inductor value: ∆IL(SC) = tON(MIN)(VIN /L) The resulting short circuit-current is: ISC = 30mV 1 + ∆IL(SC) RSENSE 2 The current foldback function is always active and is not effected by the current latchoff function. Fault Conditions: Output Overvoltage Protection (Crowbar) The output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. This condition causes huge currents to flow, much greater than in normal operation. This feature is designed to protect against a shorted top MOSFET; it does not protect against a failure of the controller itself. The comparator (OV in the Functional Diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed the top MOSFET is turned off and the bottom MOSFET is forced on. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automatically resumes. Note that dynamically changing the output voltage may cause overvoltage protection to be momentarily activated during output voltage decreases. This will not cause permanent latchoff nor will it disrupt the desired voltage change. With soft-latch overvoltage protection, dynamically changing the output voltage is allowed and the overvoltage protection tracks the newly programmed output voltage, always protecting the load (CPU). W U U 17 LTC1735-1 APPLICATIO S I FOR ATIO Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest amount of time that the LTC1735-1 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN (f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1735-1 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC1735-1 in a properly configured application is less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases as shown in Figure 6. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule keep the inductor ripple current equal or greater than 30% of IOUT(MAX) at VIN(MAX). 250 200 MINIMUM ON-TIME (ns) 150 100 50 0 0 10 20 ∆IL /IOUT(MAX) (%) 30 40 1736-1 F06 Figure 6. Minimum On-Time vs ∆IL 18 U PGOOD Pin Operation The PGOOD pin is a multifunction pin intended primarily to indicate when the output voltage is within ± 7.5% of its nominal set point. A window comparator monitors the VOSENSE pin and activates an open-drain internal MOSFET that pulls down the PGOOD pin when the output voltage is out of regulation. Normally a 10k to 100k pull-up resistor is connected to this pin from a voltage source such as INTVCC. Do not apply a voltage greater than INTVCC to this pin. Dynamically changing the output voltage between two voltage levels greater that 7.5% apart from each other will invoke the power good indication, causing the PGOOD output to go low until the new output voltage is reached. When the DC voltage on the PGOOD pin drops below its 0.8V threshold, continuous mode operation is forced. In this case, the top and bottom MOSFETs continue to be driven synchronously regardless of the load on the main output. Burst Mode operation is disabled and current reversal is allowed in the inductor. This mode is forced whenever the output voltage is not within its 7.5% window. In addition to providing a power good output, the PGOOD pin provides a logic input to force continuous synchronous operation and allow synchronization to an external clock. The internal LTC1735-1 oscillator can be synchronized to an external oscillator by applying a clock signal to the PGOOD pin though a series resistor with a signal amplitude above 1.5VP-P. When synchronized to an external frequency, Burst Mode operation is disabled but cycle skipping is allowed at low load currents since current reversal is inhibited. The bottom gate will come on every 10 clock cycles to assure the bootstrap capacitor is kept refreshed. The rising edge of an external clock applied to the PGOOD pin starts a new cycle. If the output voltage is not within the 7.5% window around its nominal set point, the open-drain PGOOD output will pull low, disabling the external synchronization. The following table summarizes the possible states available on the PGOOD pin. W U U LTC1735-1 APPLICATIO S I FOR ATIO Table 1 PGOOD PIN DC Voltage: 0V to 0.7V CONDITION No Power Good Indication Burst Mode Operation Disabled/Forced Continuous Current Reversal Enabled Power Good Indication Burst Mode, No Current Reversal When Power is Good No Power Good Indication Burst Mode Operation Disabled No Current Reversal Resistor Pull-Up to INTVCC (or Other DC Voltage Less Than INTVCC) Resistor to Ext Clock: (0V to 1.5V) The circuit shown in Figure 7 provides a power good output and forces continuous operation. Transistor Q1 keeps the voltage at the PGOOD pin below 0.8V thus disabling Burst Mode operation. When the window comparator indicates the output voltage is not within its 7.5% window, the base of Q1 is pulled to ground and the power good output appearing at the collector of Q2 goes low. INTVCC 470k 100k 10k POWER GOOD PGOOD PIN 4 Q1 1735-1 F07 Q2 Figure 7. Forced Continuous Operation with Power Good Indication Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1735-1 circuits: 1) LTC1735-1 VIN current, 2) INTVCC current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver U and control currents. VIN current results in a small (< 0.1%) loss that increases with VIN. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom-side MOSFETs. By powering EXTVCC from an output-derived source (or other high efficiency source), the additional VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For example, in a 15V to 1.8V application, 10mA of INTVCC current results in approximately 1.2mA of VIN current. This reduces the midcurrent loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the MOSFETs, inductor and current shunt. In continuous mode, the average output current flows through L and RSENSE, but is “chopped” between the topside main MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.02Ω, RL = 0.03Ω, and RSENSE = 0.01Ω, then the total resistance is 0.06Ω. This results in losses ranging from 3% to 17% as the output current increases from 1A to 5A for a 1.8V output, or 4% to 20% for a 1.5V output. Efficiency varies as the inverse square of VOUT for the same external components and power level. I2R losses cause the efficiency to drop at high output currents. 4. Transition losses apply only to the topside MOSFET(s), and only become significant when operating at high input voltages (typically 12V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f W U U 19 LTC1735-1 APPLICATIO S I FOR ATIO Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and a very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum of 0.01Ω to 0.02Ω of ESR. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been 20 U determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/ DC ratio cannot be used to determine phase margin. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. Improve Transient Response and Reduce Output Capacitance with Active Voltage Positioning Fast load transient response, limited board space and low cost are normal requirements of microprocessor power supplies. Active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor where a typical load step can be from 0.2A to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the microprocessor must be held to about ± 0.1V of nominal in spite of these load current steps. Since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. Capacitor ESR and ESL primarily determine the amount of droop or overshoot in the output voltage. Normally, several capacitors in parallel are required to meet microprocessor transient requirements. Active voltage positioning is a form of deregulation. It sets the output voltage high for light loads and low for heavy loads. When load current suddenly increases, the output voltage starts from a level higher than nominal so the output voltage can droop more and stay within the specified voltage range. When load current suddenly W U U LTC1735-1 APPLICATIO S I FOR ATIO decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. Less output capacitance is required when voltage positioning is used because more voltage variation is allowed on the output capacitors. Active voltage positioning can be implemented using the OPTI-LOOP architecture of the LTC1735-1 and two resistors connected to the ITH pin. An input voltage offset is introduced when the error amplifier has to drive a resistive load. This offset voltage is limited to ± 30mV at the input of the error amplifier. The resulting change in output voltage is the product of input offset voltage and the feedback voltage divider ratio. Figure 8 shows a CPU-core-voltage regulator with active voltage positioning. Resistors R1 and R5 force the input voltage offset that adjusts the output voltage according to the load current level. To select values for R1 and R5, first determine the amount of output deregulation allowed. The actual specification for a typical microprocessor allows the output to vary ± 0.112V. The LTC1735-1 reference R3 680k R4 100k R1 PGOOD 27k C1 39pF 1 C2 0.1µF 2 R2 100k C4 100pF C3 100pF 3 COSC TG 16 Q1 FDS6680A R5 100k C9, C19: TAIYO YUDEN JMK107BJ105 C10: KEMET T494A475M010AS C12 TO C14: TAIYO YUDEN GMK325F106 C15 TO C18: PANASONIC EEFUE0G181R D1: CENTRAL SEMI CMDSH-3 D2: MOTOROLA MBRS340 L1: PANASONIC ETQP6F1R0SA Q1 TO Q3: FAIRCHILD FDS6680A R5: IRC LRF2512-01-R003-J U1: LINEAR TECHNOLOGY LTC1735CS-1 L1 1µH D2 MBRS340 Q2, Q3 FDS6680A ×2 R6 0.003Ω C11 330pF R7 10k C19 1µF C7 0.1µF C12 TO C14 10µF 35V RUN/SS BOOST 15 C8 0.22µF SW U1 LTC1735-1 13 4 PGOOD VIN 5 C5 1000pF SENSE – SENSE + 12 ITH 14 D1 CMDSH-3 INTVCC 6 C6 47pF 7 BG 11 C9 1µF VOSENSE PGND 10 8 SGND EXTVCC 9 5V (OPTIONAL) Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning U accuracy is ±1%. Using 1% tolerance resistors, the total feedback divider accuracy is about 1% because both feedback resistors are close to the same value. The resulting setpoint accuracy is ± 2% so the output transient voltage cannot exceed ± 0.082V. For VOUT = 1.5V, the maximum output voltage change controlled by the ITH pin would be: W U U ∆VOSENSE = Input Offset Voltage • VOUT VREF ± 0.03V • 1.5 = = ±56mV 0.8 V With optimum resistor values at the ITH pin, the output voltage will swing from 1.55V at minimum load to 1.44V at full load. At this output voltage, active voltage positioning provides an additional ± 56mV to the allowable transient voltage on the output capacitors, a 68% improvement over the ± 82mV allowed without active voltage positioning. VIN 7.5V TO 24V GND VOUT 1.5V 15A + C10 4.7µF 10V + R8 11.5k C15 TO C18 180µF 4V GND 1735-1 F08 21 LTC1735-1 APPLICATIO S I FOR ATIO The next step is to calculate the ITH pin voltage, VITH, scale factor. The VITH scale factor reflects the ITH pin voltage required for a given load current in continuous inductor current operation. VITH controls the peak sense resistor voltage, which represents the DC output current plus one half of the peak-to-peak inductor current. The no load to full load VITH range is from 0.3V to 2.4V, which controls the sense resistor voltage from 0V to the ∆VSENSE(MAX) voltage of 75mV. For the circuit shown in Figure 8, the calculated VITH scale factor is: VITH Scale Factor = = VITH Range • Sense Re sistor Value ∆VSENSE(MAX) (2.4V – 0.3V) • 0.003 = 0.084V/A 0.075V Assuming continuous inductor current, VITH is:   ∆I  VITH = IOUTDC + L  • VITH Scale Factor  2   + VITH Offset At full load current:    5A VITH(MAX) =  15A + P−P  • 0.084V/A  + 0.3V 2     = 1.77 V At minimum load current:    2A VITH(MIN) =  0.2A + P−P  • 0.084V/A  + 0.3V 2     = 0.40 V Notice that ∆IL, the peak-to-peak inductor current, changes from light load to full load. Increasing the DC inductor current decreases the permeability of the inductor core material, which decreases the inductance and increases ∆IL. The amount of inductance change is a function of the inductor design. If the circuit shown in Figure 8 sustained continuous inductor current operation, the error amplifier would control 22 U VITH from 0.40V at light load to 1.77V at full load, a 1.37V change. During Burst Mode operation, the LTC1735-1 output voltage is controlled by a comparator, not the error amplifier. Even though the error amplifier is not used in Burst Mode operation, it is necessary to assume linear operation for all error amplifier gain calculations. To create the ± 30mV input offset error, the voltage gain of the error amplifier must be limited. The desired gain is: AV = ∆VITH 1.37 V = = 22.8 Input Offset Error 2(0.03V) Connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. The value of this resistor is: RITH = AV 22.8 = = 17.54k Error Amplifier gm 1.3ms To center the output voltage variation, VITH must be centered so that no ITH pin current flows when the output voltage is nominal. VITH(NOM) is the average voltage between VITH at maximum output current and minimum output current: W U U VITH(NOM) = VITH(MAX) – VITH(MIN) + VITH(MIN) 2 1.77 V – 0.40 V = + 0.40 V = 1.085V 2 The Thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor R5 that sources current into the ITH pin and resistor R1 that sinks current to SGND. To calculate the resistor values, first determine the ratio between them: k= VINTVCC – VITH(NOM) 5.2V – 1.085V = = 3.79 VITH(NOM) 1.085V VINTVCC is equal to VEXTVCC or 5.2V if EXTVCC is not used. Resistor R5 is: R5 = (k + 1) • RITH = (3.79 + 1) • 17.54k = 84.0k LTC1735-1 APPLICATIO S I FOR ATIO Resistor R1 is: R1 = (k + 1) • RITH (3.79 + 1) • 17.54k = = 22.17k k 3.79 Unfortunately, PCB noise can add to the voltage developed across the sense resistor, R6, causing the ITH pin voltage to be slightly higher than calculated for a given output current. The amount of noise is proportional to the output current level. This PCB noise does not present a serious problem but it does change the effective value of R6 so the calculated values of R1 and R5 may need to be adjusted to achieve the required results. Since PCB noise is a function of the layout, it will be the same on all boards with the same layout. Figures 9 and 10 show the transient response before and after active voltage positioning is implemented. Notice that active voltage positioning reduced the transient response from almost 200mVP-P to a little over 100mVP-P. Refer to Design Solutions 10 for more information about active voltage positioning. 1.582V 100mV/DIV 1.50V 1.418V 15A LOAD CURRENT 0.2A 0A VIN = 12V VOUT = 1.5V FIGURE 8 CIRCUIT OUTPUT VOLTAGE 5A/DIV 50µs/DIV 1735-1 F09 Figure 9. Transient Response Without Active Voltage Positioning VIN = 12V VOUT = 1.5V 1.582V 100mV/DIV 1.50V 1.418V 15A LOAD CURRENT OUTPUT VOLTAGE FIGURE 8 CIRCUIT 5A/DIV 0.2A 0A 50µs/DIV 1735-1 F10 Figure 10. Transient Response with Active Voltage Positioning U Automotive Considerations: Plugging Into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an auto is the source of a number of nasty potential transients, including load dump, reverse battery and double battery. Load dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 11 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC1735-1 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V W U U VIN LTC1735-1 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 1735-1 F11 Figure 11. Plugging Into the Cigarette Lighter 23 LTC1735-1 APPLICATIO S I FOR ATIO Design Example As a design example, assume VIN = 12V (nominal), VIN = 22V (max), VOUT = 1.5V, IMAX = 12A and f = 300kHz, RSENSE and COSC can immediately be calculated: RSENSE = 50mV/12A = 0.042Ω COSC = 1.61(107)/(300kHz) – 11pF = 43pF Assume a 1.2µH inductor and check the actual value of the ripple current. The following equation is used : ∆IL = VOUT  VOUT  1–  (f)(L)  VIN  The highest value of the ripple current occurs at the maximum input and output voltages: ∆IL = 1.5V  1.5V  1–  = 3.9A 300kHz(1.2µH)  22V  The maximum ripple current is 32% of maximum output current, which is about right. Next, verify the minimum on-time of 200ns is not violated. The minimum on-time occurs at maximum VIN and minimum VOUT. tON(MIN) 1.5V = = = 227ns VIN(MAX)f 22V(300kHz) VOUT The power dissipation on the topside MOSFET can be easily estimated. Choosing a Fairchild FDS6612A results in; RDS(ON) = 0.03Ω, CRSS = 80pF. At maximum input voltage with T(estimated) = 50°C: PMAIN = 1.5V (12)2[1+ (0.005)(50°C – 25°C)](0.03Ω) 22V +1.7(22V ) (12A )(80pF )(300kHz) 2 = 568mW Because the duty cycle of the bottom MOSFET is much greater than the top, two larger MOSFETs must be paralleled. Choosing Fairchild FDS6680A MOSFETs yields a parallel RDS(ON) of 0.0065Ω. The total power dissipation for both bottom MOSFETs, again assuming T = 50°C, is: 24 U PSYNC = 22V – 1.5V (12A)2 (1.1)(0.0065Ω) 22V = 959mW Thanks to current foldback, the bottom MOSFET dissipation in short circuit will be less than under full-load conditions. CIN is chosen for an RMS current rating of at least 6A at temperature. COUT is chosen with an ESR of 0.01Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR(∆IL) = 0.01Ω(3.9A) = 39mVP-P Since the output voltage is below 2.4V, the output resistive divider will need to be sized to not only set the output voltage but also to absorb the SENSE pins specified input current. W U U  0.8 V  R1(MAX) = 24k   = 21.3k  2.4V – 1.5V  Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an output voltage of 1.512V. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1735-1. These items are also illustrated graphically in the layout diagram of Figure 12. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1735-1 PGND pin should tie to the ground plane close to the input capacitor(s). The SGND pin should then connect to PGND and all components that connect to SGND should make a single-point tie to the SGND pin. The synchronous MOSFET source should connect to the input capacitor(s) ground. 2. Does the VOSENSE pin connect directly to the feedback resistors? The resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. The 47pF capacitor from VOSENSE to SGND should be as close as possible to the LTC1735-1. Be careful locating the feedback resistors too far away from the LTC1735-1 APPLICATIO S I FOR ATIO LTC1735-1. The VOSENSE line should not be routed close to any other nodes with high slew rates. 3. Are the SENSE + and SENSE – leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE – should be as close as possible to the LTC1735-1. Ensure accurate current sensing with kelvin connections to the SENSE resistors shown in Figure 13. Series resistance can be added to the SENSE lines to increase noise rejection. 4. Does the (+) terminal of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). INTVCC COSC CSS RC CC2 CC 1 2 3 4 5 COSC RUN/SS ITH PGOOD SENSE – SENSE + VOSENSE SGND VIN INTVCC BG PGND EXTVCC 13 12 11 10 9 + LTC1735-1 1000pF 6 7 47pF 8 R2 Figure 12. LTC1735-1 Layout Diagram HIGH CURRENT PATH SENSE + SENSE – Figure 13. Kelvin Sensing RSENSE + U 5. Is the INTVCC decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. An additional 1µF ceramic placed immediately next to the INTVCC and PGND pins can help improve noise performance. 6. Keep the switching node (SW), Top Gate node (TG), and Boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” (Pins 9 to 16) of the LTC1735-1 and occupy minimum PC trace area. + TG BOOST SW 16 15 14 DB CB D1 CIN VIN Q1 W U U + 4.7µF Q2 – L1 – R1 COUT RSENSE + 1735-1 F12 VOUT 1735-1 F13 CURRENT SENSE RESISTOR (RSENSE) 25 LTC1735-1 TYPICAL APPLICATIONS 1.8V/5A Converter with Power Good INTVCC COSC 43pF CSS 0.1µF 2 RC 33k CC 470pF 3 100k 1 COSC TG 16 CB 0.1µF 15 Q1 Si4412DY VIN 4.5V TO 22V CIN 22µF 50V CER RUN/SS ITH LTC1735-1 CC2 220pF POWER GOOD 4 PGOOD SENSE – SENSE + 5 1000pF 6 47pF 7 VOSENSE 8 SGND CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V) with Burst Mode Operation Disabled VIN 5V 100k* COSC 39pF 1 CSS 0.1µF 2 INTVCC 10k POWER GOOD Q5 Q4 5 1000pF 6 47pF 7 VOSENSE PGND 10 SENSE + BG 11 1µF SENSE – INTVCC 12 100k 470k CC RC 220pF 20k CC2 220pF 4 CIN 150µF 6.3V ×2 *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 26 U 3 8 BOOST SW 14 L1 3.3µH RSENSE 0.01Ω R2 32.4k 1% Q2 Si4410DY MBRS140T3 R1 25.5k 1% SGND VIN 13 DB CMDSH-3 VOUT 1.8V 5A INTVCC 12 + 11 4.7µF + BG COUT 150µF 6.3V ×2 PANASONIC SP PGND 10 EXTVCC 9 OPTIONAL: CONNECT TO 5V COUT: PANASONIC EEFUEOG151R CIN: MARCON THCR70LE1H226ZT L1: PANASONIC ETQP6F3R3HFA RSENSE: IRC LR 2010-01-R010F 1735-1 TA02 COSC TG 16 CB 0.22µF 15 Q1 FDS6680A RUN/SS BOOST ITH LTC1735-1 PGOOD SW 14 L1 0.78µH RSENSE 0.004Ω R2 32.4k 1% R1 25.5k 1% SGND VIN 13 DB MBR0530 VOUT 1.5V 12A + 100pF 4.7µF Q2, Q3 FDS6680A ×2 MBRD835L + COUT 180µF 4V ×3 CO 47µF 10V SGND EXTVCC 9 VIN 5V COUT: PANASONIC EEFUEOG181R CIN: PANASONIC EEFUEOJ151R CO: TAIYO YUDEN LMK550BJ476MM-B L1: COILCRAFT 1705022P-781HC Q4, Q5: 2N2222 RSENSE: IRC LRF 2512-01-R004-J 1735-1 TA03 LTC1735-1 PACKAGE DESCRIPTION 0.007 – 0.0098 (0.178 – 0.249) 0.016 – 0.050 (0.406 – 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0° – 8° TYP 0.053 – 0.068 (1.351 – 1.727) 23 4 56 7 8 0.004 – 0.0098 (0.102 – 0.249) 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC GN16 (SSOP) 1098 S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.053 – 0.069 (1.346 – 1.752) 2 3 4 5 6 7 8 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP 0.050 (1.270) BSC S16 1098 27 LTC1735-1 TYPICAL APPLICATIO High Efficiency Dynamic Output Voltage Selectable CPU Power Supply for SpeedStep Enabled Processors PGOOD RUN R7 100k INTVCC JP1 LATCH-OFF R6 DISABLE 680k R8 4.7Ω VIN 4.5V TO 24V COSC 47pF CSS 0.1µF CC2 330pF RC1 33k CC1 47pF C1 47pF 1 2 3 4 5 CS1 1000pF 6 7 8 CF1 0.1µF 16 TG COSC 15 BOOST RUN/SS CB 0.22µF 14 ITH LTC1735-1 SW 13 D1 VIN PGOOD CMDSH-3 12 – SENSE INTVCC + C2 C4 11 SENSE + BG 1µF 4.7µF 10 PGND VOSENSE 9 5V EXTVCC SGND INPUT (OPTIONAL) R5 10Ω R4 10Ω RELATED PARTS PART NUMBER LTC1149 LTC1159 LT1375/LT1376 LTC1435A LTC1474/LTC1475 LTC1628 LTC1702 LTC1709 LTC1735 LTC1736 LTC1772 DESCRIPTION High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller 1.5A 500kHz Step-Down Switching Regulator High Efficiency Low Noise Synchronous Step-Down Controller, N-Ch Drive Ultralow Quiescent Current Step-Down Monolithic Switching Regulator Dual High Efficiency 2-Phase Step-Down Controller 550kHz Dual Output Synchronous Step-Down Controller PolyPhase Synchronous Controller with 5-Bit VID High Efficiency Synchronous Step-Down Contoller, N-Channel Drive High Efficiency Synchronous Step-Down Controller with 5-Bit VID Control SOT-23 High Efficiency Constant Frequency Step-Down Controller TM LTC1436A/LTC1436A-PLL High Efficiency Low Noise Synchronous Step-Down Converter, N-Ch Drive Adaptive Power and PolyPhase are trademarks of Linear Technology Corporation. 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U Q1 FDS6680A L1 1.2µH D2 MBRS340T3 Q2, Q3 FDS6680A ×2 CIN 22µF 50V CERAMIC ×2 RSENSE 0.004Ω R1 10k 0.5% CIN: MARCON THCR70E1H226ZT COUT: PANASONIC EEFVE06181R L1: PANASONIC ETQP6F1R2HFA RSENSE: IRC CRF2512-01-R004F VOUT 1.35V OR 1.60V 12A COUT 180µF 4V SP ×4 VSEL = 1: VOUT = 1.60V VSEL = 0: VOUT = 1.35V GND 1735-1 TA01 C2 47pF C3 47pF + R2 14.3k 0.5% R3 33.2k 1% Q4 2N7002 COMMENTS 100% DC, Std Threshold MOSFETs, VIN < 48V 100% DC, Logic Level MOSFETs, VIN < 40V High Efficiency Burst Mode Operation, 16-Pin Narrow SO Adaptive PowerTM Mode 20-Pin, 24-Pin SSOP 100% DC, 8-Pin MSOP, IQ = 10µA Antiphase Drive, 28-Pin SSOP, 3.5V ≤ VIN ≤ 36V Antiphase Drive, 24-Pin SSOP, VIN ≤ 7V Up to 42A, Minimum Input Capacitors, 1.3V ≤ VOUT ≤ 3.5V Burst Mode Opertion, 16-Pin Narrow SSOP Output Fault Protection, 24-Pin SSOP 100% DC, 550kHz, SOT-23, Current Mode 17351f LT/TP 0100 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1999