LTC1735CGN

FEATURES s s s s s s s s s LTC1735 High Efficiency Synchronous Step-Down Switching Regulator DESCRIPTIO The LTC®1735 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using a fixed frequency architecture. Burst ModeTM operation provides high efficiency at low load currents. The precision 0.8V reference is compatible with future microprocessor generations. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The operating frequency (synchronizable up to 500kHz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. A forced continuous control pin reduces noise and RF interference and can assist secondary winding regulation by disabling Burst Mode operation when the main output is lightly loaded. Protection features include internal foldback current limiting, output overvoltage crowbar and optional shortcircuit shutdown. Soft-start is provided by an external capacitor that can be used to properly sequence supplies. The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum). , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation. s s s s s s s Dual N-Channel MOSFET Synchronous Drive Synchronizable/Programmable Fixed Frequency Wide VIN Range: 3.5V to 36V Operation VOUT Range: 0.8V to 6V OPTI-LOOPTM Compensation Minimizes COUT ±1% Output Voltage Accuracy Internal Current Foldback Output Overvoltage Crowbar Protection Latched Short-Circuit Shutdown Timer with Defeat Option Very Low Dropout Operation: 99% Duty Cycle Forced Continuous Control Pin Optional Programmable Soft-Start Remote Output Voltage Sense Logic Controlled Micropower Shutdown: IQ < 25µA LTC1435 Pin Compatible with Minor Component Changes Available in 16-Lead Narrow SSOP and SO Packages APPLICATIO S s s s Notebook and Palmtop Computers, PDAs Cellular Telephones and Wireless Modems DC Power Distribution Systems TYPICAL APPLICATIO COSC 47pF CSS 0.1µF CC 330pF RC 33k COSC TG RUN/SS BOOST ITH SW CC2 100pF SGND 100pF VOSENSE BG SENSE – 1000pF SENSE + PGND INTVCC LTC1735 VIN DB CMDSH-3 L1 2µH CB 0.22µF M1 FDS6680A CIN 22µF 50V VIN 5V TO 24V COUT: PANASONIC EEFUEOG181R CIN: MARCON THCR70E1H226ZT L1: PANASONIC ETQP6FZR0HFA RSENSE: IRC LRF2010-01-R005J RSENSE 0.005Ω + 4.7µF M2 FDS6680A D1 MBRS340T3 Figure 1. High Efficiency Step-Down Converter U U U VOUT 1.6V 9A R1 20k 1% R2 20k 1% + COUT 180µF 4V ×4 SP 1735 F01 1 LTC1735 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW COSC 1 RUN/SS 2 ITH 3 FCB 4 SGND 5 VOSENSE 6 SENSE – 7 SENSE + 8 GN PACKAGE 16-LEAD NARROW PLASTIC SSOP 16 TG 15 BOOST 14 SW 13 VIN 12 INTVCC 11 BG 10 PGND 9 EXTVCC Input Supply Voltage (VIN).........................36V to – 0.3V Topside Driver Supply Voltage (BOOST)....42V to – 0.3V Switch Voltage (SW) ....................................36V to – 5V EXTVCC Voltage ...........................................7V to – 0.3V Boosted Driver Voltage (BOOST – SW) .......7V to – 0.3V SENSE +, SENSE – Voltages .......... 1.1 (INTVCC) to – 0.3V FCB Voltage ............................(INTVCC + 0.3V) to – 0.3V ITH, VOSENSE Voltages ...............................2.7V to – 0.3V RUN/SS Voltages .........................................7V to – 0.3V Peak Driver Output Current 7.5%) as well as other more serious U (Refer to Functional Diagram) conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Foldback current limiting for an output shorted to ground is provided by amplifier A. As VOSENSE drops below 0.6V, the buffered ITH input to the current comparator is gradually pulled down to a 0.86V clamp. This reduces peak inductor current to about 1/4 of its maximum value. Low Current Operation The LTC1735 has three low current modes controlled by the FCB pin. Burst Mode operation is selected when the FCB pin is above 0.8V (typically tied to INTVCC). In Burst Mode operation, if the error amplifier drives the ITH voltage below 0.86V, the buffered ITH input to the current comparator will be clamped at 0.86V. The inductor current peak is then held at approximately 20mV/RSENSE (about 1/4 of maximum output current). If ITH then drops below 0.5V, the Burst Mode comparator B will turn off both MOSFETs to maximize efficiency. The load current will be supplied solely by the output capacitor until ITH rises above the 60mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by comparator F when the FCB pin is brought below 0.8V. This forces continuous operation and can assist secondary winding regulation. When the FCB pin is driven by an external oscillator, a low noise cycle-skipping mode is invoked and the internal oscillator is synchronized to the external clock by comparator C. In this mode the 25% minimum inductor current clamp is removed, providing constant frequency discontinuous operation over the widest possible output current range. This constant frequency operation is not quite as efficient as Burst Mode operation, but provides a lower noise, constant frequency spectrum. The FCB pin is tied to ground when forced continuous operation is desired. This is the least efficient mode, but is desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels—BEWARE. 9 LTC1735 OPERATIO Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff The RUN/SS capacitor, CSS, is used initially to limit the inrush current of the switching regulator. After the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, CSS is used as a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal output voltage, CSS begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This builtin latchoff can be overridden by providing a current >5µA at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of CSS during an overcurrent and/or short-circuit condition. Foldback current limiting is activated when the APPLICATIO S I FOR ATIO The basic LTC1735 application circuit is shown in Figure 1 on the first page. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, COSC and L can be chosen. Next, the power MOSFETs and D1 are selected. The operating frequency and the inductor are chosen based largely on the desired amount of ripple current. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specifications. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1735 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. 10 U W U U U (Refer to Functional Diagram) output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. INTVCC/EXTVCC POWER Power for the top and bottom MOSFET drivers and most of the internal circuitry of the LTC1735 is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5.2V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC is raised above 4.7V, the internal regulator is turned off and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source, such as the primary or a secondary output of the converter itself, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. To provide clean start-up and to protect the MOSFETs, undervoltage lockout is used to keep both MOSFETs off until the input voltage is above 3.5V. Allowing a margin for variations in the LTC1735 and external component values yields: RSENSE = 50mV IMAX COSC Selection for Operating Frequency and Synchronization The choice of operating frequency and inductor value is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The LTC1735 uses a constant frequency architecture with the frequency determined by an external oscillator capacitor COSC. Each time the topside MOSFET turns on, the voltage on COSC is reset to ground. During the on-time, COSC is charged by a fixed current. When the voltage on the LTC1735 APPLICATIO S I FOR ATIO capacitor reaches 1.19V, COSC is reset to ground. The process then repeats. The value of COSC is calculated from the desired operating frequency assuming no external clock input on the FCB pin:  1.61(107 )   – 11 COSC (pF) =   Frequency    A graph for selecting COSC versus frequency is shown in Figure 2. The maximum recommended switching frequency is 550kHz . The internal oscillator runs at its nominal frequency (fO) when the FCB pin is pulled high to INTVCC or connected to ground. Clocking the FCB pin above and below 0.8V will cause the internal oscillator to injection lock to an external clock signal applied to the FCB pin with a frequency between 0.9fO and 1.3fO. The clock high level must exceed 1.3V for at least 0.3µs and the clock low level must be less than 0.3V for at least 0.3µs. The top MOSFET turn-on will synchronize with the rising edge of the clock. Attempting to synchronize to too high an external frequency (above 1.3fO) can result in inadequate slope compensation and possible loop instability. If this condition exists simply lower the value of COSC so fEXT = fO according to Figure 2. When synchronized to an external clock, Burst Mode operation is disabled but the inductor current is not 100.0 87.5 75.0 COSC VALUE (pF) 62.5 50.0 37.5 25.0 12.5 0 0 100 200 300 400 500 OPERATING FREQUENCY (kHZ) 600 1735 F02 Figure 2. Timing Capacitor Value U allowed to reverse. The 25% minimum inductor current clamp present in Burst Mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. In this mode the synchronous MOSFET is forced on once every 10 clock cycles to recharge the bootstrap capacitor. This minimizes audible noise while maintaining reasonably high efficiency. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL = V  1 VOUT 1 – OUT  VIN  ( f)(L)  W U U Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.3 to 0.4(IMAX). Remember, the maximum ∆IL occurs at the maximum input voltage. The inductor value also has an effect on low current operation. The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on. Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. 11 LTC1735 APPLICATIO S I FOR ATIO Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1735: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.2V during start-up (see EXTVCC pin connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1735 applications. The only exception is when low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. 12 U Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1735 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: V Main Switch Duty Cycle = OUT VIN V –V Synchronous Switch Duty Cycle = IN OUT VIN The MOSFET power dissipations at maximum output current are given by: 2 V PMAIN = OUT IMAX 1 + δ RDS(ON) + VIN W U U ( )( ) k VIN ( ) (IMAX )(CRSS )(f) 2 2 V –V PSYNC = IN OUT IMAX 1 + δ RDS(ON) VIN ( )( ) where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. Kool Mµ is a registered trademark of Magnetics, Inc. LTC1735 APPLICATIO S I FOR ATIO The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 3A Schottky is generally a good size for 10A to 12A regulators due to the relatively small average current. Larger diodes can result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. CIN Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: V  V IRMS ≅ IO(MAX ) OUT  IN – 1 VIN  VOUT  1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. COUT Selection The selection of COUT is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. The output ripple (∆VOUT) in continuous mode is determined by:  1 ∆VOUT ≈ ∆IL  ESR +  8 fCOUT   Where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL U increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P–P) requirement. With ∆IL = 0.3IOUT(MAX) and allowing 2/3 of the ripple due to ESR the output ripple will be less than 50mV at max VIN assuming: COUT required ESR < 2.2 RSENSE COUT > 1/(8fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. The selection of output capacitors for CPU or other applications with large load current transients is primarily determined by the voltage tolerance specifications of the load. The resistive component of the capacitor, ESR, multiplied by the load current change plus any output voltage ripple must be within the voltage tolerance of the load (CPU). The required ESR due to a load current step is: RESR < ∆V/∆I where ∆I is the change in current from full load to zero load (or minimum load) and ∆V is the allowed voltage deviation (not including any droop due to finite capacitance). The amount of capacitance needed is determined by the maximum energy stored in the inductor. The capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. The opposite load current transition is generally determined by the control loop OPTI-LOOP components, so make sure not to over compensate and slow down the response. The minimum capacitance to assure the inductors’ energy is adequately absorbed is: W U U 13 LTC1735 APPLICATIO S I FOR ATIO L( ∆I)2 COUT > 2( ∆V)VOUT where ∆I is the change in load current. Manufacturers such as Nichicon, United Chemicon and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Panasonic SP and Sprague 595D series. Consult manufacturers for other specific recommendations. Like all components, capacitors are not ideal. Each capacitor has its own benefits and limitations. Combinations of different capacitor types have proven to be a very cost effective solution. Remember also to include high frequency decoupling capacitors. They should be placed 14 U as close as possible to the power pins of the load. Any inductance present in the circuit board traces negates their usefulness. INTVCC Regulator An internal P-channel low dropout regulator produces the 5.2V supply that powers the drivers and internal circuitry within the LTC1735. The INTVCC pin can supply a maximum RMS current of 50mA and must be bypassed to ground with a minimum of 4.7µF tantalum, 10µF special polymer or low ESR type electrolytic capacitor. A 1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly recommended. Good bypassing is required to supply the high transient currents required by the MOSFET gate drivers. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1735 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional loading of INTVCC also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 5.2V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC current is supplied by the internal 5.2V linear regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC) and overall efficiency is lowered. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC1735CS is limited to less than 17mA from a 30V supply when not using the EXTVCC pin as follows: TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. W U U LTC1735 APPLICATIO S I FOR ATIO EXTVCC Connection The LTC1735 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. Whenever the EXTVCC pin is above 4.7V the internal 5.2V regulator shuts off, the switch closes and INTVCC power is supplied via EXTVCC until EXTVCC drops below 4.5V. This allows the MOSFET gate drive and control power to be derived from the output or other external source during normal operation. When the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC ≤ VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 5V regulators this simply means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.2V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V output regulator and provides the highest efficiency. For output voltages higher than 5V, EXTVCC is required to connect to VOUT so the SENSE pins’ absolute maximum ratings are not exceeded. 3. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive boost winding as shown in Figure 3a or the capacitive charge pump shown in Figure 3b. The charge pump has the advantage of simple magnetics. 4. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range (EXTVCC ≤ VIN), such as notebook main 5V system power, it may be used to power EXTVCC providing it is compatible with the U MOSFET gate drive requirements. This is the typical case as the 5V power is almost always present and is derived by another high efficiency regulator. OPTIONAL EXTVCC CONNECTION 5V ≤ VSEC ≤ 7V VIN LTC1735 TG N-CH RSENSE VOUT EXTVCC R4 FCB R3 SGND PGND 1735 F03a W U U VIN + CIN 1N4148 VSEC 6.8V + 1µF SW L1 1:N + BG N-CH COUT Figure 3a. Secondary Output Loop and EXTVCC Connection + VIN 1µF + CIN VIN LTC1735 TG N-CH VN2222LL RSENSE VOUT EXTVCC SW L1 BAT85 0.22µF BAT85 BAT85 + BG N-CH COUT PGND 1735 F03b Figure 3b. Capacitive Charge Pump for EXTVCC Output Voltage Programming The output voltage is set by an external resistive divider according to the following formula:  R2  VOUT = 0.8 V 1 +   R1 The resistive divider is connected to the output as shown in Figure 4 allowing remote voltage sensing. 15 LTC1735 APPLICATIO S I FOR ATIO VOUT R2 VOSENSE LTC1735 SGND 1735 F04 47pF R1 Figure 4. Setting the LTC1735 Output Voltage Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. Note that the voltage across CB is about a diode drop below INTVCC. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage SW rises to VIN and the BOOST pin rises to VIN + INTVCC. The value of the boost capacitor CB needs to be 100 times greater than the total input capacitance of the topside MOSFET. In most applications 0.1µF to 0.33µF is adequate. The reverse breakdown on DB must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. SENSE +/SENSE – Pins The common mode input range of the current comparator is from 0V to 1.1(INTVCC). Continuous linear operation in step-down applications is guaranteed throughout this range allowing output voltages anywhere from 0.8V to 7V. A differential NPN input stage is used and is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This causes current to either be sourced or sunk by the sense pins depending on the output voltage. If the output voltage is below 2.4V current will flow out of both sense pins to the main output. This forces a minimum load current that can be fulfilled by the 16 U VOUT resistive divider. The maximum current flowing out of the sense pins is: ISENSE+ + ISENSE– = (2.4V – VOUT)/24k Since VOSENSE is servoed to the 0.8V reference voltage, we can choose R1 in Figure 4 to have a maximum value to absorb this current: W U U   0.8 V R1(MAX ) = 24k    2.4V – VOUT  Regulating an output voltage of 1.8V, the maximum value of R1 should be 32k. Note that at output voltages above 2.4V no maximum value of R1 is necessary to absorb the sense pin currents; however, R1 is still bounded by the VOSENSE feedback current. Soft-Start/Run Function The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC1735. Soft-start reduces surge currents from VIN by gradually increasing the controller’s current limit ITH(MAX). This pin can also be used for power supply sequencing. Pulling the RUN/SS pin below 1.5V puts the LTC1735 into a low quiescent current shutdown (IQ < 25µA). This pin can be driven directly from logic as shown in Figure 5. Releasing the RUN/SS pin allows an internal 1.2µA current source to charge up the external soft-start capacitor CSS. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: tDELAY = 1.5V CSS = (1.25s /µF ) CSS 1.2µA When the voltage on RUN/SS reaches 1.5V the LTC1735 begins operating with a current limit at approximately 25mV/RSENSE. As the voltage on the RUN/SS pin increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.25s/µF to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. LTC1735 APPLICATIO S I FOR ATIO Diode D1 in Figure 5 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. This diode and CSS can be deleted if soft-start is not needed. The RUN/SS pin has an internal 6V zener clamp (See Functional Diagram). 3.3V OR 5V D1 CSS CSS 1735 F05 RUN/SS RUN/SS Figure 5. RUN/SS Pin Interfacing Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to shut off the controller and latch off when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to turn on and limit the inrush current of the controller. After the controller has been started and given adequate time to charge up the output capacitor and provide full load current, CSS is used as a short-circuit timer. If the output voltage falls to less than 70% of it’s nominal output voltage after CSS reaches 4.1V, the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and CSS begins discharging. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing a current >5µA at a compliance of 5V to the RUN/SS pin as shown in Figure 6. This current shortens the soft-start period but also prevents net discharge of the RUN/SS VIN 3.3V OR 5V D1 RSS RUN/SS RSS D1 CSS CSS RUN/SS INTVCC (a) (b) Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated U capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5µA current from VIN as in Figure 6a, current latchoff is always defeated. Diode connecting this pull-up resistor to INTVCC , as in Figure 6b, eliminates any extra supply current during controller shutdown while eliminating the INTVCC loading from preventing controller start-up. If the voltage on CSS does not exceed 4.1V the overcurrent latch is not armed and the function is disabled. Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. Defeating this feature will easily allow troubleshooting of the circuit and PC layout. The internal shortcircuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. After the design is complete, a decision can be made whether to enable the latchoff feature. The value of the soft-start capacitor CSS will need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT)(10 – 4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. Fault Conditions: Current Limit and Current Foldback The LTC1735 current comparator has a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. The LTC1735 includes current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is defeated. If the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mV to 30mV. Under short-circuit conditions with very low duty cycle, the LTC1735 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be conducting the peak current. The short-circuit ripple current is determined by the minimum on-time 1735 F06 W U U 17 LTC1735 APPLICATIO S I FOR ATIO ∆IL(SC) = tON(MIN)VIN/L The resulting short-circuit current is: ISC = 30mV 1 + ∆IL(SC) RSENSE 2 tON(MIN) of the LTC1735 (approximately 200ns), the input voltage and inductor value: The current foldback function is always active and is not effected by the current latchoff function. Fault Conditions: Output Overvoltage Protection (Crowbar) The output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. This condition causes huge currents to flow, much greater than in normal operation. This feature is designed to protect against a shorted top MOSFET; it does not protect against a failure of the controller itself. The comparator (OV in the Functional Diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed the top MOSFET is turned off and the bottom MOSFET is forced on. The bottom MOSFET remains on continuously for as long as the 0V condition persists; if VOUT returns to a safe level, normal operation automatically resumes. Note that dynamically changing the output voltage may cause overvoltage protection to be momentarily activated during programmed output voltage decreases. This will not cause permanent latchoff nor will it disrupt the desired voltage change. With soft-latch overvoltage protection, dynamically changing the output voltage is allowed and the overvoltage protection tracks the newly programmed output voltage, always protecting the load. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest amount of time that the LTC1735 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and MINIMUM ON-TIME (ns) 18 U the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit and care should be taken to ensure that: V t ON(MIN) < OUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1735 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and voltage will increase. The minimum on-time for the LTC1735 in a properly configured application is generally less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases as shown in Figure 7. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule keep the inductor ripple current equal or greater than 30% of IOUT(MAX) at VIN(MAX). 250 200 150 100 50 0 0 10 20 ∆IL /IOUT(MAX) (%) 1735 F07 W U U 30 40 Figure 7. Minimum On-Time vs ∆IL LTC1735 APPLICATIO S I FOR ATIO FCB Pin Operation When the FCB pin drops below its 0.8V threshold, continuous mode operation is forced. In this case, the top and bottom MOSFETs continue to be driven synchronously regardless of the load on the main output. Burst Mode operation is disabled and current reversal is allowed in the inductor. In addition to providing a logic input to force continuous synchronous operation and external synchronization, the FCB pin provides a means to regulate a flyback winding output. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom, synchronous switch is on. When primary load currents are low and/or the VIN/ VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in Figure 3a by the turns ratio N of the transformer: VSEC ≅ (N + 1)VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN):  R4  VSEC(MIN) ≈ 0.8 V 1 +   R3  If VSEC drops below this level, the FCB voltage forces continuous switching operation until VSEC is again above its minimum. In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.17µA U internal current source pulling the pin high. Remember to include this current when choosing resistor values R3 and R4. The internal LTC1735 oscillator can be synchronized to an external oscillator by applying and clocking the FCB pin with a signal above 1.5VP–P. When synchronized to an external frequency, Burst Mode operation is disabled but cycle skipping is allowed at low load currents since current reversal is inhibited. The bottom gate will come on every 10 clock cycles to assure the bootstrap cap is kept refreshed. The rising edge of an external clock applied to the FCB pin starts a new cycle. The range of synchronization is from 0.9fO to 1.3fO, with fO set by COSC. Attempting to synchronize to a higher frequency than 1.3fO can result in inadequate slope compensation and cause loop instability with high duty cycles (duty cycle > 50%). If loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing COSC. The following table summarizes the possible states available on the FCB pin: Table 1 FCB Pin DC Voltage: 0V to 0.7V DC Voltage: ≥ 0.9V Feedback Resistors Ext Clock: (0V to VFCBSYNC) (VFCBSYNC > 1.5V) Condition Burst Disabled/Forced Continuous Current Reversal Enabled Burst Mode Operation, No Current Reversal Regulating a Secondary Winding Burst Mode Operation Disabled No Current Reversal W U U Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, etc. are the individual losses as a percentage of input power. 19 LTC1735 APPLICATIO S I FOR ATIO Although all dissipative elements in the circuit produce losses, 4 main sources usually account for most of the losses in LTC1735 circuits: 1) LTC1735 VIN current, 2) INTVCC current, 3) I2R losses, 4) Topside MOSFET transition losses. 1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Improve Transient Response and Reduce Output Capacitance with Active Voltage Positioning Fast load transient response, limited board space and low cost are requirements of microprocessor power supplies. U Active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor where a typical load step can be from 0.2A to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the microprocessor must be held to about ±0.1V of nominal in spite of these load current steps. Since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. Capacitor ESR and ESL primarily determine the amount of droop or overshoot in the output voltage. Normally, several capacitors in parallel are required to meet microprocessor transient requirements. Active voltage positioning is a form of deregulation. It sets the output voltage high for light loads and low for heavy loads. When load current suddenly increases, the output voltage starts from a level higher than nominal so the output voltage can droop more and stay within the specified voltage range. When load current suddenly decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. Less output capacitance is required when voltage positioning is used because more voltage variation is allowed on the output capacitors. Active voltage positioning can be implemented using the OPTI-LOOP architecture of the LTC1735 and two resistors connected to the ITH pin. An input voltage offset is introduced when the error amplifier has to drive a resistive load. This offset is limited to ± 30mV at the input of the error amplifier. The resulting change in output voltage is the product of input offset and the feedback voltage divider ratio. Figure 8 shows a CPU-core-voltage regulator with active voltage positioning. Resistors R1 and R4 force the input voltage offset that adjusts the output voltage according to the load current level. To select values for R1 and R4, first determine the amount of output deregulation allowed. The actual specification for a typical microprocessor allows the output to vary ± 0.112V. The LTC1735 reference accuracy is ±1%. Using 1% tolerance resistors, the total feedback divider accuracy is about 1% because both feedback resistors are close to the same value. The resulting setpoint accuracy is ± 2% so the output transient W U U 21 LTC1735 APPLICATIO S I FOR ATIO R3 680k R1 27k C1 39pF 1 C2 0.1µF 2 R2 100k C4 100pF 4 C3 100pF 3 COSC TG 16 R4 100k RUN/SS BOOST 15 C8 0.22µF ITH U1 LTC1735 FCB SW 14 VIN 13 D1 CMDSH-3 D2 MBRS340 M2, M3 FDS6680A ×2 5 C5 47pF 6 SGND INTVCC 12 VOSENSE SENSE – SENSE + BG 11 C9 1µF 7 C6 1000pF PGND 10 8 EXTVCC 9 5V (OPTIONAL) Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning voltage cannot exceed ± 0.082V. At VOUT = 1.5V, the maximum output voltage change controlled by the ITH pin would be: ∆VOSENSE = Input Offset • VOUT VREF ± 0.03V • 1.5 = = ±56mV 0.8 V With the optimum resistor values at the ITH pin, the output voltage will swing from 1.55V at minimum load to 1.44V at full load. At this output voltage, active voltage positioning provides an additional ± 56mV to the allowable transient voltage on the output capacitors, a 68% improvement over the ± 82mV allowed without active voltage positioning. The next step is to calculate the ITH pin voltage, VITH, scale factor. The VITH scale factor reflects the ITH pin voltage 22 U C7 0.1µF C9, C19: TAIYO YUDEN JMK107BJ105 C10: KEMET T494A475M010AS C12 TO C14: TAIYO YUDEN GMK325F106 C15 TO C18: PANASONIC EEFUE0G181R D1: CENTRAL SEMI CMDSH-3 D2: MOTOROLA MBRS340 L1: PANASONIC ETQP6F1R0SA M1 TO M3: FAIRCHILD FDS6680A R5: IRC LRF2512-01-R003-J U1: LINEAR TECHNOLOGY LTC1735CS L1 1µH R5 0.003Ω C11 330pF R6 10k C19 1µF C12 TO C14 10µF 35V VIN 7.5V TO 24V GND M1 FDS6680A VOUT 1.5V 15A W U U + C10 4.7µF 10V + R7 11.5k C15 TO C18 180µF 4V GND 1735 F08 required for a given load current. VITH controls the peak sense resistor voltage, which represents the DC output current plus one half of the peak-to-peak inductor current. The no load to full load VITH range is from 0.3V to 2.4V, which controls the sense resistor voltage from 0V to the ∆VSENSE(MAX) voltage of 75mV. The calculated VITH scale factor with a 0.003Ω sense resistor is: VITH Scale Factor = = VITH Range • Sense Re sistor Value ∆VSENSE(MAX) (2.4V – 0.3V) • 0.003 = 0.084V/A 0.075V VITH at any load current is:   ∆I  VITH = IOUTDC + L  • VITH Scale Factor  2   + VITH Offset LTC1735 APPLICATIO S I FOR ATIO At full load current:    5A VITH(MAX) =  15A + P−P  • 0.084V/A  + 0.3V 2     = 1.77 V At minimum load current:    2A VITH(MIN) =  0.2A + P−P  • 0.084V/A  + 0.3V 2     = 0.40 V In this circuit, VITH changes from 0.40V at light load to 1.77V at full load, a 1.37V change. Notice that ∆IL, the peak-to-peak inductor current, changes from light load to full load. Increasing the DC inductor current decreases the permeability of the inductor core material, which decreases the inductance and increases ∆IL. The amount of inductance change is a function of the inductor design. To create the ± 30mV input offset, the gain of the error amplifier must be limited. The desired gain is: AV = ∆VITH 1.37 V = = 22.8 Input Offset Error 2(0.03V) Connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. The value of this resistor is: RITH = AV 22.8 = = 17.54k Error Amplifier gm 1.3ms To center the output voltage variation, VITH must be centered so that no ITH pin current flows when the output voltage is nominal. VITH(NOM) is the average voltage between VITH at maximum output current and minimum output current: VITH(NOM) = VITH(MAX) – VITH(MIN) + VITH(MIN) 2 1.77 V – 0.40 V = + 0.40 V = 1.085V 2 U The Thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor R4 that sources current into the ITH pin and resistor R1 that sinks current to SGND. To calculate the resistor values, first determine the ratio between them: W U U k= VINTVCC – VITH(NOM) 5.2V – 1.085V = = 3.79 1.085V VITH(NOM) VINTVCC is equal to VEXTVCC or 5.2V if EXTVCC is not used. Resistor R4 is: R4 = (k + 1) • RITH = (3.79 + 1) • 17.54 = 84.0k Resistor R1 is: R1 = (k + 1) • RITH (3.79 + 1) • 17.54k = = 22.17k k 3.79 Unfortunately, PCB noise can add to the voltage developed across the sense resistor, R5, causing the ITH pin voltage to be slightly higher than calculated for a given output current. The amount of noise is proportional to the output current level. This PCB noise does not present a serious problem but it does change the effective value of R5 so the calculated values of R1 and R4 may need to be adjusted to achieve the required results. Since PCB noise is a function of the layout, it will be the same on all boards with the same layout. Figures 9 and 10 show the transient response before and after active voltage positioning is implemented. Notice that active voltage positioning reduced the transient response from almost 200mVP-P to a little over 100mVP-P. Refer to Design Solutions 10 for more information about active voltage positioning. 23 LTC1735 APPLICATIO S I FOR ATIO VIN = 12V VOUT = 1.5V 1.5V 100mV/DIV OUTPUT VOLTAGE FIGURE 8 CIRCUIT 15A 10A/DIV 0A 50µs/DIV LOAD CURRENT 1735 F09 Figure 9. Normal Transient Response (Without R1, R4) VIN = 12V VOUT = 1.5V 1.582V 100mV/DIV 1.5V 1.418V OUTPUT VOLTAGE FIGURE 8 CIRCUIT 15A 10A/DIV 0A 50µs/DIV LOAD CURRENT 1735 F10 Figure 10. Transient Response with Active Voltage Positioning Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery and double-battery. Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. 24 U The network shown in Figure 11 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC1735 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V W U U VIN LTC1735 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 1735 F11 Figure 11. Plugging into the Cigarette Lighter Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A and f = 300kHz. RSENSE and COSC can immediately be calculated: RSENSE = 50mV/5A = 0.01Ω COSC = 1.61(107)/(300kHz) – 11pF = 43pF Assume a 3.3µH inductor and check the actual value of the ripple current. The following equation is used: V  V ∆IL = OUT  1 – OUT  ( f)(L)  VIN  The highest value of the ripple current occurs at the maximum input voltage: ∆IL =  1.8 V  1.8 V  1–  = 2.3A 300kHz(3.3µH)  22V  The maximum ripple current is 33% of maximum output current, which is about right. LTC1735 APPLICATIO S I FOR ATIO Next verify the minimum on-time of 200ns is not violated. The minimum on-time occurs at maximum VIN: tON(MIN) = VOUT VIN(MAX )f = 1.8 V = 273ns 22V(300kHz) Since the output voltage is below 2.4V the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pin current.   0.8 V R1(MAX ) = 24k    2.4V – VOUT   0.8 V  = 24K  = 32k  2.4V – 1.8 V  Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. The power dissipation on the topside MOSFET can be easily estimated. Choosing a Siliconix Si4412DY results in RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input voltage with T(estimated) = 50°C: PMAIN = = 220mW ()[ ]( 2 +1.7(22V ) (5A )(100pF )(300kHz) 1.8 V 2 5 1 + (0.005)(50°C – 25°C) 0.042Ω 22V Because the duty cycle of the bottom MOSFET is much greater than the top, a larger MOSFET, Siliconix Si4410DY, (RDS(ON) = 0.02Ω) is chosen. The power dissipation in the bottom MOSFET, again assuming TA = 50°C, is: PSYNC = 2 22V – 1.8 V 5A 1.1 0.02Ω 22V = 500mW ( ) ( )( ) Thanks to current foldback, the bottom MOSFET dissipation in short-circuit will be less than under full load conditions. U CIN is chosen for an RMS current rating of at least 2.5A at temperature. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The worst-case output voltage ripple due to ESR is approximately: VORIPPLE = RESR( ∆IL ) = 0.02Ω(2.3A) = 46mVP −P PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1735. These items are also illustrated graphically in the layout diagram of Figure 12. Check the following in your layout: 1) Are the signal and power grounds segregated? The LTC1735 PGND pin should tie to the ground plane close to the input capacitor(s). The SGND pin should then connect to PGND and all components that connect to SGND should make a single point tie to the SGND pin. The synchronous MOSFET source pins should connect to the input capacitor(s) ground. 2) Does the VOSENSE pin connect directly to the feedback resistors? The resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. The 47pF to 100pF capacitor should be as close as possible to the LTC1735. Be careful locating the feedback resistors too far away from the LTC1735. The VOSENSE line should not be routed close to any other nodes with high slew rates. 3) Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE – should be as close as possible to the LTC1735. Ensure accurate current sensing with Kelvin connections as shown in Figure 13. Series resistance can be added to the SENSE lines to increase noise rejection. 4) Does the (+) terminal of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). 5) Is the INTVCC decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. An additional 1µF ceramic capacitor placed immediately next to W U U ) 25 LTC1735 APPLICATIO S I FOR ATIO the INTVCC and PGND pins can help improve noise performance. 6) Keep the switching node (SW), top gate node (TG) and boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing COSC 1 CSS 2 RC CC2 4 FCB CC 3 ITH LTC1735 VIN 13 DB SW 14 COSC TG 16 + RUN/SS BOOST 5 47pF 6 SGND INTVCC VOSENSE SENSE – SENSE + 7 1000pF 8 PGND EXTVCC R2 Figure 12. LTC1735 Layout Diagram HIGH CURRENT PATH SENSE + SENSE – Figure 13. Kelvin Sensing RSENSE 26 + U feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” (Pin 9 to Pin 16) of the LTC1735 and occupy minimum PC trace area. + M1 15 CIN VIN CB D1 12 BG 11 W U U + 4.7µF M2 10 – 9 L1 – R1 COUT RSENSE + 1735 F12 VOUT 1735 F13 CURRENT SENSE RESISTOR (RSENSE) LTC1735 TYPICAL APPLICATIO S 1.8V/5A Converter from Design Example with Burst Mode Operation Disabled VIN 4.5V TO 22V COSC 43pF 1 CSS 0.1µF 2 RC 33k CC2 220pF 4 CC 470pF 3 COSC TG 16 CB 0.1µF 15 M1 Si4412DY CIN 22µF 50V CER RUN/SS ITH LTC1735 FCB 5 47pF 6 SGND VOSENSE SENSE – SENSE + 7 1000pF 8 CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V) VIN 5V 100k* COSC 39pF 1 CSS 0.1µF 2 RC 20k CC2 220pF 4 CC 220pF 3 CIN 150µF 6.3V ×2 COSC RUN/SS ITH LTC1735 FCB 5 47pF 6 SGND VOSENSE SENSE – SENSE + 7 1000pF 8 *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF U BOOST SW 14 L1 3.3µH RSENSE 0.01Ω R2 32.4k 1% M2 Si4410DY MBRS140T3 R1 25.5k 1% SGND VIN 13 DB CMDSH-3 VOUT 1.8V 5A INTVCC 12 + 11 4.7µF + BG COUT 150µF 6.3V ×2 PANASONIC SP PGND 10 EXTVCC 9 OPTIONAL: CONNECT TO 5V COUT: PANASONIC EEFUEOG151R CIN: MARCON THCR70LE1H226ZT L1: PANASONIC ETQP6F3R3HFA RSENSE: IRC LR 2010-01-R010F 1735 TA02 TG 16 CB 0.22µF 15 M1 FDS6680A BOOST SW 14 L1 0.78µH RSENSE 0.004Ω R2 32.4k 1% R1 25.5k 1% SGND VIN 13 DB MBR0530 VOUT 1.5V 12A INTVCC 12 + 11 1µF 100pF 4.7µF M2, M3 FDS6680A ×2 MBRD835L + BG COUT 180µF 4V ×3 CO 47µF 10V PGND 10 EXTVCC 9 VIN COUT: PANASONIC EEFUEOG181R CIN: PANASONIC EEFUEOJ151R CO: TAIYO YUDEN LMK550BJ476MM-B L1: COILCRAFT 1705022P-781HC RSENSE: IRC LRF 2512-01-R004-J 1735 TA03 27 LTC1735 TYPICAL APPLICATIO S Selectable Output Voltage Converter with Burst Mode Operation Disabled for CPU Power VIN 4.5V TO 24V 0.1µF COSC 43pF 1 CSS 0.1µF 2 CC RC 330pF 33k CC2 47pF 4 COSC TG 16 CB 0.22µF 15 M1 FDS6680A RUN/SS 3 ITH LTC1735 FCB 5 47pF 6 SGND VOSENSE SENSE – + 7 1000pF 8 10Ω 10Ω SENSE CMDSH-3 VOUT FMMT625 10k 6.2V COSC 150pF 1 CSS 0.1µF 2 CC 2200pF RC 3.3k CC2 100pF 4 1M 16 CIN 22µF 50V ×2 • COSC TG RUN/SS BOOST 15 3 ITH LTC1735 FCB SW 14 VIN 13 5 47pF 6 SGND INTVCC 12 VOSENSE SENSE – SENSE + BG 11 7 3300pF 8 100Ω PGND 10 CIN: MARCON THCR70EIH226ZT COUT: AVX TPSV227M016R0150 T1: COILTRONICS VP5-0155 RSENSE: IRC LRF2512-01-R004F 1735 TA07 EXTVCC 9 28 U 4.7Ω + CIN 22µF ×2 CER CIN: MARCON THCR70EIH226ZT COUT: KEMET T510X447M006AS L1: PANASONIC ETQP6F1R2HFA RSENSE: IRC LRF2512-01-R004F BOOST SW 14 L1 1.2µH RSENSE 0.004Ω VIN 13 DB CMDSH-3 INTVCC 12 47pF + 11 1µF CER 4.7µF M2 FDS6680A ×2 MBRS340T3 R3 33.2k 1% VN2222 47pF R2 10k 1% VOUT 1.35V/1.60V 12A + BG R1 14.3k 1% COUT 470µF 6.3V ×3 KEMET PGND 10 EXTVCC 9 OPTIONAL: CONNECT TO 5V 10k ON: VOUT = 1.60V OFF: VOUT = 1.35V SGND 1735 TA05 4V to 40V Input to 12V Flyback Converter VIN 4V TO 40V VOUT 12V 3A T1 10 3 6 7 47Ω MBRS1100 1nF 100V R2 113k 1% R1 8.06k 1% + M1 IR2910 22Ω M2 Si4450DY COUT 470µF 16V ×4 • RSENSE 0.004Ω 1nF 100V + 0.1µF 4.7µF LTC1735 TYPICAL APPLICATIO S 5V/3.5A Converter with 12V/200mA Auxiliary Output VIN 5.5V TO 28V COSC 51pF 1 CSS 0.1µF 2 RC 33k CC2 220pF 4 CC 470pF 3 COSC TG 16 CB 0.1µF 15 MBRS1100T3 14 M1 IRF7803 RUN/SS ITH LTC1735 FCB 5 100pF 6 SGND VOSENSE SENSE – + 7 1000pF 8 SENSE 100Ω 10k 90.9k 1735 TA04 COSC 47pF 1 CSS 0.1µF 2 CC 470pF 3 RC 33k CC2 100pF 100pF 6 VOSENSE SENSE – SENSE + BG 11 COSC TG 16 CB 0.1µF M1 Si4412DY RUN/SS BOOST ITH LTC1735 SW 4 FCB VIN 5 SGND INTVCC 7 1000pF 8 PGND EXTVCC U + CIN 22µF 30V OS-CON 22Ω 1000pF BOOST SW + 13 DB CMDSH-3 T1 1:1.8 10µH 4.7µF M2 IRF7803 MBRS140T3 RSENSE 0.012Ω VIN CSEC 22µF 35V AVX R2 105k 1% R1 20k 1% SGND INTVCC 12 VOUT 5V 3.5A + 11 + BG COUT 100µF 10V ×3 AVX PGND 10 EXTVCC 9 CIN: SANYO OS-CON 305C22M COUT: AVX TPSD107M010R0068 T1: 1:8 DALE LPE6562-A262 VOUT2 12V 120mA UNREG 100Ω Dual Output 15W 3.3V/5V Power Supply VIN 4.5V TO 28V + CIN 22µF 50V • 0.01µF 3 T1C 6 COUT2 100µF 10V ×2 15 M3 Si4412DY CMDSH-3 4.7k MBRS140T3 + VOUT2 5V 1.5A 14 RSENSE 0.01Ω 7 R2 62.6k 1% R1 20k 1% 13 DB CMDSH-3 • 1 T1A • 82 T1B 12 VOUT1 3.3V 2.5A + 4.7µF M2 Si4412DY MBRS140T3 + COUT1 100µF 10V ×2 10 SGND VOUT2 CIN: MARCON THCR70EIH226ZT COUT1, 2: AVX TPSD107M010R0065 T1: BI TECHNOLOGIES HM00-93839 RSENSE: IRC LRF2512-01-R010 F 9 1735 TA08 29 LTC1735 PACKAGE DESCRIPTION 0.007 – 0.0098 (0.178 – 0.249) 0.016 – 0.050 (0.406 – 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 30 U Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0° – 8° TYP 0.053 – 0.068 (1.351 – 1.727) 23 4 56 7 8 0.004 – 0.0098 (0.102 – 0.249) 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC GN16 (SSOP) 1098 LTC1735 PACKAGE DESCRIPTION 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.053 – 0.069 (1.346 – 1.752) 2 3 4 5 6 7 8 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP 0.050 (1.270) BSC S16 1098 31 LTC1735 TYPICAL APPLICATIO 3.3V to 2.5V/5A Converter with External Clock Synchronization Operating at 500kHz 5V 0.1µF COSC 20pF 1 CSS 0.1µF 2 CC 330pF 3 RC 33k CC2 51pF 47pF 6 VOSENSE SENSE – SENSE + BG 11 EXT CLOCK 500kHz COSC TG 16 CB 0.1µF 15 M1 Si4410DY VIN 3.3V RUN/SS ITH LTC1735 4 FCB 5 SGND 7 1000pF 8 RELATED PARTS PART NUMBER LTC1147 LTC1148HV/LTC1148 LTC1149 LTC1159 LTC1266 LT1375/LT1376 LTC1435A LTC1436/LTC1436-PLL LTC1474/LTC1475 LTC1624 LTC1625/LTC1775 LTC1627 LTC1628 LTC1702 LTC1735-1 LTC1736 LTC1772 DESCRIPTION High Efficiency Step-Down Controller High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller, N-Ch Drive 1.5A 500kHz Step-Down Switching Regulator High Efficiency Synchronous Step-Down Controller, N-Ch Drive High Efficiency Low Noise Synchronous Step-Down Converter, N-Ch Drive Ultralow Quiescent Current Step-Down Monolithic Switching Regulator High Efficiency SO-8 N-Channel Switching Regulator Controller No RSENSETM Current Mode Synchronous Step-Down Controller Synchronous Monolithic 0.5A Step-Down Regulator Dual High Efficiency 2-Phase Step-Down Controller 550kHz Dual Output Synchronous Step-Down Controller High Efficiency Step-Down Controller with Power Good High Efficiency Step-Down Controller with VID Control SOT-23 Step-Down Controller COMMENTS 100% DC*, Burst Mode Operation, SO-8 100% DC*, Burst Mode Operation, VIN < 20V 100% DC*, Std Threshold MOSFETs, VIN < 48V 100% DC*, Logic Level MOSFETs, VIN < 40V 100% DC*, Burst Mode Operation, VIN < 20V High Efficiency, Monolithic, SO-8 Burst Mode Operation, 16-Pin Narrow SO Adaptive Power Mode, 24-Pin SSOP 100% DC*, 8-Pin MSOP, 10µA IQ 95% DC*, 3.5V to 36V VIN Burst Mode Operation, 16-Pin SSOP 100% DC*, 2.6V to 8.5V VIN, SO-8 Antiphase Drive for Reduced Input Capacitance Antiphase Drive, 24-Pin SSOP Output Fault Protection, 16-Pin SO/SSOP Output Fault Protection, 24-Pin SSOP 100% DC*, Up to 4A, 2.2V to 9.8V VIN No RSENSE is trademark of Linear Technology Corporation. *DC = Duty Cycle 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U + CIN 100µF 10V OS-CON CIN: SANYO OS-CON 10SL100M COUT: AVX TPSD107M010R0065 L1: COILCRAFT DO3316P-152 RSENSE: IRC LR2010-01-R010-F DB CMDSH-3 L1 1.5µH RSENSE 0.01Ω 47pF R2 43.2k 1% R1 20k 1% SGND EXTVCC 9 BOOST SW 14 VIN 13 INTVCC 12 VOUT 2.5V 5A + 4.7µF M2 Si4410DY MBRS140T3 + COUT 100µF 10V AVX ×3 PGND 10 1735 TA06 1735f LT/TP 1199 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1998