LTC1740CG

LTC1740 14-Bit, 6Msps, Sampling ADC FEATURES s s s s s s s s s s s s DESCRIPTIO 6Msps Sample Rate 79dB S/(N + D) and 91dB SFDR at 2.5MHz fIN Single 5V Supply or ± 5V Supplies Integral Nonlinearity Error: < 1LSB Differential Nonlinearity: < 0.5LSB 80MHz Full-Power Bandwidth Sampling ± 2.5V and ± 1.25V Bipolar Input Ranges 2.5V Signal Ground Available Out-of-Range Indicator True Differential Inputs with 75dB CMRR Power Dissipation: 245mW 36-Pin SSOP Package (0.209 Inch Width) The LTC®1740 is a 6Msps, 14-bit sampling A/D converter that draws only 245mW from either a single 5V or dual ± 5V supplies. This easy-to-use device includes a high dynamic range sample-and-hold and a programmable precision reference. The LTC1740 has a flexible input circuit that allows differential full-scale input ranges of ± 2.5V and ± 1.25V with the internal reference, or any full-scale input range up to ±2.5V with an external reference. The input common mode voltage is arbitrary, though a 2.5V reference is provided for single supply applications. DC specifications include 1LSB typical INL, 0.5LSB typical DNL and no missing codes over temperature. Outstanding AC performance includes 79dB S/(N + D) and 91dB SFDR at an input frequency of 2.5MHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 80MHz bandwidth. The 75dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. A separate output logic supply allows direct connection to 3V components. APPLICATIO S s s s s s Telecommunications Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectral Analysis Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. BLOCK DIAGRA 5V 1µF 8 5V 1µF VDD 9 3V TO 5V 1µF + VIN 1000pF 1 + AIN VDD 32 VDD 33 VDD 19 OVDD OF 36 12 – 1µF 2 3 –AIN VCM S/H PIPELINED 14-BIT ADC D13 (MSB) –20 AMPLITUDE (dB) –40 –60 –80 D7 MODE SELECT DIGITAL CORRECTION LOGIC OUTPUT BUFFERS D6 18 20 DIGITAL OUTPUT 4 SENSE 2.5V REFERENCE D0 (LSB) 26 5 VREF 2.250V BUSY CLK 1µF 27 35 6MHz CLK 30 VSS 29 VSS 6 GND 7 GND 10 GND 34 GND 31 GND 11 OGND 28 OGND 1740 TA01 1µF 0V OR –5V U 4096-Point FFT 0 fSMPL = 6MHz fIN = 2.5MHz, 5VP-P 5V SUPPLY –100 –120 0 0.5 1.0 1.5 2.0 FREQUENCY (MHz) 2.5 3.0 1740 TA02 W U 1740f 1 LTC1740 ABSOLUTE MAXIMUM RATINGS 0VDD = VDD (Notes 1, 2) PACKAGE/ORDER INFORMATION TOP VIEW +AIN –AIN VCM SENSE VREF GND GND VDD VDD 1 2 3 4 5 6 7 8 9 36 OF 35 CLK 34 GND 33 VDD 32 VDD 31 GND 30 VSS 29 VSS 28 OGND 27 BUSY 26 D0 25 D1 24 D2 23 D3 22 D4 21 D5 20 D6 19 OVDD Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ................................ – 6V Total Supply Voltage (VDD to VSS) ........................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1740C ............................................... 0°C to 70°C LTC1740I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1740CG LTC1740IG GND 10 OGND 11 D13 (MSB) 12 D12 13 D11 14 D10 15 D9 16 D8 17 D7 18 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS The q denotes specifications which apply over the full operating PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco IOUT(REF) = 0 (Note 7) q temperature range, otherwise specifications are at TA = 25°C. With internal 4.500V reference. Specifications are guaranteed for both dual supply and single supply operation. (Notes 4, 5) CONDITIONS q MIN 14 TYP 1 MAX ± 2.5 1.25 ± 60 ± 80 ± 75 UNITS Bits LSB LSB LSB LSB LSB ppm/°C (Note 6) q –1 0.5 ± 15 ± 30 ±15 2 U W U U WW W U 1740f LTC1740 A ALOG I PUT SYMBOL VIN PARAMETER Analog Input Range The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) CONDITIONS VREF = 4.5V (SENSE = 0V) VREF = 2.25V (SENSE Tied to VREF) External VREF (SENSE = 5V) Between Conversions During Conversions q q q q IIN CIN tACQ tAP tjitter CMRR Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio VSS < (–AIN = + AIN) < VDD DY A IC ACCURACY SYMBOL S/(N + D) THD SFDR PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious Free Dynamic Range Full-Power Bandwidth Input Referred Noise I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance VREF Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.1mA ≤ IOUT ≤ 0.1mA SENSE = GND, IOUT = 0 SENSE = VREF, IOUT = 0 SENSE = VDD TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) MIN 2.475 TYP 2.500 ±15 0.6 0.03 8 4.500 2.250 Drive VREF with External Reference ±15 MAX 2.525 UNITS V ppm/°C mV/V mV/V Ω V V V ppm/°C VREF Output Tempco U U WU U U MIN TYP ± 2.50 ±1.25 ± VREF/1.8 MAX UNITS V V V ±10 12 4 67 – 900 0.6 75 µA pF pF ns ps psRMS dB VDD = OVDD = 5V, VSS = 0V, VREF = 4.5V, AIN = – 0.1dBFS, AC coupled differential input. CONDITIONS 1MHz Input Signal 2.5MHz Input Signal 1MHz Input Signal, First 5 Harmonics 2.5MHz Input Signal, First 5 Harmonics 1MHz Input Signal 2.5MHz Input Signal MIN TYP 79.1 79.0 – 90 – 89 92 91 80 0.45 MAX UNITS dB dB dB dB dB dB MHz LSBRMS U 1740f 3 LTC1740 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage 0VDD = 4.75V, IO = –10µA 0VDD = 4.75V, IO = –200µA 0VDD = 2.7V, IO = –10µA 0VDD = 2.7V, IO = –200µA 0VDD = 4.75V, IO = 160µA 0VDD = 4.75V, IO = 1.6mA 0VDD = 2.7V, IO = 160µA 0VDD = 2.7V, IO = 1.6mA VOUT = 0V, 0VDD = 5V VOUT = VDD, 0VDD = 5V q q q q The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) CONDITIONS VDD = 5.25V, VSS = 0V VDD = 5.25V, VSS = – 5V VDD = 4.75V, VSS = 0V VDD = 4.75V, VSS = – 5V VIN = 0V to VDD q q q q q VOL Low Level Output Voltage ISOURCE ISINK Output Source Current Output Sink Current POWER REQUIRE E TS SYMBOL VDD OVDD VSS IDD ISS PD PARAMETER Positive Supply Voltage Output Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) CONDITIONS (Note 9) (Note 9) Dual Supply Mode Single Supply Mode q q q TI I G CHARACTERISTICS SYMBOL fSAMPLE tCONV tACQ tH tL tAP t1 t2 PARAMETER Sampling Frequency Conversion Time Acquisition Time CLK High Time CLK Low Time Aperature Delay of Sample-and-Hold CLK↑ to BUSY↓ BUSY↑ to Outputs Valid Data Latency The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4) CONDITIONS q q 4 UW U U MIN 2.4 2.4 TYP MAX UNITS V V 0.8 0.8 ±10 1.8 4.0 2.3 0.05 0.10 0.05 0.10 50 35 0.4 0.4 4.74 4.71 2.6 V V µA pF V V V V V V V V mA mA MIN 4.75 2.7 – 5.25 TYP MAX 5.25 VDD – 4.75 UNITS V V V V mA mA mW 0 47 2.3 245 60 2.6 300 UW MIN 0.05 TYP 100 MAX 6 135 UNITS MHz ns ns ns ns ps ns ns Cycles 1740f (Note 9) (Note 9) (Note 9) q q q 31 20 20 67 83.3 83.3 – 900 3.5 1.5 3 LTC1740 TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: VDD = 5V, VSS = – 5V or 0V, fSAMPLE = 6MHz, tr = tf = 5ns unless otherwise specified. Note 5: Linearity, offset and full-scale specifications apply for a single-ended +AIN input with – AIN tied to VCM for single supply and 0V for dual supply. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar offset is the offset voltage measured from –0.5LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. TYPICAL PERFOR A CE CHARACTERISTICS Typical INL at 6Msps 2.0 1.5 1.0 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 CODE 1740 G01 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 S/(N + D) (dBc) 12288 S/(N + D) vs Input Frequency and Amplitude 80 VIN = 0dBFS 75 VIN = – 6dBFS AMPLITUDE (dB) 75 70 65 60 55 DUAL SUPPLIES 5V INPUT RANGE AIN = 0dBFS DIFFERENTIAL INPUT 6Msps 0.1 1 10 INPUT FREQUENCY (MHz) 100 1740 G05 AMPLITUDE (dB) S/(N + D) (dBc) 70 65 VIN = –20dBFS 60 55 50 SINGLE SUPPLY 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps 0.1 1 10 INPUT FREQUENCY (MHz) 100 1740 G04 UW UW Typical DNL at 6Msps 1.0 0.8 0.6 0.4 75 80 S/(N + D) vs Input Frequency and Amplitude VIN = 0dBFS VIN = – 6dBFS 70 65 60 55 50 VIN = –20dBFS DUAL SUPPLIES 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps 0.1 1 10 INPUT FREQUENCY (MHz) 100 1740 G03 16384 0 4096 8192 CODE 12288 16384 1740 G02 SFDR and THD vs Input Frequency 95 90 SFDR 85 –THD 80 80 75 70 65 60 55 50 85 95 90 SFDR and THD vs Input Frequency SFDR –THD SINGLE SUPPLY 5V INPUT RANGE AIN = 0dBFS DIFFERENTIAL INPUT 6Msps 0.1 1 10 INPUT FREQUENCY (MHz) 100 1740 G06 50 1740f 5 LTC1740 TYPICAL PERFOR A CE CHARACTERISTICS Spurious-Free Dynamic Range vs Input Amplitude 100 dBFS 90 90 100 dBFS SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 80 70 dBc 60 50 0 –50 DUAL SUPPLIES 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) 0 1740 G07 80 70 dBc 60 50 0 –50 SINGLE SUPPLY 5V INPUT RANGE DIFFERENTIAL INPUT 6Msps –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) 0 1740 G08 AMPLITUDE (dBc) S/(N + D) and SFDR vs Sample Frequency 95 90 85 0 SFDR AMPLITUDE (dBc) AMPLITIDE (dB) 75 70 65 60 SINGLE SUPPLY 5V INPUT RANGE 55 DIFFERENTIAL INPUT 6Msps 50 3 0 1 2 4 –60 –80 –100 –120 –140 AMPLITIDE (dB) 80 S/(N + D) 5 6 SAMPLE FREQUENCY (MHz) IDD vs Clock Frequency 49 47 2.0 2.5 45 IDD (mA) 43 41 VREF = 2.25V 39 ISS (mA) VREF = 4.5V 37 35 0 1 4 3 5 2 CLOCK FREQUENCY (MHz) 6 1740 G13 6 UW 7 1740 G10 Spurious-Free Dynamic Range vs Input Amplitude 95 90 85 80 75 70 65 S/(N + D) and SFDR vs Sample Frequency SFDR S/(N + D) 60 DUAL SUPPLIES 5V INPUT RANGE 55 DIFFERENTIAL INPUT 6Msps 50 3 0 1 2 4 5 6 SAMPLE FREQUENCY (MHz) 7 8 1740 G09 Nonaveraged 4096 Point FFT DUAL SUPPLIES 6Msps –20 fIN = 2.5MHz, 5VP-P DIFFERENTIAL INPUT –40 0 –20 –40 –60 –80 –100 –120 –140 0 0.5 2 1.5 1 FREQUENCY (MHz) 2.5 3 1740 G11 Nonaveraged 4096 Point FFT SINGLE SUPPLY 6Msps fIN = 2.5MHz, 5VP-P DIFFERENTIAL INPUT 8 0 0.5 2 1.5 1 FREQUENCY (MHz) 2.5 3 1740 G12 ISS vs Clock Frequency 1.5 1.0 0.5 0 0 1 5 2 3 4 CLOCK FREQUENCY (MHz) 6 1740 G14 1740f LTC1740 PIN FUNCTIONS + AIN (Pin 1): Positive Analog Input. – AIN (Pin 2): Negative Analog Input. VCM (Pin 3): 2.5V Reference Output. Optional input common mode for single supply operation. Bypass to GND with a 1µF to 10µF ceramic capacitor. SENSE (Pin 4): Reference Programming Pin. Ground selects VREF = 4.5V. Short to VREF for VREF = 2.25V. Connect SENSE to VDD to drive VREF with an external reference. Connect SENSE directly to VDD, VREF or GND. Do not drive SENSE with a logic signal. VREF (Pin 5): DAC Reference. Bypass to GND with a 1µF to 10µF ceramic capacitor. GND (Pins 6, 7, 10, 31, 34): Analog Power Ground. VDD (Pins 8, 9): Analog 5V Supply. Bypass to GND with a 1µF to 10µF ceramic capacitor. (Do not share a capacitor with Pins 32 and 33.) OGND (Pins 11, 28): Output Logic Ground. Connect to GND. D13 to D0 (Pins 12 to 18, 20 to 26): Data Outputs. The output format is two’s complement. OVDD (Pin 19): Positive Supply for the Output Logic. Can be 2.7V to 5.25V. Bypass to GND with a 1µF to 10µF ceramic capacitor. BUSY (Pin 27): BUSY is low when a conversion is in progress. When a conversion is finished and the ADC is acquiring the input signal, BUSY is high. Either the falling edge of BUSY or the rising edge of CLK can be used to latch the output data. VSS (Pins 29, 30): Negative Supply. Can be – 5V or 0V. If VSS is not shorted to GND, bypass to GND with a 1µF ceramic capacitor. VDD (Pins 32, 33): Analog 5V Supply. Bypass to GND with a 1µF to 10µF ceramic capacitor (do not share a capacitor with Pins 8, 9). CLK (Pin 35): Conversion Start Signal. This active high signal starts a conversion on its rising edge. OF (Pin 36): Overflow Output. This signal is high when the digital output is 01 1111 1111 1111 or 10 0000 0000 0000. U U U 1740f 7 LTC1740 FUNCTIONAL BLOCK DIAGRA 5V VDD + AIN S/H –AIN VCM MODE SELECT SENSE VREF VSS 0V OR –5V TI I G DIAGRA ANALOG INPUT N tCLOCK tH tL CLK tCONV tACQ DATA OUTPUT N-3 t2 BUSY 1740 TD 8 W 3V TO 5V OVDD PIPELINED 14-BIT ADC OF D13 (MSB) OUTPUT BUFFERS D0 (LSB) 2.5V REFERENCE BUSY DIGITAL CORRECTION LOGIC CLK 1740 FBD W U UW U GND GND OGND N+1 N+2 N+3 N-2 N-1 N t1 1740f LTC1740 APPLICATIO S I FOR ATIO Conversion Details The LTC1740 is a high performance 14-bit A/D converter that operates up to 6Msps. It is a complete solution with an on-chip sample-and-hold, a 14-bit pipelined CMOS ADC and a low drift programmable reference. The digital output is parallel, with a 14-bit two’s complement format and an out-of-range (overflow) bit. The rising edge of the CLK begins the conversion. The differential analog inputs are simultaneously sampled and passed on to the pipelined A/D. After two more conversion starts (plus a 100ns conversion time) the digital outputs are updated with the conversion result and will be ready for capture on the third rising clock edge. Thus even though a new conversion is begun every time CLK goes high, each result takes three clock cycles to reach the output. The analog signals that are passed from stage to stage in the pipelined A/D are stored on capacitors. The signals on these capacitors will be lost if the delay between conversions is too long. For accurate conversion results, the part should be clocked faster than 50kHz. In some pipelined A/D converters if there is no clock present, dynamic logic on the chip will droop and the power consumption sharply increases. The LTC1740 doesn’t have this problem. If the part is not clocked for 1ms, an internal timer will refresh the dynamic logic. Thus the clock can be turned off for long periods of time to save power. Power Supplies The LTC1740 will operate from either a single 5V or dual ± 5V supply, making it easy to interface the analog input to single or dual supply systems. The digital output drivers have their own power supply pin (OVDD) which can be set from 3V to 5V, allowing direct connection to either 3V or + VIN – +AIN ± VREF 1.8 ADC CORE –AIN VREF 1740 F01 Figure 1. Analog Input Circuit U 5V digital systems. For single supply operation, VSS should be connected to analog ground. For dual supply operation, VSS should be connected to – 5V. All VDD pins should be connected to a clean 5V analog supply. (Don’t connect VDD to a noisy system digital supply.) Analog Input Range The LTC1740 has a flexible analog input with a wide selection of input ranges. The input range is always differential and is set by the voltage at the VREF pin (Figure 1). The input range of the A/D core is fixed at ± VREF/1.8. The reference voltage, VREF, is either set by the on-chip voltage reference or directly driven by an external voltage. Internal Reference Figure 2 shows a simplified schematic of the LTC1740 reference circuitry. An on-chip temperature compensated bandgap reference (VCM) is factory trimmed to 2.500V. The voltage at the VREF pin sets the input span of the ADC to ±VREF/1.8. An internal voltage divider converts VCM to 2.250V, which is connected to a reference amplifier. The reference programming pin, SENSE, controls how the VREF 1µF TO ADC W UU + R1 5k 1k – SENSE R2 5k LOGIC 2.5V REFERENCE 2.250V VCM 1µF 1740 F02 Figure 2. Reference Circuit 1740f 9 LTC1740 APPLICATIO S I FOR ATIO reference amplifier drives the VREF pin. If SENSE is tied to ground, the reference amplifier feedback is connected to the R1/R2 voltage divider, thus making VREF = 4.500V. If SENSE is tied to VREF, the reference amplifier feedback is connected to SENSE thus making VREF = 2.250V. If SENSE is tied to VDD, the reference amplifier is disconnected from VREF and VREF can be driven by an external voltage. With additional resistors between VREF and SENSE, and SENSE and GND, VREF can be set to any voltage between 2.250V and 4.5V. An external reference or a DAC can be used to drive VREF over a 0V to 5V range (Figures 3a and 3b). The input impedance of the VREF pin is 1kΩ, so a buffer may be required for high accuracy. Driving VREF with a DAC is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. 5V VIN VOUT LT1019A-2.5 1µF VREF LTC1740 SENSE VCM 1µF 1740 F03a 5V Figure 3a. Using the LT1019-2.5 as an External Reference; Input Range = ± 1.39V LTC1740 + VREF 5k 1µF SENSE 5k LTC1450 1µF VCM – Figure 3b. Driving VREF with a DAC 10 U Both the VCM and VREF pins must be bypassed with capacitors to ground. For best performance, 1µF or larger ceramic capacitors are recommended. For the case of external circuitry driving VREF, a smaller capacitor can be used at VREF so the input range can be changed quickly. In this case, a 0.2µF or larger ceramic capacitor is acceptable. The VCM pin is a low output impedance 2.5V reference that can be used by external circuitry. For single 5V supply applications it is convenient to connect AIN – directly to the VCM pin. Driving the Analog Inputs The differential inputs of the LTC1740 are easy to drive. The inputs may be driven differentially or single-ended (i. e., the AIN – input is held at a fixed value). The AIN – and AIN + inputs are simultaneously sampled and any common mode signal is reduced by the high common mode rejection of the sample-and-hold circuit. Any common mode input value is acceptable as long as the input pins stay between VDD and VSS. During conversion the analog inputs are high impedance. At the end of conversion the inputs draw a small current spike while charging the sample-and-hold. For superior dynamic performance in dual supply mode, the LTC1740 should be operated with the analog inputs centered at ground, and in single supply mode the inputs should be centered at 2.5V. For the best dynamic performance, the analog inputs can be driven differentially via a transformer or differential amplifier. DC Coupling the Input 2.250V 1740 F03b W UU In many applications the analog input signal can be directly coupled to the LTC1740 inputs. If the input signal is centered around ground, such as when dual supply op amps are used, simply connect AIN – to ground and connect VSS to – 5V (Figure 4). In a single power supply system with the input signal centered around 2.5V, connect AIN – to VCM and VSS to ground (Figure 5). If the input signal is not centered around ground or 2.5V, the voltage for AIN – must be generated externally by a resistor divider or a voltage reference (Figure 6). 1740f LTC1740 APPLICATIO S I FOR ATIO 5V 0V VIN +AIN LTC1740 –AIN VCM 1µF VSS 1405 F04 –5V Figure 4. DC Coupling a Ground Centered Signal (Dual Supply System) 5V 2.5V VIN +AIN LTC1740 –AIN VCM 1µF VSS 1740 F05 Figure 5. DC Coupling a Signal Centered Around 2.5V (Single Supply System) 5V 2.500V VIN 0V 1.25V 5V +AIN LTC1740 –AIN VREF 1µF SENSE VSS 1740 F06 Figure 6. DC Coupling a 0V to 2.5V Signal AC Coupling the Input The analog inputs to the LTC1740 can also be AC coupled through a capacitor, though in most cases it is simpler to directly couple the input to the ADC. Figure 7 shows an example where the input signal is centered around ground and the ADC operates from a single 5V supply. Note that the performance would improve if the ADC was operated from a dual supply and the input was directly coupled (as in Figure 4). With AC coupling the DC resistance to ground should be roughly matched for AIN + and AIN – to maintain offset accuracy. U 5V C 0V VIN +AIN LTC1740 –AIN R R C VCM 1µF VSS 1740 F07 W UU Figure 7. AC Coupling to the LTC1740. Note That the Input Signal Can Almost Always Be Directly Coupled with Better Performance 5V MINI CIRCUITS T1-1T VIN 15Ω +AIN 1000pF 15Ω LTC1740 –AIN VCM 1µF VSS 1740 F08a Figure 8a. Single Supply Transformer Coupled Input 5V MINI CIRCUITS T1-1T VIN 15Ω +AIN 1000pF 15Ω LTC1740 –AIN VCM 1µF VSS 1740 F08b –5V Figure 8b. Dual Supply Transformer Coupled Input Differential Operation The THD and SFDR performance of the LTC1740 can be improved by using a center tap RF transformer to drive the inputs differentially. Though the signal can no longer be DC coupled, the improvement in dynamic performance makes this an attractive solution for some applications. Typical connections for single and dual supply systems are shown in Figures 8a and 8b. Good choices for transformers are the Mini Circuits T1-1T (1:1 turns ratio) and T4-6T (1:4 turns ratio). For best results the transformer should be located close to the LTC1740 on the printed circuit board. 1740f 11 LTC1740 APPLICATIO S I FOR ATIO Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (30pF) external buffers or 100Ω resistors in series with the digital outputs are suggested. R1 50k –5V 1µF Figure 11. Offset and Full-Scale Adjust Circuit U Timing The conversion start is controlled by the rising edge of the CLK pin. Once a conversion is started it cannot be stopped or restarted until the conversion cycle is complete. Output data is updated at the end of conversion, or about 100ns after a conversion is begun. There is an additional two cycle pipeline delay, so the data for a given conversion is output two full clock cycles plus 100ns after the convert start. Thus output data can be latched on the third CLK rising edge after the rising edge that samples the input. Clock Input The LTC1740 only uses the rising edge of the CLK pin for internal timing, and CLK doesn’t necessarily need to have a 50% duty cycle. For optimal AC performance the rise time of the CLK should be less than 5ns. If the available clock has a rise time slower than 5ns, it can be locally sped up with a logic gate. The clock can be driven with 5V CMOS, 3V CMOS or TTL logic levels. 5V VIN 24k –AIN 100Ω LTC1740 VREF 10k R2 1k 10k –5V SENSE VSS 1740 F11 W UU 5V +AIN 1740f 13 LTC1740 APPLICATIO S I FOR ATIO As with all fast ADCs, the noise performance of the LTC1740 is sensitive to clock jitter when high speed inputs are present. The SNR performance of an ADC when the performance is limited by jitter is given by: SNR = – 20log (2π fIN tJ)dB where fIN is the frequency of an input sine wave and tJ is the root-mean-square jitter due to the clock, the analog input and the A/D aperture jitter. To minimize clock jitter, use a clean clock source such as a crystal oscillator, treat the clock signals as sensitive analog traces and use dedicated packages with good supply bypassing for any clock drivers. Board Layout To obtain the best performance from the LTC1740, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be placed under and around the ADC. Pins 6, 7, 10, 31, 34 (GND), Pins 11, 28 (OGND) and all other analog grounds should be connected to this ground plane. In single supply mode, Pins 29, 30 (VSS) should also be connected to this ground plane. All bypass capacitors for the LTC1740 should also be connected to this ground plane (Figure 12). The digital system ground 1 1000pF ANALOG INPUT CIRCUITRY +AIN –AIN VCM 3 1µF VREF 5 1µF + – 2 GND GND VDD VDD GND OGND OVDD 6 7 8 9 1µF 10 11 19 1µF ANALOG GROUND PLANE 1740 F12 Figure 12. Power Supply Grounding 1740f 14 U should be connected to the analog ground plane at only one point, near the OGND pin (Pin 28). The analog ground plane should be as close to the ADC as possible. Care should be taken to avoid making holes in the analog ground plane under and around the part. To accomplish this, we recommend placing vias for power and signal traces outside the area containing the part and the decoupling capacitors (Figure 13). Supply Bypassing High quality, low series resistance ceramic 1µF capacitors should be used at the VDD pins, VCM and VREF. If VSS is connected to – 5V it should also be bypassed to ground with 1µF. In single supply operation VSS should be shorted to the ground plane as close to the part as possible. OVDD requires a 1µF decoupling capacitor to ground. Surface mount capacitors such as the AVX 0805ZC105KAT provide excellent bypassing in a small board space. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. LTC1740 PLACE NON-GROUND VIAS AWAY FROM GROUND PLANE AND BYPASS CAPACITORS BYPASS CAPACITOR ANALOG GROUND PLANE 1740 F13 W UU AVOID BREAKING GROUND PLANE IN THIS AREA Figure 13. Cross Section of the LTC1740 Printed Circuit Board LTC1740 VSS VSS GND VDD VDD GND OGND 29 30 1µF 31 32 33 1µF 34 28 DIGITAL SYSTEM LTC1740 PACKAGE DESCRIPTION G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ± 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.8 – 8.2 0.42 ± 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) 0 ° – 8° 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) 0.05 (.002) G36 SSOP 0802 1740f 15 LTC1740 RELATED PARTS PART NUMBER LTC1405 LTC1406 LTC1411 LTC1412 LTC1414 LTC1420 LT1461 LTC1666 LTC1667 LTC1668 LTC1741 LTC1742 LTC1743 LTC1744 LTC1745 LTC1746 LTC1747 LTC1748 LT1807 DESCRIPTION 12-Bit, 5Msps Sampling ADC with Parallel Output 8-Bit, 20Msps ADC 14-Bit, 2.5Msps ADC 12-Bit, 3Msps, Sampling ADC 14-Bit, 2.2Msps ADC 12-Bit, 10Msps ADC Micropower Precision Series Reference 12-Bit, 50Msps DAC 14-Bit, 50Msps DAC 16-Bit, 50Msps DAC 12-Bit, 65Msps ADC 14-Bit, 65Msps ADC 12-Bit, 50Msps ADC 14-Bit, 50Msps ADC 12-Bit, 25Msps ADC 14-Bit, 25Msps ADC 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC 325MHz, Low Distortion Dual Op Amp COMMENTS Pin Compatible with the LTC1420 Undersampling Capability up to 70MHz 5V, No Pipeline Delay, 80dB SINAD ± 5V, No Pipeline Delay, 72dB SINAD ± 5V, 81dB SINAD and 95dB SFDR 71dB SINAD and 83dB SFDR at Nyquist 0.04% Max Initial Accuracy, 3ppm/°C Drift Pin Compatible with the LTC1668, LTC1667 Pin Compatible with the LTC1668, LTC1666 16-Bit, No Missing Codes, 90dB SINAD, –100dB THD Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 76.3dB SNR and 90dB SFDR Rail-to-Rail Input and Output 1740f 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q LT/TP 0603 1K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003