LTC1753

LTC1753 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® III Processor FEATURES s s s s s s s s s DESCRIPTIO s s s 5-Bit Digitally Programmable 1.3V to 3.5V Fixed Output Voltage, VRM 8.4 Compliant Fast Transient Response: 0% to 100% Duty Cycle Phase Lead Compensation for Remote Sensing Overtemperature Protection Flags for Power Good and Overvoltage Fault 19A Output Current Capability from a 5V Supply Dual N-Channel MOSFET Synchronous Driver Initial Output Accuracy: ± 1.5% Excellent Output Accuracy: ±2% Typ Over Line, Load and Temperature Variations High Efficiency: Over 95% Possible Adjustable Current Limit Without External Sense Resistors Available in 2O-Lead SSOP and SW Packages APPLICATIO S s s Power Supply for Pentium® III, AMD-K6®-2, SPARC, ALPHA and PA-RISC Microprocessors High Power 5V to 1.3V-3.5V Regulators The LTC®1753 is a high power, high efficiency switching regulator controller optimized for 5V input to a digitally programmable 1.3V-3.5V output. The internal 5-bit DAC programs the output voltage from 1.3V to 2.05V in 50mV increments and from 2.1V to 3.5V in 100mV increments. The precision internal reference and an internal feedback system provide an output accuracy of ± 1.5% at room temperature and typically ± 2% over temperature, load current and line voltage shifts. The LTC1753 uses a synchronous switching architecture with two external N-channel output devices, providing high efficiency and eliminating the need for a high power, high cost P-channel device. Additionally, it senses the output current across the on-resistance of the upper Nchannel FET, providing an adjustable current limit without an external low value sense resistor. The LTC1753 free-runs at 300kHz and can be synchronized to a faster external clock if desired. It provides a phase lead compensation scheme and under harsh loading conditions, the PWM duty cycle can be momentarily forced to 0% or 100% to reduce the output voltage recovery time. , LTC and LT are registered trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. TYPICAL APPLICATIO 5.6k PVCC 12V VIN 5V 0.1µF 5.6k + 10µF 600Ω 0.1µF + 10µF Q1A* PWRGD FAULT CPU 5 VID0 TO VID4 OUTEN COMP RC 15k CC 4700pF SS SGND GND SENSE LTC1753 Q2A* G2 VFB NC Q2* VCC IMAX PVCC G1 IFB 20Ω Q1* LO† 1.3µH 18A COUT†† 2700µF ×5 VOUT 1.3V TO 3.5V 14A C1 150pF CSS 0.1µF 1µF * SILICONIX SUD50N03-10 ** SANYO 10MV1200GX † PANASONIC ETQP 6FIR3LFA †† SANYO 6MV2700GX Figure 1. 5V to 1.3V-3.5V Supply Application U + CIN** 1200µF ×4 U U + 1753 F01 1 LTC1753 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW G2 PVCC GND SGND VCC SENSE IMAX IFB SS 1 2 3 4 5 6 7 8 9 20 G1 19 OUTEN 18 VID0 17 VID1 16 VID2 15 VID3 14 VID4 13 PWRGD 12 FAULT 11 VFB Supply Voltage VCC ........................................................................ 7V PVCC ................................................................... 14V Input Voltage IFB (Note 2) ............................................ PVCC + 0.3V IMAX ........................................................ – 0.3V to 9V All Other Inputs ...................... – 0.3V to (VCC + 0.3V) Digital Output Voltage ................................. – 0.3V to 9V IFB Input Current (Notes 2, 3) .......................... – 100mA Junction Temperature .......................................... 125°C Operating Temperature Range ..................... 0°C to 70°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................. 300°C ORDER PART NUMBER LTC1753CG LTC1753CSW COMP 10 G PACKAGE SW PACKAGE 20-LEAD PLASTIC SSOP 20-LEAD PLASTIC SO TJMAX = 125°C, θJA = 100°C/ W (G) TJMAX = 125°C, θJA = 100°C/ W (SW) Consult factory for Industrial and Military grade parts. The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, PVCC = 12V, unless otherwise noted. (Note 3) SYMBOL VCC PVCC VFB PARAMETER Supply Voltage Supply Voltage for G1, G2 Internal Feedback Voltage 1.3V Output Voltage 2.1V Initial Output Voltage 3.5V Initial Output Voltage With Respect to Rated Output Voltage (Figure 2) – 20 (– 1.5%) – 27 (– 1.5%) – 42 (– 1.5%) – 52 (– 1.5%) – 26 (– 2%) – 36 (– 2%) – 56 (– 2%) – 70 (– 2%) –5 ±1 q q q q q ELECTRICAL CHARACTERISTICS CONDITIONS q q MIN 4.5 TYP MAX 6 13.2 UNITS V V V V V 0.5 0.8 1.34 20 (+ 1.5%) 27 (+ 1.5%) 42 (+ 1.5%) 52 (+ 1.5%) 26 (+ 2%) 36 (+ 2%) 56 (+ 2%) 70 (+ 2%) VOUT 1.3V Initial Output Voltage 1.8V Initial Output Voltage 2.8V Initial Output Voltage 3.5V Initial Output Voltage 1.3V Initial Output Voltage 1.8V Initial Output Voltage 2.8V Initial Output Voltage 3.5V Initial Output Voltage Output Load Regulation Output Line Regulation Positive Power Good Trip Point Negative Power Good Trip Point FAULT Trip Point Operating Supply Current Shutdown Supply Current Supply Current Internal Oscillator Frequency VCOMP at Minimum Duty Cycle VCOMP at Maximum Duty Cycle q q q q ∆VOUT VPWRGD VFAULT ICC IPVCC fOSC VSAWL VSAWH IOUT = 0 to 14A (Figure 2) VIN = 4.75V to 5.25V, IOUT = 0 (Figure 2) % Above Output Voltage (Note 4) (Figure 2) % Below Output Voltage (Note 4) (Figure 2) % Above Output Voltage (Note 4) (Figure 2) OUTEN = VCC = 5V (Note 5)(Figure 3) OUTEN = 0, VID0 to VID4 Floating (Figure 3) PVCC = 12V, OUTEN = VCC (Note 6) (Figure 3) PVCC = 12V, OUTEN = 0, VID0 to VID4 Floating (Figure 4) (Note 11) (Note 11) q –6 8 3 –3 13 800 130 15 1 6 18 1200 250 250 300 1.8 2.8 350 2 U mV mV mV mV mV mV mV mV mV mV % % % µA µA mA µA kHz V V W U U WW W LTC1753 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, PVCC = 12V, unless otherwise noted. (Note 3) SYMBOL GERR gmERR BWERR IIMAX ISS ISSIL ISSHIL tSSHIL t PWRGD t PWRBAD t FAULT VOTDD VSHDN t r, t f t NOL VIH VIL RSENSE RVID ISINK PARAMETER Error Amplifier Open-Loop DC Gain Error Amplifier Transconductance Error Amplifier – 3dB Bandwidth IMAX Sink Current Soft-Start Source Current Maximum Soft-Start Sink Current Under Current Limit Soft-Start Sink Current Under Hard Current Limit Hard Current Limit Hold Time Power Good Response Time↑ Power Good Response Time↓ FAULT Response Time Overtemperature Driver Disable Shutdown Driver Rise and Fall Time Driver Nonoverlap Time VID0 to VID4 Input High Voltage VID0 to VID4 Input Low Voltage SENSE Input Resistance VID0 to VID4 Internal Pull-Up Resistance Digital Output Sink Current q q ELECTRICAL CHARACTERISTICS CONDITIONS (Note 7) (Note 7) COMP = Open (Note 11) VIMAX = VCC VSS = 0V, VIMAX = 0V, VIFB = VCC VSENSE = VOUT, VIMAX = VCC, VIFB = 0V (Notes 8, 9), VSS = VCC VSENSE = 0V, VIMAX = VCC, VIFB = 0V VSENSE = 0V, VIMAX = 4V, VIFB↓ from 5V VSENSE↑ from 0V to Rated VOUT VSENSE↓ from Rated VOUT to 0V VSENSE↑ from Rated VOUT to VCC OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) (Figure 4) (Figure 4) q q q q q q q q q q q q q q q MIN 40 0.9 150 – 16 30 20 TYP 54 1.6 400 190 – 12 60 45 500 MAX 2.3 230 –8 150 UNITS dB millimho kHz µA µA µA mA µs 0.5 200 200 1.6 1 500 500 1.7 90 2 1000 1000 1.8 0.8 150 ms µs µs V V ns ns V 30 2 100 0.8 108 V kΩ kΩ mA 10 10 20 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: When IFB is taken below GND, it will be clamped by an internal diode. This pin can handle input currents greater than 100mA below GND without latchup. In the positive direction, it is not clamped to VCC or PVCC. Note 3: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: The Power Good and FAULT trip thresholds are tested at the 1.8V output voltage code. The Power Good and FAULT trip thresholds are guaranteed by design for all other output voltage codes to the same specification. Note 5: The LTC1753 goes into the shutdown mode if VID0 to VID4 are floating. Due to the internal pull-up resistors, there will be an additional 0.25mA/pin if any of the VID0 to VID4 pins are pulled low. Note 6: Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC1753 operating frequency, supply voltage and the external FETs used. Note 7: The open-loop DC gain and transconductance from the SENSE pin to COMP pin will be (GERR)(1.26/3.3) and (gmERR)(1.26/3.3) respectively. Note 8: The current limiting amplifier can sink but cannot source current. Under normal (not current limited) operation, the output current will be zero. Note 9: Under typical soft current limit, the net soft-start discharge current will be 60µA (ISSIL) + [– 12µA(ISS)] ≅ 48µA. The soft-start sink-to-source current ratio is designed to be 5:1. Note 10: When VID0 to VID4 are all HIGH, the LTC1753 will be forced to shut down internally. The OUTEN trip voltages are guaranteed by design for all other input codes. Note 11: This parameter is guaranteed by design and correlation and is not tested in production. 3 LTC1753 TYPICAL PERFOR A CE CHARACTERISTICS Typical 1.3V VOUT Distribution 50 TOTAL SAMPLE SIZE = 500 40 40 NUMBER OF UNITS NUMBER OF UNITS EFFICIENCY (%) 30 25°C 100°C 20 10 0 1.275 1.285 1.305 1.315 1.295 OUTPUT VOLTAGE (V) Load Regulation 2.825 REFER TO TYPICAL APPLICATION 2.820 CIRCUIT FIGURE 1 V = 5V, PVCC = 12V, TA = 25°C 2.815 IN OUTPUT VOLTAGE (V) 2.810 2.805 2.800 2.795 2.790 2.785 2.780 2.775 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUTPUT CURRENT (A) 1753 G04 OUTPUT VOLTAGE (V) 2.810 2.805 2.800 2.795 2.790 2.785 2.780 2.775 4.75 4.85 5.05 5.15 4.95 INPUT VOLTAGE (V) 5.25 1753 G05 OUTPUT VOLTAGE (V) 1.78 1.76 1.74 1.72 1.70 1.68 1.66 1.64 1.62 1.60 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 2.1 1.9 1.7 1.5 1.3 1.1 0.9 – 50 –25 ERROR AMPLIFIER OPEN-LOOP DC GAIN (dB) 1.80 OVER-TEMPERATURE DRIVER DISABLE (V) ERROR AMPLIFIER TRANSCONDUCTANCE (millimho) Overtemperature Driver Disable vs Temperature 4 UW 1753 G07 Typical 2.8V VOUT Distribution 50 TOTAL SAMPLE SIZE = 500 100 90 80 25°C 100°C 20 70 60 50 40 30 10 20 10 1.325 1753 G01 Efficiency vs Load Current A B 30 REFER TO TYPICAL APPLICATION CIRCUIT FIGURE 1 VIN = 5V, PVCC = 12V, VOUT = 2.8V, COUT = 330µF × 7, LO = 2µH A: Q1 = 1 × SUD50N03-10 Q2 = 1 × SUD50N03-10 B: Q1 = 2 × SUD50N03-10 Q2 = 1 × SUD50N03-10 NO FAN Q1 IS MOUNTED ON 1IN2 COPPER AREA 0 0.3 2 4 6 8 10 LOAD CURRENT (A) 12 14 0 2.75 0 2.77 2.81 2.83 2.79 OUTPUT VOLTAGE (V) 2.85 1753 G02 1753 G03 Line Regulation 2.825 2.820 2.815 REFER TO TYPICAL APPLICATION CIRCUIT FIGURE 1 OUTPUT = NO LOAD TA = 25°C 2.860 2.850 2.840 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.760 2.750 Output Temperature Drift 2.740 – 50 – 25 50 0 75 25 TEMPERATURE (°C) 100 125 1753 G06 Error Amplifier Transconductance vs Temperature 2.3 60 Error Amplifier Open-Loop DC Gain vs Temperature 55 50 45 50 25 75 0 TEMPERATURE (°C) 100 125 40 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 1753 G08 1753 G09 LTC1753 TYPICAL PERFOR A CE CHARACTERISTICS Oscillator Frequency vs Temperature 350 340 OSCILLATOR FREQUENCY (kHz) IMAX SINK CURRENT (µA) 220 210 200 190 180 170 160 150 –50 SOFT START SOURCE CURRENT (µA) –25 75 0 50 25 TEMPERATURE (°C) 100 125 330 320 310 300 290 280 270 260 250 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 VCC Operating Supply Current vs Temperature 1.2 VCC OPERATING SUPPLY CURRENT (mA) VCC SHUTDOWN SUPPLY CURRENT (µA) 1.1 1.0 0.9 0.8 0.7 0.6 VCC = 5V fOSC = 300kHz 200 175 150 125 100 75 50 – 50 – 25 0 75 50 25 TEMPERATURE (°C) 100 125 PVCC SUPPLY CURRENT (mA) 0.5 – 50 –25 50 25 75 0 TEMPERATURE (°C) Output Over Current Protection 3.0 2.5 Q1 CASE = 90°C, VOUT = 2.8V Q1 = 2 × MTD20N03HDL Q2 = 1 × MTD20N03HDL RIMAX = 2.7k, RIFB = 20Ω, SS CAP = 0.01µF OUTPUT VOLTAGE (V) 2.0 1.5 1.0 SHORT-CIRCUIT CURRENT 0.5 0 0 2 4 6 8 10 12 14 OUTPUT CURRENT (A) 16 18 UW 1753 G10 IMAX Sink Current vs Temperature –8 –9 –10 –11 –12 –13 –14 –15 Soft-Start Source Current vs Temperature –16 – 50 – 25 50 25 75 0 TEMPERATURE (°C) 100 125 1753 G11 1753 G12 VCC Shutdown Supply Current vs Temperature 250 225 70 60 50 40 30 20 10 0 PVCC Supply Current vs Gate Capacitance PVCC = 12V TA = 25°C 100 125 0 2000 4000 6000 GATE CAPACITANCE (pF) 8000 1753 G15 1753 G13 1753 G14 Transient Response, VOUT = 2.8V VOUT 50mV/DIV 10 ILOAD 5A/DIV 0 50µs/DIV 1753 G17 1753 G16 5 LTC1753 TYPICAL PERFOR A CE CHARACTERISTICS Expanded View of Undershoot Illustrates 100% Duty Cycle Operation, VOUT = 2.8V Expanded View of Overshoot Illustrates 0% Duty Cycle Operation, VOUT = 2.8V VOUT 20mV/DIV G1 10V/DIV 5µs/DIV 1753 G18 PI FU CTIO S G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET, Q2. This output will swing from PVCC to GND. It will always be low when G1 is high or when the output is disabled. To prevent undershoot during a soft-start cycle, G2 is held low until G1 first goes high. PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be connected to a potential of at least VIN + VGS(ON)Q1. For normal applications, connect PVCC to a 12V power supply or generate PVCC using a simple charge pump. GND (Pin 3): Power Ground. GND should be connected to a low impedance ground plane in close proximity to the source of Q2. SGND (Pin 4): Signal Ground. SGND is connected to the low power internal circuitry and should be connected to the negative terminal of the output capacitor where it returns to the ground plane. GND and SGND should be shorted directly at the LTC1753. VCC (Pin 5): Power Supply. Power for the internal low power circuity. VCC should be wired separately from the drain of Q1 if they share the same supply. A 10µF bypass capacitor is recommended from this pin to SGND. SENSE (Pin 6): Output Voltage Pin. Connect to the positive terminal of the output capacitor. There is an internal 108k resistor connected from this pin to SGND. SENSE is a very sensitive pin; for optimum performance, connect an external 1µF capacitor from this pin to SGND. By connecting a small external resistor between the output capacitor and the SENSE pin, the initial output voltage can be raised slightly. Since the internal divider has a nominal impedance of 108kΩ, a 1100Ω series resistor will raise the nominal output voltage by 1%. If an external resistor is used, the value of the 1µF capacitor on the SENSE pin must be greatly reduced or loop phase margin will suffer. Set a time constant for the RC combination of approximately 0.1µs. So, for example, with a 1100Ω resistor, set C = 90pF. Use a standard 100pF capacitor. In addition, LTC recommends that the 1µF capacitor be connected from the top of the additional external resistor directly to SGND. IMAX (Pin 7): Current Limit Threshold. Current limit is set by the voltage drop across an external resistor connected between the drain of Q1 and IMAX. There is a 190µA internal pull-down at IMAX. IFB (Pin 8): Current Limit Sense Pin. Connect to the switching node between the source of Q1 and the drain of Q2. If IFB drops below IMAX when G1 is on, the LTC1753 will go into current limit. The current limit circuit can be disabled by floating IMAX and shorting IFB to VCC. SS (Pin 9): Soft-Start. Connect to an external capacitor to implement a soft-start function. During moderate overload conditions, the soft-start capacitor will be discharged slowly in order to reduce the duty cycle. In hard current limit, the soft-start capacitor will be forced low immediately and the LTC1753 will rerun a complete soft-start cycle. CSS must be selected such that during power-up the current through Q1 will not exceed the current limit value. 6 UW VOUT 20mV/DIV G1 10V/DIV 5µs/DIV 1753 G19 U U U LTC1753 PI FU CTIO S COMP (Pin 10): External Compensation. The COMP pin is connected directly to the output of the error amplifier and the input of the PWM comparator. An RC + C network is used at this node to compensate the feedback loop to provide optimum transient response. VFB (Pin 11): Voltage Feedback. VFB is the tap point of the internal resistor divider connected from SENSE to SGND. During rapid and heavy output loading conditions, a small capacitor between the SENSE and VFB pin creates a feedforward path that reduces the transient recovery time. For applications where extremely low output ripple is required, low ESR capacitors are typically used. In this case, a small capacitor between SENSE and VFB helps to compensate the switching loop. This pin can be left floating, but should be isolated from high current switching nodes. FAULT (Pin 12): Overvoltage Fault. FAULT is an opendrain output. If VOUT reaches 13% above the nominal output voltage, FAULT will go low and G1 and G2 will be disabled. Once triggered, the LTC1753 will remain in this state until the power supply is recycled or the OUTEN pin is toggled. If OUTEN = 0, FAULT floats or is pulled high by an external resistor. PWRGD (Pin 13): Power Good. This is an open-drain signal to indicate validity of output voltage. A high indicates that the output has settled to within ± 3% of the rated output for more than 1ms. PWRGD will go low if the output is out of regulation for more than 500µs. If OUTEN = 0, PWRGD pulls low. VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14): Digital Voltage Select. TTL inputs used to set the regulated output voltage required by the processor (Table 2). There is an internal 20kΩ pull-up at each pin. When all five VIDn pins are high or floating, the chip will shut down. OUTEN (Pin 19): Output Enable. TTL input which enables the output voltage. The external MOSFET temperature can be monitored with an external thermistor as shown in Figure 11. When the OUTEN input voltage drops below 1.7V, the drivers are internally disabled to prevent the MOSFETs from heating further. If OUTEN is less than 1.2V for longer than 30µs, the LTC1753 will enter shutdown mode. The internal oscillator can be synchronized to a faster external clock by applying the external clocking signal to the OUTEN pin. (See Applications Information.) G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET, Q1. This output will swing from PVCC to GND. It will always be low when G2 is high or the output is disabled. U U U 7 LTC1753 BLOCK DIAGRA W 12 FAULT DELAY LOGIC OUTEN 19 DISDR SYSTEM POWER DOWN 13 PWRGD 2 PVCC QSS ERR 113% VREF + FC – COMP 10 ISS SS 9 + – VREF MHCL HCL MONO 8 + 1 G2 11 VFB BG MIN MAX – PWM R S 20 G1 – + – + 6 SENSE 18 VID0 VREF – 3% VREF + 3% 66.5k 17 VID1 16 VID2 – CC 8 IFB 41.5k 7 IMAX IMAX VREF DAC 15 VID3 14 VID4 + + LVC 0.5VREF / 0.7VREF – 1553 BD LTC1753 TEST CIRCUITS VCC 5V PVCC 12V VIN 5V + 3k 3k 10µF 0.1µF 10µF + 0.1µF + CIN** 1200µF ×4 100pF 100pF OUTEN PWRGD FAULT VCC PVCC IFB G1 IMAX NC Q1A* LO† Q1* 1.3µH 15A COUT†† + 2700µF ×5 VOUT LTC1753 VID0 TO VID4 VID0 TO VID4 COMP SS SGND GND SENSE G2 VFB NC Q2A* Q2* C1 150pF RC 15k CC 4700pF 0.1µF 1µF * SILICONIX Si4410 ** SANYO 10MV1200GX † PANASONIC ETQP 6FIR3LFA †† SANYO 6MV2700GX 1753 F02 Figure 2 VCC VID0 VID1 VID2 VID3 VID4 VCC 0.1µF VCC IFB PVCC G1 NC NC NC NC 0.1µF PVCC + 10µF VID0 VID1 VID2 VID3 VID4 OUTEN NC NC NC PWRGD LTC1753 FAULT COMP SS NC SGND GND + 10µF IMAX G2 VFB SENSE 1573 F03 Figure 3 VCC 5V PVCC 12V tr tf 90% 50% G1 5000pF G1 RISE/FALL 10% 90% 50% 10% + 10µF 0.1µF VCC IFB NC VOUT VFB SENSE SGND GND LTC1753 PVCC 0.1µF + 10µF t NOL G2 5000pF G2 RISE/FALL 50% t NOL 50% 1753 F04 Figure 4 9 LTC1753 FU CTIO TABLES Table 1. PWRGD and FAULT Logic INPUT OUTEN 0 1 1 1 1 VSENSE** X < 97% > 97% < 103% >103% > 113% FAULT 1 1 1 1 0 OUTPUT* PWRGD 0 0 1 0 0 VID4 VID3 Table 2. Rated Output Voltage INPUT PIN VID4 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 RATED OUTPUT VOLTAGE (V) 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 APPLICATIO S I FOR ATIO OVERVIEW The LTC1753 is a voltage feedback, synchronous switching regulator controller (see Block Diagram) designed for use in high power, low voltage step-down (buck) converters. It includes an on-chip DAC to control the output voltage, a PWM generator, a precision reference trimmed to ±1%, two high power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit. The LTC1753 includes a current limit sensing circuit that uses the upper external power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Once the current comparator, CC, detects an overcurrent condition, the duty cycle is reduced by discharging the soft-start capacitor through a voltage- 10 U W UU U U Table 2. Rated Output Voltage (cont) INPUT PIN VID2 VID1 VID0 RATED OUTPUT VOLTAGE (V) 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 SHDN 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 1 0 1 1 1 2.8 1 0 1 1 0 2.9 1 0 1 0 1 3.0 1 0 1 0 0 3.1 1 0 0 1 1 3.2 1 0 0 1 0 3.3 1 0 0 0 1 3.4 1 0 0 0 0 3.5 * With external pull-up resistor ** With respect to the output voltage selected in Table 2 X Don’t care controlled current source. Under severe overloads or output short circuit conditions, the chip will be repeatedly forced into soft-start until the short is removed, preventing the external components from being damaged. Under output overvoltage conditions, the MOSFET drivers will be disabled permanently until the chip power supply is recycled or the OUTEN pin is toggled. OUTEN can optionally be connected to an external negative temperature coefficient (NTC) thermistor placed near the external MOSFETs or the microprocessor. Two threshold levels are provided internally. When OUTEN drops to 1.7V, the G1 and G2 pins will be forced low. If OUTEN is pulled below 1.2V, the LTC1753 will go into shutdown mode, cutting the supply current to a minimum. If thermal shutdown is not required, OUTEN can be connected to a LTC1753 APPLICATIO S I FOR ATIO conventional TTL enable signal. The free-running 300kHz PWM frequency can be synchronized to a faster external clock connected to OUTEN. Adjusting the oscillator frequency can add flexibility in the external component selection. See the Clock Synchronization section. Output regulation can be monitored with the PWRGD pin which in turn monitors the internal MIN and MAX comparators. If the output is ± 3% beyond the selected value for more than 500µs, the PWRGD output will be pulled low. Once the output has settled within ± 3% of the selected value for more than 1ms, PWRGD will return high. THEORY OF OPERATION Primary Feedback Loop The regulator output voltage at the SENSE pin is divided down internally by a resistor divider with a total resistance of approximately 108k. This divided down voltage is subtracted from a reference voltage supplied by the DAC output. The resulting error voltage is amplified by the error amplifier and the output is compared to the oscillator ramp waveform by the PWM comparator. This PWM signal controls the external MOSFETs through G1 and G2. The resulting chopped waveform is filtered by LO and COUT closing the loop. Loop frequency compensation is achieved with an external RC + C network at the COMP pin, which is connected to the output node of the transconductance amplifier. In low output ripple voltage applications, low ESR output capacitors are typically used. Under this condition, a capacitor between the SENSE and VFB pins helps compensate the switching loop. For heavy transient output loading applications, a small capacitor between the SENSE and VFB pin acts as a feedforward path and helps reduce the transient recovery time. MIN, MAX Feedback Loops Two additional comparators in the feedback loop provide high speed fault correction in situations where the ERR amplifier may not respond quickly enough. MIN compares the feedback signal VFB to a voltage 3% below the internal reference. If VFB is lower than the threshold of this comparator, the MIN comparator overrides the ERR amplifier and forces the loop to 100% duty cycle. U Similarly, the MAX comparator forces the output to 0% duty cycle if VFB is more than 3% above the internal reference. To prevent these two comparators from triggering due to noise, output voltage ripple must be controlled with sufficient output bypassing to prevent jitter. In addition, the MIN and MAX comparators’ response times are deliberately controlled so that they take about one microsecond to respond. These two comparators help prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability. Soft-Start and Current Limit The LTC1753 includes a soft-start circuit which is used for initial start-up and during current limit operation. The SS pin requires an external capacitor to GND with the value determined by the required soft-start time. An internal 12µA current source is included to charge the external SS capacitor. During start-up, the COMP pin is clamped to a diode drop above the voltage at the SS pin. This prevents the error amplifier, ERR, from forcing the loop to 100% duty cycle. The LTC1753 will begin to operate at low duty cycle as the SS pin rises above about 1.2V (VCOMP ≈ 1.8V). As SS continues to rise, QSS turns off and the error amplifier begins to regulate the output. The MIN comparator is disabled when soft-start is active to prevent it from overriding the soft-start function. The LTC1753 includes yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples and holds the voltage drop measured across the external MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases due to the drop across the RDS(ON) of Q1. When the voltage at IFB drops below IMAX, indicating that Q1’s drain current has exceeded the maximum level, CC starts to pull current out of the external soft-start capacitor, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin will fall gradually, creating a time delay before current limit takes effect. Very short, mild W UU 11 LTC1753 APPLICATIO S I FOR ATIO MAXIMUM OPERATING LOAD CURRENT (A) 8 10 12 14 16 18 Si4410 820 1.2k — — — — Table 3. Recommended RIMAX Resistor (kΩ) vs Maximum Operating Load Current and External MOSFET Q1 Si4410 (TWO IN PARALLEL) 430 560 680 820 910 1.2k SUD50N03 680 820 1k 1.2k 1.5k — VIN LTC1753 IMAX RIMAX overloads may not affect the output voltage at all. More significant overload conditions will allow the SS pin to reach a steady state, and the output will remain at a reduced voltage until the overload is removed. Serious overloads will generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. This helps minimize the number of components in the high current path. Due to switching noise and variation of RDS(ON), the actual current limit trip point is not highly accurate. The current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. For a given current limit level, the external resistor from IMAX to VIN can be determined by: RIMAX = where, I ILMAX = ILOAD + RIPPLE 2 ILOAD = Maximum load current IRIPPLE = Inductor ripple current = (ILMAX )(RDS(ON)Q1) IIMAX (VIN − VOUT )(VOUT ) (fOSC )(L O)(VIN) 12 U MTD20N03 (TWO IN PARALLEL) 1k 1.2k 1.5k 1.8k 2.0k 2.2k W UU + CIN + CC 190µA 7 G1 IFB 20Ω 8 Q1 LO VOUT – + G2 Q2 COUT 1753 F05 Figure 5. Current Limit Setting fOSC = LTC1753 oscillator frequency = 300kHz LO = Inductor value RDS(ON)Q1 = Hot on-resistance of Q1 at ILMAX IIMAX = Internal 190µA sink current at IMAX OUTEN and Thermistor Input The LTC1753 includes a low power shutdown mode, controlled by the logic at the OUTEN pin. A high at OUTEN allows the part to operate normally. A low level at OUTEN stops all internal switching, pulls COMP and SS to ground internally and turns Q1 and Q2 off. PWRGD is pulled low, and FAULT is left floating. In shutdown, the LTC1753 quiescent current drops to about 130µA. The residual current is used to keep the thermistor sensing circuit at OUTEN alive. Note that the leakage current of the external MOSFETs may add to the total shutdown current consumed by the circuit, especially at elevated temperatures. OUTEN is designed with two thresholds to allow it to also be utilized for overtemperature protection. The power MOSFET operating temperature can be monitored with an external negative temperature coefficient (NTC) thermistor LTC1753 APPLICATIO S I FOR ATIO mounted next to the external MOSFET which is expected to run the hottest –– often the high-side device, Q1. Electrically, the thermistor should form a voltage divider with another resistor, R1, connected to VCC. Their midpoint should be connected to OUTEN (see Figure 6). As the temperature increases, the OUTEN pin voltage is reduced. Under normal operating conditions, the OUTEN pin should stay above 1.7V and all circuits will function normally. If the temperature gets abnormally high, the OUTEN pin voltage will eventually drop below 1.7V, the LTC1753 disables both FET drivers. If OUTEN decreases below 1.2V, the LTC1753 enters shutdown mode. To activate any of these three modes, the OUTEN voltage must drop below the respective threshold for longer than 30µs. VIN VCC R1 R2 NTC THERMISTOR MOUNT IN CLOSE THERMAL PROXIMITY TO Q1 LTC1753 OUTEN G2 Q2 G1 Q1 LO Figure 6. OUTEN Pin as a Thermistor Input Clock Synchronization The internal oscillator can be synchronized to an external clock by applying the external clocking signal to the OUTEN pin. The synchronizing range extends from the initial operating frequency up to 500kHz. If the external frequency is much higher than the natural free-running frequency, the peak-to-peak sawtooth amplitude within the LTC1753 will decrease. Since the loop gain is inversely proportional to the amplitude of the sawtooth, the compensation network may need to be adjusted slightly. Note that the temperature sensing circuitry does not operate when external synchronization is used. U MOSFET Gate Drive Power for the internal MOSFET drivers is supplied by PVCC. This supply must be above the input supply voltage by at least one power MOSFET VGS(ON) for efficient operation. For a typical application, PVCC should be connected to a 12V power supply. If the OUTEN pin is low, G1 and G2 are both held low to prevent output voltage undershoot. As VCC and PVCC power up from a 0V condition, an internal undervoltage lockout circuit prevents G1 and G2 from going high until VCC reaches about 3.5V. If VCC powers up while PVCC is at ground potential, the SS is forced to ground potential internally. SS clamps the COMP pin low and prevents the drivers from turning on. On power-up or recovery from thermal shutdown, the drivers are designed such that G2 is held low until G1 first goes high. Power MOSFETs Two N-channel power MOSFETs are required for most LTC1753 circuits. Logic level MOSFETs should be used and they should be selected based on on-resistance and GATE threshold voltage considerations. RDS(ON) should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. GATE threshold voltages for logic level MOSFETs are lower than standard MOSFETs. A MOSFET whose RDS(ON) is rated at VGS = 4.5V does not necessarily have a logic level MOSFET GATE threshold voltage. Using standard MOSFETs instead of logic level MOSFETs can cause startup problems, especially if PVCC is derived from a charge pump scheme. In a typical LTC1753 buck converter circuit the average inductor current is equal to the output load current. This current is always flowing through either Q1 or Q2 with the power dissipation split up according to the duty cycle: + VOUT COUT 1753 F06 W UU V DC Q1 = OUT VIN () VIN − VOUT V DC Q2 = 1 − OUT = VIN VIN () ( ) 13 LTC1753 APPLICATIO S I FOR ATIO The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. (VIN)PMAX(Q1) RDS(ON)Q1 = = 2 [DC(Q1)](IMAX) (VOUT)(IMAX)2 PMAX(Q2) (VIN)PMAX(Q2) RDS(ON)Q2 = = 2 [DC(Q2)](IMAX) (VIN − VOUT)(IMAX)2 PMAX Q1 () PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed with a 5V input and a 2.8V, 11.2A output might allow no more than 4% efficiency loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: [(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET and a required RDS(ON) of: Table 4. Recommended MOSFETs for LTC1753 Applications RDS(ON) AT 25°C (mΩ) 19 20 35 8 10 7.5 14 28 37 PARTS Siliconix SUD50N03-10 D-PAK Siliconix Si4410DY SO-8 ON Semiconductor MTD20N03HDL D PAK Fairchild FDS6670A SO-8 Fairchild FDS6680 SO-8 ON Semiconductor MTB75N03HDL DD PAK IR IRL3103S DD PAK IR IRLZ44 TO-220 Fuji 2SK1388 TO-220 Note: Please refer to the manufacturer’s data sheet for testing conditions and detail information. 14 U W UU (5V)(1.39W) = 0.019Ω () 2 (2.8V)(11.2A) (5V)(1.39W) = 0.025Ω RDS(ON)Q2 = 2 (5V − 2.8V)(11.2A) RDS ON Q1 = Note also that while the required RDS(ON) values suggest large MOSFETs, the dissipation numbers are only 1.39W per device or less––large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03 or Motorola MTD20N03HDL (both in D PAK) are small footprint surface mount devices with RDS(ON) values below 0.03Ω at 5V of gate drive that work well in LTC1753 circuits. With higher output voltages, the RDS(ON) of Q1 may need to be significantly lower than that for Q2. These conditions can often be met by paralleling two MOSFETs for Q1 and using a single device for Q2. Note that using a higher PMAX value RATED CURRENT (A) 15 at 25°C 10 at 100°C 10 at 25°C 8 at 75°C 20 at 25°C 16 at 100°C 13 at 25°C 11.5 at 25°C 75 at 25°C 59 at 100°C 56 at 25°C 40 at 100°C 50 at 25°C 36 at 100°C 35 at 25°C TYPICAL INPUT CAPACITANCE CISS (pF) 3200 2700 880 3200 2070 4025 1600 3300 1750 θJC (°C/W) 1.8 — 1.67 25 25 1.0 1.8 1.0 2.08 TJMAX (°C) 175 150 150 150 150 150 175 175 150 LTC1753 APPLICATIO S I FOR ATIO in the RDS(ON) calculations will generally decrease MOSFET cost and circuit efficiency while increasing MOSFET heat sink requirements. Inductor Selection The inductor is often the largest component in the LTC1753 design and should be chosen carefully. Inductor value and type should be chosen based on output slew rate requirements, output ripple requirements and expected peak current. Inductor value is primarily controlled by the required current slew rate. The maximum rate of rise of current in the inductor is set by its value, the input-tooutput voltage differential and the maximum duty cycle of the LTC1753. In a typical 5V input, 2.8V output application, the maximum current slew rate will be: DCMAX (VIN − VOUT) = 1.83 L L A µs where L is the inductor value in µH. With proper frequency compensation, the combination of the inductor and output capacitor will determine the transient recovery time. In general, a smaller value inductor will improve transient response at the expense of increased output ripple voltage and inductor core saturation rating. A 2µH inductor would have a 0.9A/µs rise time in this application, resulting in a 5.5µs delay in responding to a 5A load current step. During this 5.5µs, the difference between the inductor current and the output current must be made up by the output capacitor, causing a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1µH to 5µH range for most typical 5V input LTC1753 circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. The ripple current is approximately equal to: U IRIPPLE = W UU (VIN − VOUT)(VOUT) (fOSC)(LO)(VIN) fOSC = LTC1753 oscillator frequency = 300kHz LO = Inductor value Solving this equation with our typical 5V to 2.8V application with a 2µH inductor, we get: (2.2)(0.56) = 2AP-P (300kHz)(2µH) Peak inductor current at 11.2A load: 11.2A + 2A = 12.2A 2 The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice. Input and Output Capacitors A typical LTC1753 design puts significant demands on both the input and the output capacitors. During constant load operation, a buck converter like the LTC1753 draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current plus 1/2 peak-to-peak ripple current, and the minimum value is zero. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal to IOUT /2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. 15 LTC1753 APPLICATIO S I FOR ATIO Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours (three months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer’s specification is recommended to extend the useful life of the circuit. Lower operating temperature will have the largest effect on capacitor longevity. The output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. Peak-to-peak current is equal to that in the inductor, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the LTC1753 can adjust the inductor current to the new value. Output capacitor ESR results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 11A load step with a 0.05Ω ESR output capacitor will result in a 550mV output voltage shift; this is 19.6% of the output voltage for a 2.8V supply! Because of the strong relationship between output capacitor ESR and output load transient response, the output capacitor is usually chosen for ESR, not for capacitance value; a capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage. Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC1753 applications. OS-CON electrolytic capacitors from Sanyo and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. AVX TPS series surface mount devices are popular surge tested tantalum capacitors that work well in LTC1753 applications. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. A typical LTC1753 application might exhibit 5A input ripple current. Sanyo OS-CON part number 10SA220M (220µF/10V) capacitors COMP 10 ERR RC CC C1 DAC Figure 7a. Compensation Pin Hook-Up Loop stability is affected by the values of the inductor, output capacitor, output capacitor ESR, FET RDS(ON), error amplifier transconductance and error amplifier compensation network. The inductor and the output capacitor create a double pole at the frequency: fLC = 1 2π√(LO)(COUT) 16 – + U feature 2.3A allowable ripple current at 85°C; three in parallel at the input (to withstand the input ripple current) will meet the above requirements. Similarly, AVX TPSE337M006R0100 (330µF/6V) have a rated maximum ESR of 0.1Ω; seven in parallel will lower the net output capacitor ESR to 0.014Ω. For low cost application, Sanyo MV-GX series of capacitors can be used with acceptable performance. The small size, low profile Sanyo OS-CON 4SP820M comes with extremely low ESR (typically 0.008Ω at room temperature). This is an excellent choice for output capacitor usage. However, due to the low ESR, it requires attention to frequency compensation. Refer to the Feedback Loop Compensation section for details. Feedback Loop Compensation The LTC1753 voltage feedback loop is compensated at the COMP pin, attached to the output node of the internal gm error amplifier. The feedback loop can generally be compensated properly with an RC + C network from COMP to GND as shown in Figure 7a. 1µF 6 SENSE C2 R2 VFB 11 R1 LTC1753 1753 F07a W UU LTC1753 APPLICATIO S I FOR ATIO The ESR of the output capacitor forms a zero at the frequency: fESR = 1 2π(ESR)(COUT) The compensation network at the error amplifier output is to provide enough phase margin at the 0dB crossover frequency for the overall closed-loop transfer function. The zero and pole from the compensation network are: 1 1 fZ = and fP = respectively. 2π(RC)(CC) 2π(RC)(C1) Figure 7b shows the Bode plot of the overall transfer function. The compensation value used in this design is based on the following criteria: fSW = 12fCO, fZ = fLC and fP = 5fCO. At the loop crossover frequency fCO, the attenuation due the LC filter and the input resistor divider is compensated by the gain of the PWM modulator and the gain of the error amplifier (gmERR)(RC). When low ESR output capacitors (Sanyo OS-CON) are used, the ESR zero can be high enough in frequency that it provides little phase boost at the loop crossover frequency. Therefore, inadequate phase margin is obtained for the system. This causes loop stability problems and fZ fSW = LTC1753 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY LOOP GAIN LOOP GAIN – 20dB/DECADE fP fLC fESR fCO FREQUENCY Figure 7b. Bode Plot of the LTC1753 Overall Transfer Function U poor load transient response despite the improvement in output voltage ripple. To resolve this problem, a small capacitor can be connected between the SENSE and VFB pins to create a polezero pair in the loop compensation. The zero location is prior to the pole location and thus, phase lead can be added to boost the phase margin at the loop crossover frequency. The pole and zero locations are located at: fZC2 = 1 1 and fPC2 = 2π(R2)(C2) 2π(R12)(C2) W UU where R12 is the parallel combination resistance of R1 and R2. Choose C2 so that the zero is located at a lower frequency compared to fCO and the pole location is high enough that the closed loop has enough phase margin for stability. Figure 7c shows the Bode plot using phase lead compensation around the LTC1753 internal resistor divider network. Although a mathematical approach to frequency compensation can be used, the added complication of input and/ or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final compensation values, or by obtaining the optimum loop fSW = LTC1753 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY fZ – 20dB/DECADE fCO fP fPC2 fLC fZC2 fESR 1753 F07b FREQUENCY 1753 F07c Figure 7c. Bode Plot of the LTC1753 Overall Transfer Function Using a Low ESR Output Capacitor 17 LTC1753 APPLICATIO S I FOR ATIO response using a network analyzer to find the actual loop poles and zeros. Table 5 shows the suggested compensation components for 5V input applications based on the inductor and output capacitor values. The values were calculated using multiple paralleled 330µF AVX TPS series surface mount tantalum capacitors as the output capacitor. The optimum component values might deviate from the suggested values slightly because of board layout and operating condition differences. Table 5. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 330µF AVX TPS Output Capacitors LO (µH) CO (µF) RC (kΩ) CC (µF) C1 (pF) 1 1 1 2.7 2.7 2.7 5.6 5.6 5.6 990 1980 4950 990 1980 4950 990 1980 4950 1.8 3.6 9.1 5.1 10 24 10 20 51 0.022 0.01 0.01 0.01 0.01 0.0047 0.01 0.0047 0.0033 680 330 120 220 120 47 120 56 22 An alternate output capacitor is the Sanyo MV-GX series. Using multiple parallel 1500µF Sanyo MV-GX capacitors for the output capacitor, Table 6 shows the suggested compensation component value for a 5V input application based on the inductor and output capacitor values. Table 6. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 1500µF Sanyo MV-GX Output Capacitors LO (µH) CO (µF) RC (kΩ) CC (µF) C1 (pF) 1 1 1 2.7 2.7 2.7 5.6 5.6 5.6 4500 6000 9000 4500 6000 9000 4500 6000 9000 4.3 5.6 8.2 11 15 22 24 30 47 0.022 0.015 0.01 0.01 0.01 0.01 0.01 0.0047 0.0047 270 220 150 100 82 56 56 39 27 18 U Table 7 shows the suggested compensation component value for a 5V application based on the Sanyo OS-CON 4SP820M low ESR output capacitors Table 7. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 820µF Sanyo OS-CON 4SP820M Output Capacitors LO (µH) CO (µF) RC (kΩ) CC (µF) C1 (pF) C2 (pF) 1 1 1 2.7 2.7 2.7 5.6 5.6 5.6 1640 2460 4100 1640 2460 4100 1640 2460 4100 5.6 9.1 15 16 24 39 33 47 82 0.01 0.0047 0.0047 0.0047 0.0033 0.0022 0.0033 0.0022 0.0022 220 150 82 82 56 33 39 27 15 270 270 270 270 270 270 270 270 270 W UU Remote Sense Considerations In some installations such as Intel Slot 2 designs, the regulator is by necessity a relatively long distance from the load. It is desirable in these instances to connect the regulator sense connection at the load rather than directly at the regulator output. This forces the supply voltage to be regulated at the load which, after all, is the desired point to control. In most cases no problems will be encountered as a result of doing this. However, care must be exercised if the power path is long or the capacitance at the load is very large. The power distribution path has some finite amount of inductance. There will also be a significant amount of capacitance at the load as the local bypass. These two circuit elements constitute a second order, lowpass filter and the SENSE lead connects to the output of this filter. As is true for any LC filter, there is 180° of phase shift at a frequency beyond the double pole. If the resonant frequency of the filter falls below the regulator’s feedback loop crossover frequency, the loop will likely oscillate. There are a couple of measures that may be taken to alleviate this problem. The first is to minimize the inductance of the power path. Therefore, it is desirable to make the power trace as wide as possible and as short as LTC1753 APPLICATIO S I FOR ATIO possible. It should also be located as close as possible above (or below) the power ground plane. Some of the phase shift problem can be solved by taking the AC feedback locally at the regulator output while still taking the DC feedback at the point of load. This permits accurate DC regulation while still maintaining reasonable phase margin. This is done by connecting the top of phase lead capacitor, C2, locally at the regulator output while connecting the SENSE pin to the load. The corner frequency 1/(2π • R2 • C2) must be significantly less than the resonant frequency of the parasitic inductance and the output capacitance 1/(2π • √LDIST • CLOAD). Certain board layouts may require RC2, a small series resistor, to decrease the slew rate of the feedforward path. In general, an empirical approach to compensating this type of loop will be best since it will be very difficult to estimate the parasitic inductance of the power path analytically. It should be noted that if the circuit can have a wide range of output capacitance, this can be dangerous technique to employ since the double-pole frequency will move as the load capacitance changes. Be sure to verify stability with all possible combinations of output capacitance. Q1 LO LDIST + Q2 COUT 1µF + CLOAD 6 SENSE 1µF RC2 C2 R2 VFB 11 R1 LTC1753 COMP 10 RC CC C1 ERR DAC 1753 F08 Figure 8. Feedback Connections for Remote Sense Applications U VID0 to VID4, PWRGD and FAULT The digital inputs (VID0 to VID4) program the internal DAC which in turn controls the output voltage. These digital input controls are intended to be static and are not designed for high speed switching. Forcing VOUT to step from a high to a low voltage by changing the VIDn pins quickly can cause FAULT to trip. Figure 9 shows the relationship between the VOUT voltage, PWRGD and FAULT. To prevent PWRGD from interrupting the CPU unnecessarily, the LTC1753 has a built-in tPWRBAD delay to prevent noise at the SENSE pin from toggling PWRGD. The internal time delay is designed to take about 500µs for PWRGD to go low and 1ms for it to recover. Once PWRGD goes low, the internal circuitry watches for the output voltage to exceed 113% of the rated voltage. If this happens, FAULT will be triggered. Once FAULT is triggered, G1 and G2 will be forced low immediately and the LTC1753 will remain in this state until VCC power supply is recycled or OUTEN is toggled. 13% VOUT 3% RATED VOUT LOAD – 3% t PWRBAD PWRGD t PWRGD t FAULT FAULT 1753 F09 W UU – + Figure 9. PWRGD and FAULT 19 LTC1753 APPLICATIO S I FOR ATIO LAYOUT CONSIDERATIONS When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1753. These items are also illustrated graphically in the layout diagram of Figure 10. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10A. 1. In general, layout should begin with the location of the power devices. Be sure to orient the power circuitry so that a clean power flow path is achieved. Conductor widths should be maximized and lengths minimized. After you are satisfied with the power path, the control circuitry should be laid out. It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. The GND and SGND pins should be shorted directly at the LTC1753. This helps to minimize internal ground disturbances in the LTC1753 and prevents differences in ground potential from disrupting internal circuit operation. This connection should then tie into the ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capacitors. This is not always practical, however, due to physical constraints. Another reasonably good point to make this connection is between the output capacitors and the source connection of the low side FET Q2. Do not tie this single point ground in the trace run between the low side FET source and the input capacitor ground, as this area of the ground plane will be very noisy. 20 U 3. The small signal resistors and capacitors for frequency compensation and soft-start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. Do not connect these parts to the ground plane! 4. The VCC and PVCC decoupling capacitors should be as close to the LTC1753 as possible. The 10µF bypass capacitors shown at VCC and PVCC will help provide optimum regulation performance. 5. The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET. An additional 1µF ceramic capacitor between VIN and power ground is recommended. 6. The SENSE and VFB pins are very sensitive to pickup from the switching node. Care should be taken to isolate SENSE and VFB from possible capacitive coupling to the inductor switching signal. A 1µF is required between the SENSE pin and the SGND pin next to the LTC1753. If PWRGD or FAULT are in the wrong logic state for nonobvious reasons, check the layout of the SENSE and VFB traces carefully. The 1µF capacitor should be mounted as close to the SENSE pin as possible. In addition, if feedforward compensation is in use, a resistor in series with the feedforward capacitor might be required. Finally, a low value resistor may be placed between the output voltage and the SENSE pin (and the 1µF capacitor). This RC will help filter high frequency spikes. 7. OUTEN is a high impedance input and should be externally pulled up to a logic HIGH for normal operation. 8. Kelvin sense IMAX and IFB at Q1’s drain and source pins. W UU LTC1753 APPLICATIO S I FOR ATIO VIN Q1 LO VOUT PVCC 10µF 1 2 0.1µF 3 G2 PVCC GND VID1 VID2 5 6 BOLD LINES INDICATE HIGH CURRENT PATHS = GROUND PLANE RIMAX RIFB 7 8 9 10 CSS C1 RC CC VCC SENSE IMAX IFB SS COMP VID3 VID4 PWRGD FAULT VFB LTC1753 G1 20 19 18 17 16 15 14 13 12 1753 F10 + COUT + + CIN Q2 Figure 10. LTC1753 Layout Diagram U + OUTEN VID0 VID0 VID1 5.6k VID2 5.6k VID3 VID4 10µF 0.1µF 4 SGND 11 C2 1µF W UU 21 LTC1753 PACKAGE DESCRIPTIO U Dimension in inches (millimeters) unless otherwise noted. G Package 20-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 7.07 – 7.33* (0.278 – 0.289) 20 19 18 17 16 15 14 13 12 11 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 0 ° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) 0.65 (0.0256) BSC NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.25 – 0.38 (0.010 – 0.015) 0.05 – 0.21 (0.002 – 0.008) G20 SSOP 1098 22 LTC1753 PACKAGE DESCRIPTIO U Dimension in inches (millimeters) unless otherwise noted. SW Package 20-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 NOTE 1 0.394 – 0.419 (10.007 – 10.643) 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 1 0.093 – 0.104 (2.362 – 2.642) 2 3 4 5 6 7 8 9 10 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) S20 (WIDE) 1098 NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1753 TYPICAL APPLICATIO 5.6k CPU 5 VID0 TO VID4 5V 1.8k OUTEN LTC1753 DALE NTHS-1206N02 MOUNT THERMISTER IN CLOSE THERMAL PROXIMITY TO Q1 C1 150pF Figure 11. Single Supply LTC1753 5V to 1.3V-3.5V Application with Thermal Monitor RELATED PARTS PART NUMBER DESCRIPTION LTC1530 LTC1628 LTC1553L LT1585-1.5 LTC1629 LTC1703 LTC1706-81 LTC1709 LTC1735 LTC1772 LTC1873 LTC1929 High Power Synchronous Step-Down Controller Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor Fixed 1.5V, 4.6A and 5A Low Dropout, Fast Response GTL+ Regulators PolyPhaseTM High Efficiency Controller 2-Phase, Dual Synchronous Controller with VID 5-Bit VID Programmer High Efficiency, Synchronous Step-Down Switching Regulator with 5-Bit VID High Efficiency Low Noise Synchronous Step-Down Switching Regulator SOT-23 Step-Down Controller Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID 2-Phase, High Efficiency, Synchronous Step-Down Switching Regulator COMMENTS SO-8 with Current Limit, No RSENSETM Saves Space, Fixed Frequency Ideal for 5V to 3.3V or Lower Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V ≤ VIN ≤ 36V DAC Code Conforms to the Intel Pentium II Processor VRM8.2 DC/DC Converter Specification GTL+ Power Supplies Expandable Up to 12 Phases, 28-Lead SSOP, Up to 200A Mobile VID Code, Each Output Up to 15A, VIN = 5V for I/O and Core Desktop Pentium III Processors, VIN ≤ 7V Current Mode, VIN to 36V, IOUT Up to 42A Drives Synchronous N-Channel FETs, VIN ≤ 36V 100% Duty Cycle, Up to 4A, 2.2V to 9.8V VIN Desktop VID Codes, IOUT Up to 25A on Each Channel, 28-Lead SSOP Current Mode Ensures Accurate Current Sensing, VIN Up to 36V, IOUT Up to 42A, 28-Lead SSOP No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U VIN 5V 0.1µF 5.6k 0.1µF PWRGD FAULT IFB G2 VFB COMP RC 15k CC 4700pF CSS 0.1µF 1µF SS SGND GND SENSE 270pF * SILICONIX Si4410 ** SANYO 10MV1200GX † PANASONIC ETQP 6FIR3LFA †† SANYO 6MV2700GX VCC IMAX PVCC G1 20Ω LO† Q1* 1.3µH 14A COUT†† Q2* 2700µF ×5 + 10µF 820Ω 1N5817 + CIN** 1200µF ×3 + VOUT 14A 1753 F11 1753f LT/TP 0400 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 1998