LTC1771I

Final Electrical Specifications LTC1771 Low Quiescent Current High Efficiency Step-Down DC/DC Controller FEATURES s s s s s s s s s DESCRIPTIO February 2000 s s s s Very Low Standby Current: 10µA Available in Space-Saving 8-Lead MSOP Package High Output Currents Wide VIN Range: 2.8V to 20V Operation VOUT Range: 1.23V to 18V High Efficiency: Over 93% Possible ± 2% Output Accuracy Very Low Dropout Operation: 100% Duty Cycle Current Mode Operation for Excellent Line and Load Transient Response Defeatable Burst ModeTM Operation Short-Circuit Protected Optional Programmable Soft-Start Micropower Shutdown: IQ = 2µA The LTC®1771 is a high efficiency current mode stepdown DC/DC controller that draws as little as 10µA DC supply current to regulate the output at no load while maintaining high efficiency for loads up to several amps. The LTC1771 drives an external P-channel power MOSFET using a current mode, constant off-time architecture. An external sense resistor is used to program the operating current level. Current mode control provides short-circuit protection, excellent transient response and controlled start-up behavior. Burst Mode operation enables the LTC1771 to maintain high efficiency down to extremely low currents. Shutdown mode further reduces the supply current to a mere 2µA. For low noise applications, Burst Mode operation can be easily disabled with the MODE pin. Wide input supply range of 2.8V to 18V (20V maximum) and 100% duty cycle operation for low dropout make the LTC1771 ideal for a wide variety of battery-powered applications where maximizing battery life is important. The LTC1771’s availability in both 8-lead MSOP and SO packages provides for a minimum area solution. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. APPLICATIO S s s s s s s Cellular Telephones and Wireless Modems 1- to 4-Cell Lithium-Ion-Powered Applications Portable Instruments Battery-Powered Equipment Battery Chargers Scanners TYPICAL APPLICATIO VIN 4.5V TO 18V RSENSE 0.05Ω VIN RUN/SS CSS 0.01µF RC 10k CC 22OpF SENSE PGATE M1 Si6447DQ 10µF 25V CER 100 VIN = 5V 90 EFFICIENCY (%) ITH LTC1771 VFB MODE GND VIN R2 1.64M 1% L1 15µH UPS5817 80 70 60 50 + COUT 150µF 6.3V VOUT 3.3V 2A R1 1M 1% 5pF 1771 F01 VOUT = 3.3V RSENSE = 0.05Ω 40 10 0.1 1 100 1000 LOAD CURRENT (mA) Figure 1. High Efficiency Step-Down Converter Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U U LTC1771 Efficiency VIN = 10V VIN = 15V 10000 1771 F01b 1 LTC1771 ABSOLUTE AXI U RATI GS (Note 1) Junction Temperature (Note 2) ............................ 125°C Operating Temperature Range (Note 3) LTC1771E ......................................... – 40°C to 85°C LTC1771I ......................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C Input Supply Voltage (VIN)........................ – 0.3V to 20V Peak Driver Output Current < 10µs (PGATE) ............. 1A RUN/SS Voltage ........................... – 0.3V to (VIN + 0.3V) MODE Voltage .......................................... – 0.3V to 20V ITH, VFB Voltage .......................................... – 0.3V to 5V SENSE Voltage (VIN > 12V)...(VIN – 12V) to (VIN + 0.3V) SENSE Voltage (VIN ≤ 12V) .......... – 0.3V to (VIN + 0.3V) PACKAGE/ORDER I FOR ATIO TOP VIEW RUN/SS ITH VFB GND 1 2 3 4 8 7 6 5 MODE SENSE VIN PGATE ORDER PART NUMBER LTC1771EMS8 MS8 PART MARKING LTKD RUN/SS 1 ITH 2 VFB 3 GND 4 MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 150°C/ W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 10V, VRUN = open unless otherwise specified. SYMBOL VFB IFB ISUPPLY ∆VLINEREG ∆VLOADREG IQ PARAMETER Feedback Voltage Feedback Current No-Load Supply Current Reference Voltage Line Regulation Output Voltage Load Regulation Input DC Supply Current Active Mode (PGATE = 0V) Sleep Mode (Note 6) Shutdown Short Circuit Maximum Current Sense Threshold Minimum Current Sense Threshold Sleep Current Sense Threshold Switch Off Time Mode Pin Threshold CONDITIONS (Note 5) (Note 5) VIN = 10V, ILOAD = 0 (Note 6) VIN = 5V to 15V (Note 5) ITH = 0.5V to 2V, Burst Disabled (Note 5) (Note 4) VIN = 2.8V to 18V VIN = 2.8V to 18V, VFB = 1.5V VIN = 2.8V to 18V, VRUN = 0V VIN = 2.8V to 18V, VFB = 0V VFB = VREF – 20mV VFB = VREF + 10mV, Burst Disabled ITH = 1V VFB at Regulated Value VFB = 0V VMODE Rising q q q q q q ∆VSENSE(MAX) ∆VSENSE(MIN) ∆VSENSE(SLEEP) t OFF VMODE 2 U U W WW U W TOP VIEW 8 7 6 5 MODE SENSE VIN PGATE ORDER PART NUMBER LTC1771ES8 LTC1771IS8 S8 PART MARKING 1771 1771I S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 110°C/ W MIN 1.205 TYP 1.230 1 10 0.003 0.25 150 9 2 175 MAX 1.255 10 0.03 1 235 15 6 275 180 UNITS V nA µA %/V % µA µA µA µA mV mV mV µs µs 110 140 – 25 50 3.5 70 0.5 1.3 2 V LTC1771 ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 10V, VRUN = open unless otherwise specified. SYMBOL VRUN/SS IRUN PGATE t r, tf PARAMETER RUN/SS Pin Threshold Source Current PGATE Transition Time (Note 7) Rise Time Fall Time CONDITIONS VRUN/SS Rising VRUN = 0V, VIN = 2.8V to 18V CLOAD = 2000pF CLOAD = 2000pF q MIN 0.5 0.3 TYP 1.0 1 80 90 MAX 2 3 UNITS V µA ns ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1771S8: TJ = TA + (PD)(110°C/W) LTC1771MS8: TJ = TA + (PD)(150°C/W) Note 3: The LTC1771E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC1771I is guaranteed and tested over the – 40°C to 85°C operating temperature range. Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: The LTC1771 is tested in a feedback loop that servos VFB to the balance point for the error amplifier (VITH = 1.23V). Note 6: No-load supply current consists of sleep mode current (9µA typical) plus a small switching component necessary to overcome Schottky diode leakage and feedback resistor current. Note 7: tr and tf measured at 10% to 90% levels. PI FU CTIO S RUN/SS (Pin 1): The voltage level on this pin controls shutdown/run mode (ground = shutdown, open/high = run). Connecting an external capacitor to this pin provides soft-start. ITH (Pin 2): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 3V. VFB (Pin 3): Feedback of Output Voltage for Comparison to Internal 1.23V Reference. An external resistive divider across the output is returned to this pin. GND (Pin 4): Ground Pin. PGATE (Pin 5): High Current Gate Driver for External P-Channel MOSFET Switch. Voltage swing is from ground to VIN. VIN (Pin 6): Main Input Voltage Supply Pin. SENSE (Pin 7): Current Sense Input for Monitoring Switch Current. Maximum switch current and Burst Mode threshold is programmed with an external resistor between SENSE and VIN. MODE (Pin 8): Burst Mode Enable/Disable Pin. Connecting this pin to VIN (or above 2V) enables Burst Mode operation, while connecting this pin to ground disables Burst Mode operation. Do not leave floating. U U U 3 LTC1771 FUNCTIONAL BLOCK DIAGRA VIN 1µA RUN/SS 1 MODE 8 (BURST ENABLE) 10% CURRENT 1.23V CSS + – ON EA VOUT 10% CURRENT SLEEP * ITH 2 RC CC GND 4 1V 2V 1V – + B READY VIN BLANKING MODE ON TRIGGER 1-SHOT STRETCH VFB 3 L 3.5µs VOUT *OPTIONAL FOR FOLDBACK CURRENT LIMITING 4 + ON C – SOFT-START W VIN 6 READY 1.23V REFERENCE 22k RSENSE U U + VIN CIN SENSE 7 250k SW 5 + COUT 1771 BD LTC1771 OPERATIO Main Control Loop The LTC1771 uses a constant off-time, current mode step-down architecture. During normal operation, the P-channel MOSFET is turned on at the beginning of each cycle and turned off when the current comparator C triggers the 1-shot timer. The external MOSFET switch stays off for the 3.5µs 1-shot duration and then turns back on again to begin a new cycle. The peak inductor current at which C triggers the 1-shot is controlled by the voltage on Pin 3 (ITH), the output of the error amplifier EA. An external resistive divider connected between VOUT and ground allows EA to receive an output feedback voltage VFB. When the load current increases, it causes a slight decrease in VFB relative to the 1.23V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. The main control loop is shut down by pulling Pin 1 (RUN/SS) low. Releasing RUN/SS allows an internal 1µA current source to charge soft-start capacitor CSS. When CSS reaches 1V, the main control loop is enabled with the ITH voltage clamped at approximately 40% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. Burst Mode Operation The LTC1771 provides outstanding low current efficiency and ultralow no-load supply current by using Burst Mode operation when the MODE pin is pulled above 2V. During Burst Mode operation, short burst cycles of normal switching are followed by a longer idle period with the switch off and the load current is supplied by the output capacitor. During this idle period, only the minimum required circuitry—1.23V reference and error amp—are left on, and the supply current is reduced to 9µA. At no load, the output capacitor is still discharged very slowly by leakage current in the Schottky diode and feedback resistor current resulting in very low frequency burst cycles that add a few more microamps to the supply current. U (Refer to Functional Block Diagram) Burst Mode operation is provided by clamping the minimum ITH voltage at 1V which represents about 25% of maximum load current. If the load falls below this level, i.e. the ITH voltage tries to fall below 1V, the burst comparator B switches state signaling the LTC1771 to enter sleep mode. During this time, EA is reduced to 10% of its normal operating current and the external compensation capacitor is disconnected and clamped to 1V so that the EA can drive its output with the lower available current. As the load discharges the output capacitor, the internal ITH voltage increases. When it exceeds 1V the burst comparator exits sleep mode, reconnects the external compensation components to the error amplifier output, and returns EA to full power along with the other necessary circuitry. This scheme (patent pending) allows the EA to be reduced to such a low operating current during sleep mode without adding unacceptable delay to wake up the LTC1771 due to the compensation capacitor on ITH required for stability in normal operation. Burst Mode operation can be disabled by pulling the MODE pin to ground. In this mode of operation, the burst comparator B is disabled and the ITH voltage allowed to go all the way to 0V. The load can now be reduced to about 1% of maximum load before the loop skips cycles to maintain regulation. This mode provides a low noise output spectrum, useful for reducing both audio and RF interference, at the expense of reduced efficiency at light loads. Off-Time The off-time duration is 3.5µs when the feedback voltage is close to the reference voltage; however, as the feedback voltage drops, the off-time lengthens and reaches a maximum value of about 70µs when VFB is zero. This ensures that the inductor current has enough time to decay when the reverse voltage across the inductor is low such as during short circuit, thus protecting the MOSFET and inductor. 5 LTC1771 APPLICATIO S I FOR ATIO The basic LTC1771 application circuit is shown in Figure 1 on the first page. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, L can be chosen. Next, the MOSFET and D1 are selected. The inductor is chosen based largely on the desired amount of ripple current and for Burst Mode operation. Finally CIN is selected for its ability to handle the required RMS input current and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specifications. RSENSE Selection RSENSE is chosen based on the required output current. The LTC1771 current comparator has a maximum threshold of 140mV/RSENSE. The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak less half the peak-to-peak ripple current ∆IL. For best performance when Burst Mode operation is enabled, choose ∆IL equal to 35% of peak current. Allowing a margin for variations in the LTC1771 and external components gives the following equation for choosing RSENSE: RSENSE = 100mV/IMAX At higher supply voltages, the peak currents may be slightly higher due to overshoot from current comparator delay and can be predicted from the second term in the following equation: IPEAK V –V  0.14 ≅ + 0.5  IN OUT  RSENSE  L(µH)  1/ 2 Inductor Value Selection Once RSENSE is known, the inductor value can be determined. The inductance value has a direct effect on ripple current. The ripple current decreases with higher inductance and increases with higher VOUT. The ripple current during continuous mode operation is set by the off-time and inductance to be: V +V  ∆IL(CONT) = t OFF  OUT D  L   Kool Mµ is a registered trademark of Magnetics, Inc. 6 U where tOFF = 3.5µs. However, the ripple current at low loads during Burst Mode operation is: ∆IL(BURST) ≈ 35% of IPEAK ≈ 0.05/RSENSE For best efficiency when Burst Mode operation is enabled, choose: ∆IL(CONT) ≤ ∆IL(BURST) so that the inductor current is continuous during the burst periods. This sets a minimum inductor value of: LMIN = (70µH)(VOUT + VD)(RSENSE) When burst is disabled, ripple currents less than ∆IL(BURST) can be achieved by choosing L > LMIN. Lower ripple current reduces output voltage ripple and core losses, but too low of ripple current will adversely effect efficiency. Inductor Core Selection Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent increase in voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. W UU LTC1771 APPLICATIO S I FOR ATIO Power MOSFET Selection An external P-channel power MOSFET must be selected for use with the LTC1771. The main selection criteria for the power MOSFET are the threshold voltage VGS(TH) and the “on” resistance RDS(ON), reverse transfer capacitance and total gate charge. Since the LTC1771 can operate down to input voltages as low as 2.8V, a sublogic level threshold MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required for applications that work close to this voltage. When these MOSFETs are used, make sure that the input supply to the LTC1771 is less than the absolute maximum VGS rating (typically 12V), as the MOSFET gate will see the full supply voltage. The required RDS(ON) of the MOSFET is governed by its allowable power dissipation. For applications that may operate the LTC1771 in dropout, i.e. 100% duty cycle, at its worst case the required RDS(ON) is given by: RDS(ON) = ( PP IOUT (MAX) ) 2 (1+ δP ) where PP is the allowable power dissipation and δP is the temperature dependency of RDS(ON). (1 + δP) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.005/°C can be used as an approximation for low voltage MOSFETs. In applications where the maximum duty cycle is less than 100% and the LTC1771 is in continuous mode, the RDS(ON) is governed by: RDS(ON) = DC = (DC)IOUT2 (1+ δP ) VOUT + VD VIN + VD PP where DC is the maximum operating duty cycle of the LTC1771. Catch Diode Selection The catch diode carries load current during the off-time. The average diode current is therefore dependent on the P-channel switch duty cycle. At high input voltages the U diode conducts most of the time. As VIN approaches VOUT the diode conducts only a small fraction of the time. The most stressful condition for the diode is when the output is short-circuited. Under this condition, the diode must safely handle IPEAK at close to 100% duty cycle. To maximize both low and high current efficiencies, a fast switching diode with low forward drop and low reverse leakage should be used. Low reverse leakage current is critical to maximize low current efficiency since the leakage can potentially exceed the magnitude of the LTC1771 supply current. Low forward drop is critical for high current efficiency since loss is proportional to forward drop. The effect of reverse leakage and forward drop on no- load supply current and efficiency for various Schottky diodes is shown in Table 1. As can be seen, these are conflicting parameters and the user must weigh the importance of each spec in choosing the best diode for the application. Table 1. Effect of Catch Diode on Performance DIODE MBR0540 UPS5817 MBR0520 MBRS120T3 MBRM120LT3 MBRS320 LEAKAGE NO-LOAD EFFICIENCY (VR = 3.3V) VF @ 1A SUPPLY CURRENT AT 10V/1A 0.25µA 2.8µA 3.7µA 4.4µA 8.3µA 19.7µA 0.50V 0.41V 0.36V 0.43V 0.32V 0.29V 10.4µA 11.8µA 12.2µA 12.2µA 14.0µA 20.0µA 86.3% 88.2% 88.4% 87.9% 89.4% 89.8% W UU CIN and COUT Selection At higher load currents, when the inductor current is continuous, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum capacitor current is given by: CIN required IRMS = IMAX VOUT (VIN − VOUT ) VIN [ ]1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s 7 LTC1771 APPLICATIO S I FOR ATIO ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Do not underspecify this component. An additional 0.1µF ceramic capacitor is also helpful on VIN for high frequency decoupling. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) in continuous mode is approximated by: ∆VOUT  1 ≈ IRIPPLE  ESR +  8 fCOUT   where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. For output ripple less than 100mV, assure COUT required ESR is tON(MIN)  VIN − VOUT  where tOFF = 3.5µs and tON(MIN) is generally about 0.5µs for the LTC1771. If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1771 will remain in Burst Mode operation even at high load currents. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. Mode Pin Burst Mode operation is disabled by pulling MODE (Pin 8) below 0.5V. Disabling Burst Mode operation provides a low noise output spectrum, useful for reducing both audio and RF interference. It does this by keeping the frequency constant (for fixed VIN) down to much lower load current (1% to 2% of IMAX) and reducing the amount of output voltage and current ripple at light loads. When Burst Mode operation is disabled, efficiency is reduced at light loads and no load supply current increases to 175µA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1771. These items are also illustrated graphically in the layout diagram of Figure 3. Check the following in your layout: 10 U 1. Is the Schottky diode closely connected to the drain of the external MOSFET and the input cap ground? 2. Is the 0.1µF input decoupling capacitor closely connected between VIN (Pin 6) and ground (Pin 4)? This capacitor carries the high frequency peak currents. 3. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1 and R2 must be connected between the (+) plate of COUT and signal ground. Locate the feedback resistors right next to the LTC1771. The VFB line should not be routed close to any nodes with high slew rates. 4. Is the 1000pF decoupling capacitor for the current sense resistor connected as close as possible to Pins 6 and 7? Ensure accurate current sensing with Kelvin connections to the sense resistor. 5. Is the (+) plate of CIN closely connected to the sense resistor ? This capacitor provides the AC current to the MOSFET. 6. Are the signal and power grounds segregated? The signal ground consists of the (–) plate of COUT, Pin 4 of the LTC1771 and the resistive divider. The power ground consists of the Schottky diode anode and the (–) plate of CIN which should have as short lead lengths as possible. 7. Keep the switching node (SW) and the gate node (PGATE) away from sensitive small signal nodes, especially the voltage sensing feedback pin (VFB), and minimize their PC trace area. 8. High impedance nodes such as ITH and VFB are very sensitive to leakage paths on the PC board due to stray flux, solder, epoxy, etc. Make sure PC board is clean. Water-soluble solder flux can be especially leaky if not cleaned properly. Leakage on ITH will manifest itself as excessive output ripple during Burst Mode operation. If the problem persists, adding a 10M resistor from Pin 2 to ground should eliminate the problem. W UU LTC1771 APPLICATIO S I FOR ATIO Design Example As a design example, assume VIN = 10V (nominal), VIN = 15V(MAX), VOUT = 3.3V, and IMAX = 2A. With this information, we can easily calculate all the important components. RSENSE = 100mV/2A = 0.05Ω To optimize low current efficiency, MODE pin is tied to VIN to enable Burst Mode operation, thus the minimum inductance necessary is: LMIN = 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH 15µH is chosen for the application.  3.3V + 0.5V  ∆IL = 3.5µs   = 0.89A  15µH  For the feedback resistors, choose R1 = 1M to minimize supply current. R2 can then be calculated to be: R2 = (VOUT/1.23 – 1) • R1 = 1.68M Assume that the MOSFET dissipation is to be limited to PP = 0.25W. If TA = 70°C and the thermal resistance of the MOSFET is 83°C/W, then the junction temperatures will be 91°C and δP = 0.33. The required RDS(ON) for the MOSFET can now be calculated: CSS 1 CITH RITH 2 3 4 RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 8 7 6 5 MODE R1 R2 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 3. LTC1771 Layout Diagram + CFF U P - Channel RDS(ON) = 0.25W  3.3V + 0.5V    2A  10 V + 0.5V  = 0.130Ω W UU ( ) (1.33) 2 Since the gate of the MOSFET will see the full input voltage, a MOSFET must be selected whose VGS(MAX) > 15V. A P-channel MOSFET that meets both the VGS(MAX) and RDS(ON) requirement is the Si6447DQ. The most stringent requirement for the Schottky diode occurs when VOUT = 0V (i.e., short circuit) at maximum VIN. In this case the worst-case dissipation rises to:  VIN  PD = ISC(AVG) (VD)   VIN + VD  With a 0.05Ω sense resistor ISC(AVG) = 2A will result, increasing the 0.5V Schottky diode dissipation to 1W. CIN is chosen for a RMS current rating of at least 1A at temperature. COUT is chosen with an ESR of 0.05Ω for low output ripple. The output voltage ripple due to ESR is approximately: VORIPPLE ≈ (RESR)(∆IL) = 0.05Ω (0.89AP-P) = 45mVP-P + CIN D1 Q1 0.1µF COUT L VOUT 1771 F03 11 LTC1771 TYPICAL APPLICATIO S 3.3V to 2.5V/1A Regulator with Burst Mode Operation Enabled 0.01µF 1 220pF 10k 2 3 4 RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 5 Si3443DV 1M 1% 1.02M 1% 5pF RSENSE 0.1Ω 22µH 8 7 6 1000pF VIN 3.3V TO 12V VOUT 2.5V 1A 0.01µF 1 220pF 10k 2 3 4 RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 5 RSENSE Si6447DQ 0.05Ω 22µH 8 7 6 1000pF VIN 5.5V TO 18V VOUT 5V 2A 1M 1% 12 U + CIN 22µF 25V + UPS5817 COUT 150µF 6.3V 1771 TA01 5V/2A Regulator with Burst Mode Operation Disabled + 3.09M 1% 5pF CIN 22µF 25V + UPS5817 COUT 150µF 6.3V 1771 TA04 LTC1771 TYPICAL APPLICATIO S 0.01µF 1 220pF 10k 2 3 4 RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 5 RSENSE 0.05Ω 15µH 8 7 6 1000pF MODE 1M 1% 0.01µF 1 220pF 10k 2 3 4 1M 1% RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 8.66M 1% 5pF 5 Si6435DQ RSENSE 0.025Ω 8 7 6 1000pF VIN 5V TO 18V MODE U Low Dropout Single Cell Lithium-Ion to 3V + Si3443DV 1.43M 1% 5pF UPS5817 CIN 22µF 25V Li-Ion 3.3V TO 4.2V VOUT 3V 2A + COUT 150µF 6.3V 1771 TA02 12V/1A Zeta Converter + CIN 22µF 25V • 47µH • 47µH 22µF 20V + UPS5817 COUT 150µF 20V 1771 TA05 VOUT 12V 1A + 13 LTC1771 TYPICAL APPLICATIONS 0.01µF 1 220pF 10k 2 3 4 RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 1.02M 1% 5pF U1 56 7 8 22µH 1N4148 ×2 VOUT 2.5V 1A 5 RSENSE 0.1Ω 43 2 8 7 6 1000pF VIN 2.8V TO 12V MODE 1M 1% U1: INTERNATIONAL RECTIFIER FETKY TM IRF7422D2 0.01µF 1 220pF 10k 2 3 4 RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 5 Si6447DQ 1M 1% 4.69M 1% 5pF RSENSE 0.1Ω 47µH 8 7 6 1000pF VIN 8V CIN TO 18V 22µF 25V UPS5817 VOUT 4-NiCd 1A COUT 100µF 10V 1771 TA07 14 U 2.5V/1A Regulator with Foldback Current Limit + 1 CIN 22µF 25V ITH + COUT 150µF 6.3V 1771 TA06 4-NiCd Battery Charger MODE + + UPS5817 LTC1771 PACKAGE DESCRIPTIO 0.007 (0.18) 0.021 ± 0.006 (0.53 ± 0.015) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 (0.406 – 1.270) U Dimension in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 8 76 5 0.193 ± 0.006 (4.90 ± 0.15) 0.118 ± 0.004** (3.00 ± 0.102) 1 0.040 ± 0.006 (1.02 ± 0.15) 0° – 6° TYP SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) BSC 23 4 0.034 ± 0.004 (0.86 ± 0.102) 0.006 ± 0.004 (0.15 ± 0.102) MSOP (MS8) 1098 S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC SO8 1298 15 LTC1771 TYPICAL APPLICATIO 0.01µF 1 220pF 10k 2 3 4 1M 1% RUN/SS ITH VFB GND MODE SENSE LTC1771 VIN PGATE 3.09M 1% 5pF 5 Si3443DV 8 7 6 1000pF MODE RELATED PARTS PART NUMBER LTC1147 Series LTC1174/LTC1174-3.3/LTC1174-5 LTC1265 LTC1474/LTC1475 LTC1574/LTC1574-3.3/LTC1574-5 LTC1622 LTC1624 LT®1761 Series LT1763 Series LTC1772 DESCRIPTION High Efficiency Step-Down Switching Regulator Controllers High Efficiency Step-Down and Inverting DC/DC Converters 1.2A High Efficiency Step-Down DC/DC Converter Low Quiscent Current Step-Down Regulators High Efficiency Step-Down DC/DC Converters with Internal Schottky Diode Low Input Voltage Step-Down DC/DC Controller High Efficiency SO-8 N-Channel Switching Regulator Controller 100mA, Low Noise, LDO Micropower Regulators in SOT-23 500mA, Low Noise, LDO Micropower Regulators Constant Frequency Step-Down DC/DC Controller COMMENTS 100% DC, 3.5V ≤ VIN ≤ 16V Selectable IPEAK = 300mA or 600mA Burst Mode Operation, Internal MOSFET Monolithic, IQ = 10µA, 400mA, MS8 LTC1174 with Internal Schottky Diode Constant Frequency, 2V to 10V VIN, MS8 95% DC, 3.5V to 36V VIN 20µA Quiescent Current, 20µVRMS Noise 30µA Quiescent Current, 20µVRMS Noise SOT-23, 2.2V to 9.8V VIN 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U 5V/1A Zeta Converter VIN (V) ILOAD(MAX) (A) 2.8 0.8 3.3 1.1 5 1.7 7.5 2.3 10 2.7 12 2.9 VIN 2.8V TO 12V RSENSE 0.025Ω + CIN 22µF 25V • 22µH • 22µH 22µF 10V + UPS5817 COUT 150µF 6.3V 1771 TA03 VOUT 5V 1A + 1771i LT/TP 0200 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2000