LTC1851CFW

LTC1850/LTC1851 8-Channel, 10-Bit/12-Bit, 1.25Msps Sampling ADCs DESCRIPTIO The 10-bit LTC®1850 and 12-bit LTC1851 are complete 8-channel data acquisition systems. They include a flexible 8-channel multiplexer, a 1.25Msps successive approximation analog-to-digital converter with sample-and-hold, an internal 2.5V reference and reference buffer amplifier, and a parallel output interface. The multiplexer can be configured for single-ended or differential inputs, two gain ranges and unipolar or bipolar operation. The ADCs have a scan mode that will repeatedly cycle through all 8 multiplexer channels and can also be programmed with a sequence of up to 16 addresses and configurations that can be scanned in succession. The sequence memory can also be read back. The reference and buffer amplifier provide pin strappable ranges of 4.096V, 2.5V and 2.048V. The parallel output includes the 10-bit or 12-bit conversion result plus the 4-bit multiplexer address. The digital outputs are powered from a separate supply allowing for easy interface to 3V digital logic. Typical power consumption is 40mW at 1.25Msps from a single 5V supply. , LTC and LT are registered trademarks of Linear Technology Corporation. FEATURES s s s s s s s s s s s s Flexible 8-Channel Multiplexer Single-Ended or Differential Inputs Two Gain Ranges Plus Unipolar and Bipolar Operation 1.25Msps Sampling Rate Single 5V Supply and 40mW Power Dissipation Scan Mode and Programmable Sequencer Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851 True Differential Inputs Reject Common Mode Noise Internal 2.5V Reference Parallel Output Includes MUX Address Easy Interface to 3V Logic Nap and Sleep Shutdown Modes APPLICATIO S s s s s s s High Speed Data Acquisition Test and Measurement Imaging Systems Telecommunications Industrial Process Control Spectrum Analysis BLOCK DIAGRA CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 2.5V REFERENCE 8-CHANNEL MULTIPLEXER LTC1851 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER INTERNAL CLOCK OVDD BUSY DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D11/S2 D10/S1 D9/S0 D8 D7 D6 D5 D4 D3 D2 D1 D0 OGND 1851 BD INL COC ERROR (LSBs) M1 SHDN CS CONVST RD WR DIFF A2 A1 A0 UNI/BIP PGA M0 REFOUT 12-BIT 1.25Msps ADC DATA LATCHES OUTPUT DRIVERS REFIN REF AMP REFCOMP U W U Integral Linearity, LTC1851 1.00 0.50 0.00 –0.50 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1850/51 G01 18501f 1 LTC1850/LTC1851 ABSOLUTE AXI U RATI GS Supply Voltage (VDD) ................................................. 6V Analog Input Voltage (Note 3) ..... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ....................– 0.3V to 10V Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 500mW PACKAGE/ORDER I FOR ATIO TOP VIEW CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 48 M1 47 SHDN 46 CS 45 CONVST 44 RD 43 WR 42 DIFF 41 A2 40 A1 39 A0 38 UNI/BIP 37 PGA 36 M0 35 OVDD 34 OGND 33 BUSY 32 NC 31 NC 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 ORDER PART NUMBER LTC1850CFW LTC1850IFW REFOUT 10 REFIN 11 REFCOMP 12 GND 13 VDD 14 VDD 15 GND 16 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 D9/S2 21 D8/S1 22 D7/S0 23 D6 24 FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 110°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. 2 U U W WW U W OVDD = VDD (Notes 1, 2) Ambient Operating Temperature Range LTC1850C/LTC1851C ............................ 0°C to 70°C LTC1850I/LTC1851I .......................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C TOP VIEW CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 48 M1 47 SHDN 46 CS 45 CONVST 44 RD 43 WR 42 DIFF 41 A2 40 A1 39 A0 38 UNI/BIP 37 PGA 36 M0 35 OVDD 34 OGND 33 BUSY 32 D0 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7 ORDER PART NUMBER LTC1851CFW LTC1851IFW REFOUT 10 REFIN 11 REFCOMP 12 GND 13 VDD 14 VDD 15 GND 16 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 D11/S2 21 D10/S1 22 D9/S0 23 D8 24 FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 110°C/W 18501f LTC1850/LTC1851 CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error (Bipolar and Unipolar) Gain = 1 (PGA = 1) Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Offset Error Match Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Unipolar Gain Error Match Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Bipolar Gain Error Match Full-Scale Error Temperature Coefficient (Note 8) REFCOMP ≥ 2V REFCOMP ≥ 2V (Note 7) CONDITIONS The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 6) MIN q q q A ALOG I PUT The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL VIN PARAMETER Analog Input Range (Note 9) Unipolar, Gain = 1 (PGA = 1) Unipolar, Gain = 2 (PGA = 0) Bipolar, Gain = 1 (PGA = 1) Bipolar, Gain = 2 (PGA = 0) Analog Input Leakage Current Analog Input Capacitance CONDITIONS 4.75V ≤ VDD ≤ 5.25V 0 – REFCOMP 0 – REFCOMP/2 ± REFCOMP/2 ±REFCOMP/4 VIN > 0V < VDD, All Channels Between Conversions (Gain = 1) Between Conversions (Gain = 2) During Conversions q q q IIN CIN tACQ tS(MUX) tAP tjitter CMRR Sample-and-Hold Acquisition Time Multiplexer Settling Time (Includes tACQ) Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio 0V < (AIN – = AIN +) < 5V U U LTC1850 LTC1851 TYP MAX MIN TYP MAX 12 ± 0.25 ± 0.25 ± 0.5 ± 0.5 ±2 ±2 ±4 ±0.5 ± 0.35 ± 0.25 ±1 ±1 ±5 ±7 ± 10 ±1 ±6 ± 10 ±1 ±6 ±10 ±1 15 UNITS Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C 10 q q ±0.5 ±1 ±1 ±2 With External 4.096V Reference Applied to REFCOMP (Note 12) ±2 ±4 ±0.5 With External 4.096V Reference Applied to REFCOMP (Note 12) ±2 ±4 ±0.5 15 U MIN TYP MAX UNITS V V V V ±1 15 25 5 50 50 – 0.5 2 60 150 150 µA pF pF pF ns ns ns psRMS dB 18501f 3 LTC1850/LTC1851 DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 Signal-to-(Noise + Distortion) Ratio Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 Total Harmonic Distortion Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 Spurious-Free Dynamic Range Unipolar, PGA = 0 Unipolar, PGA = 1 Bipolar, PGA = 0 Bipolar, PGA = 1 S/(N+D) THD SFDR I TER AL REFERE CE PARAMETER REFOUT Output Voltage REFOUT Output Temperature Coefficient REFOUT Line Regulation Reference Buffer Gain REFCOMP Output Voltage REFCOMP Impedance DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD VDD = 4.75V, IO = – 10µA VDD = 4.75V, IO = – 200µA VDD = 4.75V, IO = 160µA VDD = 4.75V, IO = 1.6mA CS High (Note 9) VOUT = 0V VOUT = VDD q q q Hi-Z Output Leakage D11 to D0, ADOUT, A1OUT, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High Hi-Z Capacitance D11 to D0, ADOUT, A1OUT, A2OUT, DIFFOUT Output Source Current Output Sink Current 4 U U U WU (Note 5) CONDITIONS 47kHz Input Signal 61.6 61.7 61.6 61.7 47kHz Input Signal 61.0 61.0 61.0 61.2 47kHz Input Signal, First 5 Harmonics –76 –78 –81 –80 74 80 84 82 70 71 71 72 –80 –82 –87 –86 82 86 90 88 dB dB dB dB dB dB dB dB dB dB dB dB 71 72 71 72 dB dB dB dB MIN LTC1850 TYP MAX MIN LTC1851 TYP MAX UNITS 47kHz Input Signal U U TA = 25°C. (Notes 5, 6) CONDITIONS IOUT = 0 IOUT = 0 VREFCOMP/VREFIN External 2.5V Reference Internal 2.5V Reference REFIN = VDD 1.636 4.090 4.060 MIN 2.48 TYP 2.50 ± 15 0.01 1.638 4.096 4.096 6.4 1.640 4.100 4.132 MAX 2.52 UNITS V ppm/°C LSB/V V/V V V kΩ MIN 2.4 TYP MAX 0.8 ±5 UNITS V V µA pF V V 2 4.5 q q q q 4.0 0.05 0.10 0.4 ±10 15 – 20 30 V V µA pF mA mA 18501f LTC1850/LTC1851 POWER REQUIRE E TS SYMBOL VDD OVDD IDD PDISS PARAMETER Positive Supply Voltage Output Positive Supply Voltage Positive Supply Current Power Dissipation Power Down Positive Supply Current Nap Mode Sleep Mode Power Down Power Dissipation Nap Mode Sleep Mode The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS (Note 10) (Note 10) VDD = VDD = OVDD = 5V, fSAMPLE = 1.25MHz q q q q TI I G CHARACTERISTICS SYMBOL fSAMPLE(MAX) tCONV tACQ t1 t2 t3 t4 PARAMETER Maximum Sampling Frequency Acquisition + Conversion Conversion Time Acquisition Time CS to RD Setup Time CS to CONVST Setup Time CS to SHDN Setup Time SHDN to CONVST Wake-Up Time The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS q q q q t5 t6 t7 t8 t9 t10 CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD t11 BUS Relinquish Time 0°C to 70°C – 40°C to 85°C RD Low Time CONVST High Time Latch Setup Time Latch Hold Time WR Low Time (Note 10) (Notes 9, 10) (Notes 9, 10) (Note 10) q q q q q q q t12 t13 t14 t15 t16 UW MIN 4.75 2.7 TYP MAX 5.25 5.25 UNITS V V mA mW mA µA mW mW 8 40 1 50 5 0.25 10 50 SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V UW MIN 1.25 TYP MAX 800 650 150 UNITS MHz ns ns ns ns ns (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) Nap Mode (Note 10) Sleep Mode, 10µF REFCOMP Bypass Capacitor (Note 10) (Notes 10, 11) CL = 25pF q q 0 10 200 200 10 ns ns ms ns q q q 50 10 60 20 15 50 –5 20 35 45 45 60 30 35 40 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 18501f (Note 10) CL = 25pF q q q CL = 100pF q 25 10 t10 50 10 10 50 5 LTC1850/LTC1851 TI I G CHARACTERISTICS SYMBOL t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 PARAMETER WR High Time M1 to M0 Setup Time M0 to BUSY Delay M0 to WR (or RD) Setup Time M0 High Pulse Width RD High Time Between Readback Reads Last WR (or RD) to M0 M0 to RD Setup Time M0 to CONVST Aperture Delay Aperture Jitter The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS (Note 10) (Notes 9, 10) M1 High (Notes 9, 10) (Note 10) (Note 10) (Note 10) (Notes 9, 10) (Note 10) q q q q q q q q Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND, OGND and GND wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 4.75V to 5.25V, fSAMPLE = 1.25MHz, tr = tf = 2ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended input on any channel with COM grounded. 6 UW MIN 50 10 TYP MAX UNITS ns ns 20 t19 50 50 10 t19 t19 – 0.5 2 ns ns ns ns ns ns ns ns psRMS Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0111 1111 1111 and 1000 0000 0000 for LTC1851 and between 01 1111 1111 and 10 0000 0000 for LTC1850. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For the best results, ensure that CONVST returns high either within 400ns after the start of the conversion or after BUSY rises. Note 12: The analog input range is determined by the voltage on REFCOMP. The gain error specification is tested with an external 4.096V but is valid for any value of REFCOMP. 18501f LTC1850/LTC1851 TYPICAL PERFOR A CE CHARACTERISTICS Typical INL, PGA =1, LTC1851 1.00 1.00 DNL EOC ERROR (LSBs) 0.00 0.00 DNL EOC ERROR (LSBs) INL COC ERROR (LSBs) 0.50 –0.50 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1850/51 G01 Typical INL, PGA = 0, LTC1851 1.00 INL COC ERROR (LSBs) 0.50 AMPLITUDE (dB) –40 –60 –80 0.00 AMPLITUDE (dB) –0.50 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1850/51 G07 0 –20 AMPLITUDE (dB) –40 –60 –80 –100 –110 0 100 AMPLITUDE (dB) UW Typical DNL, PGA =1, LTC1851 1.00 Typical DNL, PGA = 0, LTC1851 0.50 0.50 0.00 –0.50 –0.50 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1850/51 G04 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1850/51 G02 Nonaveraged 4096 Point FFT, fIN = 47kHz, Unipolar Mode, PGA = 0, LTC1851 0 –20 SNR = 71.2dB SFDR = 82.0dB SINAD = 70.6dB 0 –20 –40 –60 –80 Nonaveraged 4096 Point FFT, fIN = 47kHz, Bipolar Mode, PGA = 0, LTC1851 SNR = 71.35dB SFDR = 90.4dB SINAD = 71.2dB –100 –100 –110 0 100 200 300 400 FREQUENCY (kHz) 500 600 –120 0 100 200 300 400 FREQUENCY (kHz) 500 600 LTC1850/51 G03 LTC1850/51 G05 Nonaveraged 4096 Point FFT, fIN = 47kHz, Unipolar Mode, PGA = 1, LTC1851 SNR = 72.3dB SFDR = 87.3dB SINAD = 71.4dB 0 –20 –40 –60 –80 Nonaveraged 4096 Point FFT, fIN = 47kHz, Bipolar Mode, PGA = 1, LTC1851 SNR = 72.3dB SFDR = 89.3dB SINAD = 72.1dB –100 –120 200 300 400 FREQUENCY (kHz) 500 600 0 100 200 300 400 FREQUENCY (kHz) 500 600 LTC1850/51 G06 LTC1850/51 G08 18501f 7 LTC1850/LTC1851 TYPICAL PERFOR A CE CHARACTERISTICS Distortion vs Input Frequency, Bipolar Mode, PGA = 1 –50 –55 –60 DISTORTION (dB) DISTORTION (dB) DISTORTION (dB) –65 –70 –75 –80 –85 –90 –95 THD 3RD HARMONIC 2ND HARMONIC –100 10 1000 100 FREQUENCY (kHz) 10000 185051 G09 Distortion vs Input Frequency, Unipolar Mode, PGA = 1 –50 –55 –60 DISTORTION (dB) –65 –70 2ND HARMONIC –75 –80 –85 –90 –95 –100 10 1000 100 FREQUENCY (kHz) 10000 185051 G20 CMRR (dB) THD 40 30 20 CMRR (dB) 3RD HARMONIC Input Common Mode Rejection Ratio vs Frequency, Bipolar Mode, PGA = 1 80 70 60 CMRR (dB) 40 30 20 10 0 1k 10k 100k FREQUENCY (Hz) LTC1850/51 G14 CMRR (dB) 50 8 UW Distortion vs Input Frequency, Bipolar Mode, PGA = 0 –50 –55 –60 –65 –70 THD –75 –80 –85 –90 –95 –100 10 1000 100 FREQUENCY (kHz) 10000 185051 G10 Distortion vs Input Frequency, Unipolar Mode, PGA = 0 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 10 1000 100 FREQUENCY (kHz) 10000 185051 G19 THD 3RD HARMONIC 2ND HARMONIC 3RD HARMONIC 2ND HARMONIC Input Common Mode Rejection Ratio vs Frequency, Bipolar Mode, PGA = 0 80 70 60 50 80 70 60 50 40 30 20 10 1k 10k 100k FREQUENCY (Hz) LTC1850/51 G11 Input Common Mode Rejection Ratio vs Frequency, Unipolar Mode, PGA = 0 10 0 1M 10M 0 1k 10k 100k FREQUENCY (Hz) 1M 10M LTC1850/51 G13 Input Common Mode Rejection Ratio vs Frequency, Unipolar Mode, PGA = 1 80 70 60 50 40 30 20 10 1M 10M 0 1k 10k 100k FREQUENCY (Hz) 1M 10M LTC1850/51 G16 18501f LTC1850/LTC1851 TYPICAL PERFOR A CE CHARACTERISTICS Channel-to-Channel Isolation (Worst Pair) Bipolar Mode, PGA = 0 110 100 90 LIMIT OF MEASUREMENT 80 70 60 50 0 2M 4M 6M 8M INPUT FREQUENCY (Hz) 10M 110 100 90 LIMIT OF MEASUREMENT 80 70 60 50 0 2M 4M 6M 8M INPUT FREQUENCY (Hz) 10M ISOLATION (dB) LTC1850/51 G12 ISOLATION (dB) Channel-to-Channel Isolation (Worst Pair), Unipolar Mode, PGA = 1 110 100 ISOLATION (dB) 90 LIMIT OF MEASUREMENT 80 70 60 50 0 2M 4M 6M FREQUENCY (Hz) 8M 10M 110 100 90 ISOLATION (dB) UW Channel-to-Channel Isolation (Worst Pair), Unipolar Mode, PGA = 0 LTC1850/51 G15 Channel-to-Channel Isolation (Worst Pair), Bipolar Mode, PGA =1 LIMIT OF MEASUREMENT 80 70 60 50 0 2M 4M 6M 8M INPUT FREQUENCY (Hz) 10M LTC1850/51 G18 LTC1850/51 G17 18501f 9 LTC1850/LTC1851 PI FU CTIO S CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin (COM) or differentially in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). COM (Pin 9): Analog Input Common Pin. For single-ended operation (DIFF = 0), COM is the “–” analog input. COM is disabled when DIFF is high. REFOUT (Pin 10): Internal 2.5V Reference Output. Requires bypass to analog ground plane with 1µF. REFIN (Pin 11): Reference Mode Select/Reference Buffer Input. REFIN selects the Reference mode and acts as the reference buffer Input. REFIN tied to ground will produce 2.048V on the REFCOMP pin. REFIN tied to the positive supply disables the reference buffer to allow REFCOMP to be driven externally. For voltages between 1V and 2.6V, the reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on REFIN (4.096V on REFCOMP for a 2.5V input on REFIN). REFCOMP (Pin 12): Reference Buffer Output. REFCOMP sets the full-scale input span. The reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on the REFIN pin (4.096V on REFCOMP for a 2.5V input on REFIN). REFIN tied to ground will produce 2.048V on the REFCOMP pin. REFCOMP can be driven externally if REFIN is tied to the positive supply. Requires bypass to analog ground plane with 10µF tantalum in parallel with 0.1µF ceramic or 10µF ceramic. GND (Pin 13): Ground. Tie to analog ground plane. VDD (Pin 14): 5V Supply. Short to Pin 15. VDD (Pin 15): 5V Supply. Bypass to GND with 10µF tantalum in parallel with 0.1µF ceramic or 10µF ceramic. GND (Pin 16): Ground for Internal Logic. Tie to analog ground plane. DIFFOUT/S6 (Pin 17): Three-State Digital Data Output. Active when RD is low. Following a conversion, the singleended/differential bit of the present conversion is available on this pin concurrent with the conversion result. In Readback mode, the single-ended/differential bit of the current sequencer location (S6) is available on this pin. The output swings between OVDD and OGND. A2OUT/S5, A1OUT/S4, A0OUT/S3 (Pins 18 to 20): ThreeState Digital MUX Address Outputs. Active when RD is low. Following a conversion, the MUX address of the present conversion is available on these pins concurrent with the conversion result. In Readback mode, the MUX address of the current sequencer location (S5-S3) is available on these pins. The outputs swing between OVDD and OGND. D9/S2 (Pin 21, LTC1850): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D11/S2 (Pin 21, LTC1851): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 11 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D8/S1 (Pin 22, LTC1850): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 8 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D10/S1 (Pin 22, LTC1851): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 10 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D7/S0 (Pin 23, LTC1850): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 7 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. 10 U U U 18501f LTC1850/LTC1851 PI FU CTIO S D9/S0 (Pin 23, LTC1851): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. D8 to D0 (Pins 24 to 32, LTC1851): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. NC (Pins 31, 32, LTC1850): No Connect. There is no internal connection to these pins. BUSY (Pin 33): Converter Busy Output. The BUSY output has two functions. At the start of a conversion, BUSY will go low and remain low until the conversion is completed. The rising edge may be used to latch the output data. BUSY will also go low while the part is in Program/Readback mode (M1 high, M0 low) and remain low until M0 is brought back high. The output swings between OVDD and OGND. OGND (Pin 34): Digital Data Output Ground. Tie to analog ground plane. May be tied to logic ground if desired. OVDD (Pin 35): Digital Data Output Supply. Normally tied to 5V, can be used to interface with 3V digital logic. Bypass to OGND with 10µF tantalum in parallel with 0.1µF ceramic or 10µF ceramic. See Table 5. M0 (Pin 36): Mode Select Pin 0. Used in conjunction with M1 to select operating mode. See Table 5 PGA (Pin 37): Gain Select Input. A high logic level selects gain = 1, a low logic level selects gain = 2. UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low selects a unipolar input span, a high logic level selects a bipolar input span. A0 to A2 (Pins 39 to 41): MUX Address Input Pins. DIFF (Pin 42): Single-Ended/Differential Select Input. A low logic level selects single-ended mode, a high logic level selects differential mode. WR (Pin 43): Write Input. In Direct Address mode, WR low enables the MUX address and configuration input pins (Pins 37 to 42). WR can be tied low or the rising edge of WR can be used to latch the data. In Program mode, WR is used to program the sequencer. WR low enables the MUX address and configuration input pins (Pins 37 to 42). The rising edge of WR latches the data and increments the counter to the next sequencer location. RD (Pin 44): Read Input. During normal operation, RD enables the output drivers when CS is low. In Readback mode (M1 high, M0 low), RD going low reads the current sequencer location, RD high advances to the next sequencer location. CONVST (Pin 45): Conversion Start Input. This active low signal starts a conversion on its falling edge. CS (Pin 46): Chip Select Input. The chip select input must be low for the ADC to recognize the CONVST and RD inputs. If SHDN is low, a low logic level on CS selects Nap mode; a high logic level on CS selects Sleep mode. SHDN (Pin 47): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the CS pin. CS low selects Nap mode, CS high selects Sleep mode. Tie high if unused. M1 (Pin 48): Mode Select Pin 1. Used in conjunction with M0 to select operating mode. U U U 18501f 11 LTC1850/LTC1851 PI FU CTIO S PIN 1 to 8 9 10 11 12 13 14 15 16 17 18 19 20 21 21 22 22 23 23 24 to 30 24 to 32 31 to 32 33 34 35 36 37 38 39 to 41 42 43 44 45 46 47 48 NAME CH0 to CH7 COM REFOUT REFIN REFCOMP GND VDD VDD GND DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D9/S2 (LTC1850) D11/S2 (LTC1851) D8/S1 (LTC1850) D10/S1 (LTC1851) D7/S0 (LTC1850) D9/S0 (LTC1851) D6 to D0 (LTC1850) D8 to D0 (LTC1851) NC (LTC1850) BUSY OGND OVDD M0 PGA UNI/BIP A0 to A2 DIFF WR RD CONVST CS SHDN M1 Converter Busy Output Output Ground Output Supply Mode Select Pin 0 Gain Select Input Unipolar/Bipolar Input MUX Address Inputs Single-Ended/Differential Input Write Input, Active Low Read Input, Active Low Conversion Start Input, Active Low Chip Select Input, Active Low Shutdown Input, Active Low Mode Select Pin 1 2.7 0 0 0 0 0 0 0 0 0 0 0 OGND 0 5 5.25 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD OVDD –0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 VDD + 0.3 VDD + 0.3 6 10 10 10 10 10 10 10 10 10 10 10 DESCRIPTION Analog Inputs Analog Input Common Pin 2.5V Reference Output Reference Buffer Input Reference Buffer Output Ground, Substrate Ground Supply Supply Ground Single-Ended/Differential Output MUX Address Output MUX Address Output MUX Address Output Data Output Data Output Data Output Data Output Data Output Data Output Data Outputs Data Outputs OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND 4.75 4.75 0 MIN 0 0 2.5 2.5 4.096 0 5 5 0 OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 5.25 5.25 VDD NOMINAL (V) TYP MAX VDD VDD ABSOLUTE MAXIMUM (V) MIN MAX – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 – 0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 6 6 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 12 U U U 18501f LTC1850/LTC1851 APPLICATIO S I FOR ATIO The LTC1850/LTC1851 are complete and very flexible data acquisition systems. They consist of a 10-bit/12-bit, 1.25Msps capacitive successive approximation A/D converter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifier, a 16-bit parallel digital output and digital control logic including a programmable sequencer. CONVERSION DETAILS The core analog-to-digital converter in the LTC1850/ LTC1851 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 10-bit/12-bit parallel output. Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle is begun, it cannot be restarted. During the conversion, the internal differential 10-bit/12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The outputs of the analog input multiplexer are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches are open, putting the comparator into compare mode. The input switches connect CSAMPLE to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of the conversion, the differential DAC output balances the input charges. The SAR contents (a 10-bit/ 12-bit data word), which represents the difference of the analog input multiplexer outputs, and the 4-bit address word are loaded into the 14-bit/16-bit output latches. U DYNAMIC PERFORMANCE Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where ENOB is the effective number of bits and S/(N + D) is expressed in dB. At the maximum sampling rate of 1.25MHz, the LTC1850/LTC1851 maintain near ideal ENOBs up to and beyond the Nyquist input frequency of 625kHz. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log V22 + V32 + V 42 + ...Vn2 V1 W UU where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The LTC1850/LTC1851 have good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 18501f 13 LTC1850/LTC1851 APPLICATIO S I FOR ATIO If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD fa ± fb = 20Log ( ) Amplitude at fa ± fb Amplitude at fa ( Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB for the LTC1851 (11 effective bits) or 56dB for the LTC1850 (9 effective bits). The LTC1850/LTC1851 have been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. ANALOG INPUT MULTIPLEXER The analog input multiplexer is controlled using the singleended/differential pin (DIFF), three MUX address pins (A2, A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain select pin (PGA). The single-ended/differential pin (DIFF) allows the user to configure the MUX as eight singleended channels relative to the analog input common pin 14 U (COM) when DIFF is low or as four differential pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when DIFF is high. The channels (and polarity in the differential case) are selected using the MUX address inputs as shown in Table 1. Unused inputs (including the COM in the differential case) should be grounded to prevent noise coupling. Table 1. Multiplexer Address Table MUX ADDRESS 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 + + + + + + + + DIFFERENTIAL CHANNEL SELECTION + – – + + – – + + – – + + – – + * * * * * * * * SINGLE-ENDED CHANNEL SELECTION – – – – – – – – DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM W UU ) MUX ADDRESS 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM *Not used in differential mode. Connect to GND. In addition to selecting the MUX channel, the LTC1850/ LTC1851 also allows the user to select between two gains and unipolar or bipolar inputs for a total of four input spans. PGA high selects a gain of 1 (the input span is equal to the voltage on REFCOMP). PGA low selects a gain of 2 where the input span is equal to half of the voltage on REFCOMP. UNI/BIP low selects a unipolar input span, UNI/BIP high selects a bipolar input span. Table 2 summarizes the possible input spans. 18501f LTC1850/LTC1851 APPLICATIO S I FOR ATIO Table 2. Input Span Table INPUT SPAN UNI/BIP 0 0 1 1 PGA 0 1 0 1 0 – REFCOMP/2 0 – REFCOMP ± REFCOMP/4 ± REFCOMP/2 REFCOMP = 4.096V 0 – 2.048V 0 – 4.096V ± 1.024V ± 2.048V It should be noted that the bipolar input span of the LTC1850/LTC1851 does not allow negative inputs with respect to ground. The LTC1850/LTC1851 have a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of the “+” and “–” inputs independent of the common mode voltage. The common mode rejection holds up to high frequencies. The only requirement is that both inputs can not exceed the VDD power supply voltage or ground. When a bipolar input span is selected the “+” input can swing ± full scale relative to the “–” input but neither input can exceed VDD or go below ground. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Some AC applications may have their performance limited by distortion. The ADC and many other circuits exhibit higher distortion when signals approach the supply or ground. THD will degrade as the inputs approach either power supply rail. Distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. Driving the Analog Inputs The inputs of the LTC1850/LTC1851 are easy to drive. Each of the analog inputs can be used as a single-ended input relative to the input common pin (CH0-COM, CH1COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differential inputs. Regardless of the MUX configuration, the “+” and “–” inputs are U sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1850/LTC1851 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 150ns for full throughput rate). Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (