LTC1852CFW-TRPBF

LTC1852/LTC1853 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs FEATURES n DESCRIPTION The 10-bit LTC®1852 and 12-bit LTC1853 are complete 8-channel data acquisition systems. They include a flexible 8-channel multiplexer, a 400ksps successive approximation analog-to-digital converter, an internal reference and a parallel output interface. The multiplexer can be configured for single-ended or differential inputs, two gain ranges and unipolar or bipolar operation. The ADCs have a scan mode that will repeatedly cycle through all 8 multiplexer channels and can also be programmed to sequence through up to 16 addresses and configurations. The sequence can also be read back from internal memory. The reference and buffer amplifier provide pin strappable ranges of 4.096V, 2.5V and 2.048V. The parallel output includes the 10-bit or 12-bit conversion result plus the 4-bit multiplexer address. The digital outputs are powered from a separate supply allowing for easy interface to 3V digital logic. Typical power consumption is 10mW at 400ksps from a single 5V supply and 3mW at 250ksps from a single 3V supply. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. n n n n n n n Flexible 8-Channel Multiplexer Single-Ended or Differential Inputs Two Gain Ranges Unipolar or Bipolar Operation Scan Mode and Programmable Sequencer Eliminate Configuration Software Overhead Low Power: 3mW at 250ksps 2.7V to 5.5V Supply Range Internal or External Reference Operation Parallel Output Includes MUX Address Nap and Sleep Shutdown Modes Pin Compatible up-grade 1.25Msps 10-Bit LTC1850 and 12-Bit LTC1851 APPLICATIONS n n n n n n High Speed Data Acquisition Test and Measurement Imaging Systems Telecommunications Industrial Process Control Spectrum Analysis BLOCK DIAGRAM LTC1853 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 2.5V REFERENCE 8-CHANNEL MULTIPLEXER INTERNAL CLOCK CONTROL LOGIC AND PROGRAMMABLE SEQUENCER M1 SHDN CS CONVST RD WR DIFF A2 A1 A0 UNI/BIP PGA M0 OVDD BUSY DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D11/S2 D10/S1 D9/S0 D8 D7 D6 D5 D4 D3 D2 D1 D0 OGND 18523 BD Integral Linearity 1.0 0.5 INL ERROR (LSBs) 0 –0.5 REFOUT + – 12-BIT SAMPLING ADC DATA LATCHES OUTPUT DRIVERS –1.0 0 REFIN REF AMP 512 1024 1536 2048 2560 3072 3584 4096 CODE 1852 F01 REFCOMP 18523fa 1 LTC1852/LTC1853 ABSOLUTE MAXIMUM RATINGS OVDD = VDD (Note 1, 2) Supply Voltage (VDD) ..................................................6V Analog Input Voltage (Note 3) ..... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) .................... –0.3V to 10V Digital Output Voltage ..................–0.3V to (VDD + 0.3V) Power Dissipation ...............................................500mW Ambient Operating Temperature Range LTC1852C/LTC1853C .............................. 0°C to 70°C LTC1852I/LTC1853I............................. –40°C to 85°C Storage Temperature Range...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ................. 300°C PIN CONFIGURATION LTC1852 TOP VIEW CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 48 M1 47 SHDN 46 CS 45 CONVST 44 RD 43 WR 42 DIFF 41 A2 40 A1 39 A0 38 UNI/BIP 37 PGA 36 M0 35 OVDD 34 OGND 33 BUSY 32 NC 31 NC 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 LTC1853 TOP VIEW 48 M1 47 SHDN 46 CS 45 CONVST 44 RD 43 WR 42 DIFF 41 A2 40 A1 39 A0 38 UNI/BIP 37 PGA 36 M0 35 OVDD 34 OGND 33 BUSY 32 D0 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7 REFOUT 10 REFIN 11 REFCOMP 12 GND 13 VDD 14 VDD 15 GND 16 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 D9/S2 21 D8/S1 22 D7/S0 23 D6 24 REFOUT 10 REFIN 11 REFCOMP 12 GND 13 VDD 14 VDD 15 GND 16 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 D11/S2 21 D10/S1 22 D9/S0 23 D8 24 FW PACKAGE 48-LEAD PLASTIC TSSOP FW PACKAGE 48-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 110°C/W TJMAX = 150°C, θJA = 110°C/W ORDER INFORMATION LEAD FREE FINISH LTC1852CFW#PBF LTC1852IFW#PBF LTC1853CFW#PBF LTC1853IFW#PBF TAPE AND REEL LTC1852CFW#TRPBF LTC1852IFW#TRPBF LTC1853CFW#TRPBF LTC1853IFW#TRPBF PART MARKING LTC1852CFW LTC1852IFW LTC1853CFW LTC1853IFW PACKAGE DESCRIPTION 48-Lead Plastic TSSOP (6.1mm) 48-Lead Plastic TSSOP (6.1mm) 48-Lead Plastic TSSOP (6.1mm) 48-Lead Plastic TSSOP (6.1mm) TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 18523fa 2 LTC1852/LTC1853 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, REFCOMP < VDD (Notes 5,6) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error (Bipolar and Unipolar) Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Offset Error Match (Bipolar and Unipolar) Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Unipolar Gain Error Match Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Bipolar Gain Error Match Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Full-Scale Error Temperature Coefficient With External 2.5V Reference Applied to REFCOMP VDD = 2.7V to 5.5V, fS ≤ 250kHz With External 2.5V Reference Applied to REFCOMP VDD = 2.7V to 5.5V, fS ≤ 250kHz l l l l CONVERTER CHARACTERISTICS CONDITIONS MIN l LTC1852 TYP ±0.25 ±0.25 ±0.5 ±1 MAX ±1 ±1 ±2 ±4 ±0.5 MIN 12 LTC1853 TYP ±0.35 ±0.25 ±1 ±2 MAX ±1 ±1 ±6 ±12 ±1 ±4 ±8 ±1 ±4 ±8 ±1 UNITS Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C 10 (Note 7) (Note 8) REFCOMP ≥ 2V l l l l With External 4.096V Reference Applied to REFCOMP (Note 12) VDD = 4.75V to 5.25V, fS ≤ 400kHz With External 4.096V Reference Applied to REFCOMP (Note 12) VDD = 4.75V to 5.25V, fS ≤ 400kHz ±2 ±4 ±0.5 ±2 ±4 ±0.5 ±1 ±2 ±1 ±2 15 ±3 ±6 ±3 ±6 ±1.5 ±3 ±1.5 ±3 15 ±8 ±16 ±8 ±16 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 5) SYMBOL VIN PARAMETER Analog Input Range (Note 9) Unipolar, Gain = 1 (PGA = 1) Unipolar, Gain = 2 (PGA = 0) Bipolar, Gain = 1 (PGA = 1) Bipolar, Gain = 2 (PGA = 0) Analog Input Leakage Current Analog Input Capacitance Between Conversions (Gain = 1) Between Conversions (Gain = 2) During Conversions CONDITIONS 2.7V ≤ VDD ≤ 5.5V, REFCOMP ≤ VDD 0 – REFCOMP 0 – REFCOMP/2 ± REFCOMP/2 ±REFCOMP/4 l ANALOG INPUT MIN TYP MAX UNITS V V V V IIN CIN ±1 15 25 5 50 50 150 150 μA pF pF pF ns ns ns psRMS dB tACQ tS(MUX) tAP tjitter CMRR Sample-and-Hold Acquisition Time Multiplexer Settling Time (Includes tACQ) Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio VDD = 5V VDD = 5V – 0.5 2 60 DYNAMIC ACCURACY SYMBOL S/(N + D) THD SFDR PARAMETER Total Harmonic Distortion Spurious Free Dynamic Range TA = 25°C. (Notes 5) CONDITIONS 40kHz Input Signal 40kHz Input Signal, First 5 Harmonics 40kHz Input Signal MIN TYP 72.5 –80 –85 MAX UNITS dB dB dB 18523fa Signal-to-Noise Plus Distortion Ratio 3 LTC1852/LTC1853 INTERNAL REFERENCE PARAMETER REFOUT Output Voltage REFOUT Output Temperature Coefficient REFOUT Line Regulation Reference Buffer Gain REFCOMP Output Voltage REFCOMP Impedance External 2.5V Reference (VDD = 5V) Internal 2.5V Reference (VDD = 5V) Impedance to GND, REFIN = VDD TA = 25°C. (Notes 5, 6) CONDITIONS IOUT = 0 IOUT = 0 2.7 ≤ VDD ≤ 5.5, IOUT = 0 1.6368 4.092 4.060 MIN 2.48 TYP 2.50 ±15 0.01 1.6384 4.096 4.096 19.2 1.6400 4.100 4.132 MAX 2.52 UNITS V ppm/°C LSB/V V/V V V kΩ The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V (Note 5) SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage VDD = 4.75V, IO = – 10μA VDD = 4.75V, IO = – 200μA VDD = 4.75V, IO = 160μA VDD = 4.75V, IO = 1.6mA CS High (Note 9) VOUT = 0V VOUT = VDD ● ● ● ● DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD MIN ● ● ● TYP MAX 0.8 ±5 UNITS V V μA pF V V 2.4 1.5 4.5 4 0.5 0.10 0.4 ±10 15 –20 30 V V μA pF mA mA Hi-Z Output Leakage D11 to D0, A0, A1, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High Hi-Z Capacitance D11 to D0 Output Source Current Output Sink Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 5V (Note 5) SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage VDD = 2.7V, IO = – 10μA VDD = 2.7V, IO = – 200μA VDD = 2.7V, IO = 160μA VDD = 2.7V, IO = 1.6mA CS High (Note 9) VOUT = 0V VOUT = VDD ● ● ● ● DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD MIN ● ● ● TYP MAX 0.45 ±5 UNITS V V μA pF V V 1.9 1.5 2.5 2 0.05 0.10 0.4 ±10 15 –10 15 V V μA pF mA mA Hi-Z Output Leakage D11 to D0, A0, A1, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High Hi-Z Capacitance D11 to D0 Output Source Current Output Sink Current 18523fa 4 LTC1852/LTC1853 POWER REQUIREMENTS SYMBOL VDD OVDD IDD PDISS IDDPD PARAMETER Analog Positive Supply Voltage Output Positive Supply Voltage Positive Supply Current Power Dissipation Power Down Positive Supply Current Nap Mode Sleep Mode Power Down Power Dissipation Nap Mode Sleep Mode Power Down Power Dissipation Nap Mode Sleep Mode The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS (Note 10) (Note 10) VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz SHDN = Low, CS = Low SHDN = Low, CS = High VDD = VDD = OVDD = 5V, fS = 400kHz SHDN = Low, CS = Low SHDN = Low, CS = High VDD = VDD = OVDD = 3V, fS = 250kHz SHDN = Low, CS = Low SHDN = Low, CS = High ● ● ● ● ● ● MIN 2.7 2.7 TYP MAX 5.5 5.5 UNITS V V mA mA mW mW mA μA mW mW mW mW 2 0.83 10 2.25 0.5 20 2.5 0.1 1.5 0.06 3 1.33 15 4 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL fSAMPLE(MAX) PARAMETER Maximum Sampling Frequency Acquisition + Conversion tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Conversion Time Acquisition Time CS to RD Setup Time CS to CONVST Setup Time CS to SHDN Setup Time SHDN to CONVST Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY ● TIMING CHARACTERISTICS CONDITIONS VDD = 5.5V VDD = 2.7V VDD = 5.5V VDD = 2.7V VDD = 5.5V VDD = 2.7V (Note 13) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) Nap Mode (Note 10) Sleep Mode (Note 10) (Notes 10, 11) CL = 25pF ● ● ● ● ● ● ● ● ● ● ● MIN 400 250 TYP MAX UNITS kHz kHz 2.5 4.0 2.0 3.5 150 0 10 200 200 10 50 10 60 20 15 50 –5 20 35 45 45 60 30 35 40 35 μs μs μs μs ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 18523fa Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD (Note 10) ● ● CL = 25pF CL = 100pF ● 25 ● t11 BUS Relinquish Time 0°C to 70°C – 40°C to 85°C ● ● ● 10 t12 RD Low Time t10 5 LTC1852/LTC1853 TIMING CHARACTERISTICS SYMBOL t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 PARAMETER CONVST High Time Latch Setup Time Latch Hold Time WR Low Time WR High Time M1 to M0 Setup Time M0 to BUSY Delay M0 to WR (or RD) Setup Time M0 High Pulse Width RD High Time Between Readback Reads Last WR (or RD) to M0 M0 to RD Setup Time M0 to CONVST Aperture Delay Aperture Jitter The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS (Note 10) (Note 10) (Notes 9, 10) (Note 10) (Note 10) (Notes 9, 10) M1 High (Notes 9, 10) (Note 10) (Note 10) (Note 10) (Notes 9, 10) (Note 10) ● ● ● ● ● ● ● ● ● ● ● ● MIN 50 10 10 50 50 10 TYP MAX UNITS ns ns ns ns ns ns 20 t19 50 50 10 t19 t19 – 0.5 2 ns ns ns ns ns ns ns ns psRMS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with OGND and GND wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 400kHz, tr = tf = 2ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended input on any channel with COM grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 1111 1111 1111 and 0000 0000 0000. For the LTC1853 and between 11 1111 1111 and 00 0000 0000 for the LTC1852. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For the best results, ensure that CONVST returns high either within 400ns after the start of the conversion or after BUSY rises. Note 12: The analog input range is determined by the voltage on REFCOMP The gain error specification is tested with an external 4.096V . but is valid for any value of REFCOMP greater than 2V and less than (VDD – 0.5V.) Note 13: MUX address is updated immediately after BUSY falls. TYPICAL PERFORMANCE CHARACTERISTICS Differential Linearity 1.0 0 –20 8192 Point FFT with fIN = 39.599kHz 0.5 DNL ERROR (LBS) AMPLITUDE (dB) –40 –60 –80 –100 0 –0.5 –1.0 –120 0 CODE 4096 1852 F02 0 FREQUENCY (kHz) 200 1852 F03 18523fa 6 LTC1852/LTC1853 PIN FUNCTIONS CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin or differentially in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). COM (Pin 9): Analog Input Common Pin. For single-ended operation (DIFF = 0), COM is the “–” analog input. COM is disabled when DIFF is high. REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass to analog ground plane with 1μF . REFIN (Pin 11): Reference Mode Select/Reference Buffer Input. REFIN selects the reference mode and acts as the reference buffer input. REFIN tied to ground (Logic 0) will produce 2.048V on the REFCOMP pin. REFIN tied to the positive supply (Logic 1) disables the reference buffer to allow REFCOMP to be driven externally. For voltages between 1V and 2.6V, the reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on REFIN (4.096V on REFCOMP for a 2.5V input on REFIN). REFCOMP (Pin 12): Reference Buffer Output. REFCOMP sets the full-scale input span. The reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on the REFIN pin (4.096V on REFCOMP for a 2.5V input on REFIN). REFIN tied to ground will produce 2.048V on the REFCOMP pin. REFCOMP can be driven externally if REFIN is tied to the positive supply. Bypass to analog ground plane with 10μF tantalum in parallel with 0.1μF ceramic or 10μF ceramic. GND (Pins 13, 16): Ground. Tie to analog ground plane. VDD (Pins 14, 15): Positive Supply. Bypass to analog ground plane with 10μF tantalum in parallel with 0.1μF ceramic or 10μF ceramic. DIFFOUT/S6 (Pin 17): Three-State Digital Data Output. Active when RD is low. Following a conversion, the single-ended/differential bit of the present conversion is available on this pin concurrent with the conversion result. In Readback mode, the single-ended/differential bit of the current sequencer location (S6) is available on this pin. The output swings between OVDD and OGND. A2OUT/S5, A1OUT/S4, A0OUT/S3 (Pins 18 to 20): ThreeState Digital MUX Address Outputs. Active when RD is low. Following a conversion, the MUX address of the present conversion is available on these pins concurrent with the conversion result. In Readback mode, the MUX address of the current sequencer location (S5-S3) is available on these pins. The outputs swing between OVDD and OGND. D9/S2 (Pin 21, LTC1852): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D11/S2 (Pin 21, LTC1853): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 11 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D8/S1 (Pin 22, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 8 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D10/S1 (Pin 22, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 10 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D7/S0 (Pin 23, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 7 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. 18523fa 7 LTC1852/LTC1853 PIN FUNCTIONS D9/S0 (Pin 23, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. D8 to D0 (Pins 24 to 32, LTC1853): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. NC (Pins 31 to 32, LTC1852): No Connect. There is no internal connection to these pins. BUSY (Pin 33): Converter Busy Output. The BUSY output has two functions. At the start of a conversion, BUSY will go low and remain low until the conversion is completed. The rising edge may be used to latch the output data. BUSY will also go low while the part is in Program/Readback mode (M1 high, M0 low) and remain low until M0 is brought back high. The output swings between OVDD and OGND. OGND (Pin 34): Digital Data Output Ground. Tie to analog ground plane. May be tied to logic ground if desired. OVDD (Pin 35): Digital Data Output Supply. Normally tied to 5V, can be used to interface with 3V digital logic. Bypass to OGND with 10μF tantalum in parallel with 0.1μF ceramic or 10μF ceramic. M0 (Pin 36): Mode Select Pin 0. Used in conjunction with M1 to select operating mode. See Table 5. PGA (Pin 37): Gain Select Input. A high logic level selects gain = 1, a low logic level selects gain = 2. UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low selects a unipolar input span, a high logic level selects a bipolar input span. A0 to A2 (Pins 39 to 41): MUX Address Input Pins. DIFF (Pin 42): Single-Ended/Differential Select Input. A low logic level selects single ended, a high logic level selects differential. WR (Pin 43): Write Input. In Direct Address mode, WR low enables the MUX address and configuration input pins (Pins 37 to 42). WR can be tied low or the rising edge of WR can be used to latch the data. In Program mode, WR is used to program the sequencer. WR low enables the MUX address and configuration input pins (Pins 37 to 42). The rising edge of WR latches the data and increments the counter to the next sequencer location. RD (Pin 44): Read Input. During normal operation, RD enables the output drivers when CS is low. In Readback mode (M1 high, M0 low), RD going low reads the current sequencer location, RD high advances to the next sequencer location. CONVST (Pin 45): Conversion Start Input. This active low signal starts a conversion on its falling edge. CS (Pin 46): Chip Select Input. The chip select input must be low for the ADC to recognize the CONVST and RD inputs. If SHDN is low, a low logic level on CS selects Nap mode; a high logic level on CS selects Sleep mode. SHDN (Pin 47): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the CS pin. CS low selects Nap mode, CS high selects Sleep mode. Tie high if unused. M1 (Pin 48): Mode Select Pin 1. Used in conjunction with M0 to select operating mode. See Table 5. 18523fa 8 LTC1852/LTC1853 PIN FUNCTIONS PIN 1 to 8 9 10 11 12 13 14 15 16 17 18 19 20 21 21 22 22 23 23 24 to 30 24 to 32 31 to 32 33 34 35 36 37 38 39 to 41 42 43 44 45 46 47 48 NAME CH0 to CH7 COM REFOUT REFIN REFCOMP GND VDD VDD GND DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D9/S2 (LTC1852) D11/S2 (LTC1853) D8/S1 (LTC1852) D10/S1 (LTC1853) D7/S0 (LTC1852) D9/S0 (LTC1853) D6 to D0 (LTC1852) D8 to D0 (LTC1853) NC (LTC1852) BUSY OGND OVDD M0 PGA UNI/BIP A0 to A2 DIFF WR RD CONVST CS SHDN M1 DESCRIPTION Analog Inputs Analog Input Common Pin 2.5V Reference Output Reference Buffer Input Reference Buffer Output Ground Positive Supply Positive Supply Ground Single-Ended/Differential Output MUX Address Output MUX Address Output MUX Address Output Data Output Data Output Data Output Data Output Data Output Data Output Data Outputs Data Outputs No Connect Converter Busy Output Output Ground Output Supply Mode Select Pin 0 Gain Select Input Unipolar/Bipolar Input MUX Address Inputs Single-Ended/Differential Input Write Input, Active Low Read Input, Active Low Conversion Start Input, Active Low Chip Select Input, Active Low Shutdown Input, Active Low Mode Select Pin 1 2.7 0 0 0 0 0 0 0 0 0 0 0 OGND 0 5 5.5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 0VDD –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VDD + 0.3 VDD + 0.3 6 6 6 6 6 6 6 6 6 6 6 6 OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND 2.7 2.7 0 MIN 0 0 2.5 2.5 4.096 0 5 5 0 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 5.5 5.5 VDD NOMINAL (V) TYP MAX VDD VDD ABSOLUTE MAXIMUM (M) MIN MAX –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 6 6 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 18523fa 9 LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 are complete and very flexible data acquisition systems. They consist of a 10-bit/12-bit, 400ksps capacitive successive approximation A/D converter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifier, a 16-bit parallel digital output and digital control logic, including a programmable sequencer. CONVERSION DETAILS The core analog-to-digital converter in the LTC1852/ LTC1853 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 10-bit/12-bit parallel output. Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle is begun, it cannot be restarted. During the conversion, the internal differential capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The outputs of the analog input multiplexer are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches are open, putting the comparator into compare mode. The input switches connect CSAMPLE to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of the conversion, the differential DAC output balances the input charges. The SAR contents (a 10-bit/12-bit data word), which represents the difference of the analog input multiplexer outputs, and the 4-bit address word are loaded into the 14-bit/16-bit output latches. DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where ENOB is the effective number of bits and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1852/LTC1853 maintain near ideal ENOBs up to and beyond the Nyquist input frequency of 200kHz. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log V22 + V32 + V42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The LTC1852/LTC1853 have good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 18523fa 10 LTC1852/LTC1853 APPLICATIONS INFORMATION If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD ( fa ± fb) = 20Log Amplitude at ( fa ± fb) Amplitude at fa inputs as shown in Table 1. Unused inputs (including the COM in the differential case) should be grounded to prevent noise coupling. Table 1. Multiplexer Address Table MUX ADDRESS DIFF A2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 + + + + + + + + DIFFERENTIAL CHANNEL SELECTION + – – + + – – + + – – + + – – + * * * * * * * * SINGLE-ENDED CHANNEL SELECTION – – – – – – – – A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB for the LTC1853 (11 effective bits) or 56dB for the LTC1852 (9 effective bits). The LTC1852/LTC1853 have been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. ANALOG INPUT MULTIPLEXER The analog input multiplexer is controlled using the single-ended/differential pin (DIFF), three MUX address pins (A2, A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain select pin (PGA). The single-ended/differential pin (DIFF) allows the user to configure the MUX as eight single-ended channels relative to the analog input common pin (COM) when DIFF is low or as four differential pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when DIFF is high. The channels (and polarity in the differential case) are selected using the MUX address MUX ADDRESS DIFF A2 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM *Not used in differential mode. Connect to AGND. In addition to selecting the MUX channel, the LTC1852/ LTC1853 also allows the user to select between two gains and unipolar or bipolar inputs for a total of four input spans. PGA high selects a gain of 1 (the input span is equal to the voltage on REFCOMP). PGA low selects a gain of 2 where the input span is equal to half of the voltage on REFCOMP . UNI/BIP low selects a unipolar input span, UNI/BIP high selects a bipolar input span. Table 2 summarizes the possible input spans. Table 2. Input Span Table INPUT SPAN UNI/BIP 0 0 1 1 PGA 0 1 0 1 0 – REFCOMP/2 0 – REFCOMP ± REFCOMP/4 ±REFCOMP/2 REFCOMP = 4.096V 0 – 2.048V 0 – 4.096V ±1.024V ±2.048V 18523fa 11 LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 have a unique differential sampleand-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of the “+” and “–” inputs independent of the common mode voltage. The common mode rejection holds up to high frequencies. The only requirement is that both inputs can not exceed the AVDD power supply voltage or ground. When a bipolar input span is selected the “+” input can swing ± full scale relative to the “–” input but neither input can exceed AVDD or go below ground. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar offset will vary. The change in bipolar offset is typically less than 0.1% of the common mode voltage. Some AC applications may have their performance limited by distortion. Most circuits exhibit higher distortion when signals approach the supply or ground. THD will degrade as the inputs approach either power supply rail. Distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. Driving the Analog Inputs The inputs of the LTC1852/LTC1853 are easy to drive. Each of the analog inputs can be used as a single-ended input relative to the input common pin (CH0-COM, CH1-COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differential inputs. Regardless of the MUX configuration, the “+” and “–” inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1852/LTC1853 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be less than 150ns for full throughput rate). Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (