LTC1861HMS-PBF

LTC1860/LTC1861 µPower, 12-Bit, 250ksps 1- and 2-Channel ADCs in MSOP FEATURES n n n n n n n n n n DESCRIPTION The LTC®1860/LTC1861 are 12-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 5V supply. At 250ksps, the supply current is only 850μA. The supply current drops at lower speeds because the LTC1860/LTC1861 automatically power down to a typical supply current of 1nA between conversions. These 12-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1860 has a differential analog input with an adjustable reference pin. The LTC1861 offers a software-selectable 2-channel MUX and an adjustable reference pin on the MSOP version. The 3-wire, serial I/O, MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 12-Bit 250ksps ADCs in MSOP Package Single 5V Supply Low Supply Current: 850μA (Typ) Auto Shutdown Reduces Supply Current to 2μA at 1ksps True Differential Inputs 1-Channel (LTC1860) or 2-Channel (LTC1861) Versions SPI/MICROWIRETM Compatible Serial I/O High Speed Upgrade to LTC1286/LTC1298 Pin Compatible with 16-Bit LTC1864/LTC1865 Guaranteed Operation to 125°C (MSOP Package) APPLICATIONS n n n n High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition TYPICAL APPLICATION Single 5V Supply, 250ksps, 12-Bit Sampling ADC 1F 5V 100 LTC1860 1 2 ANALOG INPUT 0V TO 5V 3 4 VREF IN+ IN– GND VCC SCK SDO CONV 8 7 6 5 1860 TA01 Supply Current vs Sampling Frequency 1000 SUPPLY CURRENT ( A) 10 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS 1 0.1 0.01 0.01 0.1 10 100 1 SAMPLING FREQUENCY (kHz) 1000 1860 TA02 18601fa 1 LTC1860/LTC1861 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) .................................................7V Ground Voltage Difference AGND, DGND LTC1861 MSOP Package .............±0.3V Analog Input ....................(GND – 0.3V) to (VCC + 0.3V) Digital Input .................................... (GND – 0.3V) to 7V Digital Output ................... (GND – 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 400mW Operating Temperature Range LTC1860C/LTC1861C ...............................0°C to 70°C LTC1860I/LTC1861I .......................... – 40°C to 85°C LTC1860H/LTC1861H.........................–40°C to 125°C Storage Temperature Range...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................300°C PIN CONFIGURATION LTC1860 VREF IN+ IN¯ GND 1 2 3 4 TOP VIEW 8 7 6 5 VCC SCK SDO CONV LTC1861 CONV CH0 CH1 AGND DGND 1 2 3 4 5 TOP VIEW 10 9 8 7 6 VREF VCC SCK SDO SDI MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 210°C/W MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 210°C/W LTC1860 VREF 1 IN+ 2 IN– 3 TOP VIEW 8 VCC 7 SCK 6 SDO 5 CONV LTC1861 CONV 1 CH0 2 CH1 3 GND 4 TOP VIEW 8 VCC 7 SCK 6 SDO 5 SDI GND 4 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W 18601fa 2 LTC1860/LTC1861 ORDER INFORMATION LEAD FREE FINISH LTC1860CMS8#PBF LTC1860IMS8#PBF LTC1860HMS8#PBF LTC1860CS8#PBF LTC1860IS8#PBF LTC1861CMS#PBF LTC1861IMS#PBF LTC1861HMS#PBF LTC1861CS8#PBF LTC1861IS8#PBF LEAD BASED FINISH LTC1860CMS8 LTC1860IMS8 LTC1860HMS8 LTC1860CS8 LTC1860IS8 LTC1861CMS LTC1861IMS LTC1861HMS LTC1861CS8 LTC1861IS8 TAPE AND REEL LTC1860CMS8#TRPBF LTC1860IMS8#PBF LTC1860HMS8#PBF LTC1860CS8#PBF LTC1860IS8#PBF LTC1861CMS#PBF LTC1861IMS#PBF LTC1861HMS#PBF LTC1861CS8#PBF LTC1861IS8#PBF TAPE AND REEL LTC1860CMS8 LTC1860IMS8 LTC1860HMS8 LTC1860CS8 LTC1860IS8 LTC1861CMS LTC1861IMS LTC1861HMS LTC1861CS8 LTC1861IS8 PART MARKING LTWR LTWS LTWS 1860 1860I LTWT LTWU LTWU 1861 1861I PART MARKING LTWR LTWS LTWS 1860 1860I LTWT LTWU LTWU 1861 1861I PACKAGE DESCRIPTION 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO PACKAGE DESCRIPTION 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 18601fa 3 LTC1860/LTC1861 CONVERTER AND MULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL Resolution No Missing Codes Resolution INL Transition Noise Gain Error Offset Error Input Differential Voltage Range Absolute Input Range VREF Input Range Analog Input Leakage Current CIN Input Capacitance LTC1860 SO-8 and MSOP LTC1861 MSOP , LTC1861 SO-8 VIN = IN+ – IN– IN+ Input IN– Input LTC1860 SO-8 and MSOP LTC1861 MSOP , (Note 4) In Sample Mode During Conversion l l l l l CONDITIONS l l l MIN 12 12 TYP MAX UNITS Bits Bits (Note 3) ±1 0.07 ±20 ±2 ±3 0 –0.05 –0.05 1 12 5 ±5 ±7 VREF VCC + 0.05 VCC/2 VCC ±1 LSB LSBRMS mV mV mV V V V V μA pF pF DYNAMIC ACCURACY TA = 25°C. VCC = 5V, fSAMPLE = 250kHz, unless otherwise specified. SYMBOL SNR S/(N + D) THD PARAMETER Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Ratio Total Hamonic Distortion Up to 5th Harmonic Full Power Bandwidth Full Linear Bandwidth S/(N + D) ≥ 68dB 100kHz Input Signal 100kHz Input Signal CONDITIONS MIN TYP 72 71 77 20 125 MAX UNITS dB dB dB MHz kHz DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL VIH VIL IIH IIL VOH VOL PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10μA VCC = 4.75V, IO = 360μA VCC = 4.75V, IO = 1.6mA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. MIN l l l l l l l TYP MAX 0.8 2.5 –2.5 UNITS V V μA μA V V 2.4 4.5 2.4 4.74 4.72 0.4 V 18601fa 4 LTC1860/LTC1861 DIGITAL AND DC ELECTRICAL CHARACTERISTICS SYMBOL IOZ ISOURCE ISINK IREF ICC PARAMETER Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current (LTC1860 SO-8, MSOP and LTC1861 MSOP) Supply Current CONDITIONS CONV = VCC VOUT = 0V VOUT = VCC CONV = VCC fSMPL = fSMPL(MAX) CONV = VCC After Conversion CONV = VCC After Conversion, H-Grade fSMPL = fSMPL(MAX) fSMPL = fSMPL(MAX) l l l l l l The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. MIN TYP –25 20 0.001 0.05 0.001 0.001 0.85 1.25 3 0.1 3 5 1.3 MAX ±3 UNITS μA mA mA μA mA μA μA mA mV PD Power Dissipation RECOMMENDED OPERATING CONDITIONS the full operating temperature range, otherwise specifications are TA = 25°C. PARAMETER Supply Voltage Clock Frequency H-Grade tCYC tSMPL tsuCONV thDI tsuDI tWHCLK tWLCLK tWHCONV tWLCONV thCONV Total Cycle Time Analog Input Sampling Time Setup Time CONV↓ Before First SCK↑, (See Figure 1) Holdtime SDI After SCK↑ Setup Time SDI Stable Before SCK↑ SCK High Time SCK Low Time CONV High Time Between Data Transfer Cycles CONV Low Time During Data Transfer Hold Time CONV Low After Last SCK↑ LTC1860 (Note 5) LTC1861 (Note 5) H-Grade LTC1861 LTC1861 fSCK = fSCK(MAX) fSCK = fSCK(MAX) (Note 5) (Note 5) CONDITIONS SYMBOL VCC fSCK The ● denotes specifications which apply over MIN 4.75 l l TYP MAX 5.25 20 16.7 UNITS V MHz MHz μs SCK SCK 12 • SCK + tCONV 12 10 60 65 15 15 40% 40% tCONV 12 13 30 30 ns ns ns ns 1/fSCK 1/fSCK μs SCK ns 18601fa 5 LTC1860/LTC1861 TIMING CHARACTERISTICS SYMBOL tCONV fSMPL(MAX) tdDO PARAMETER Conversion Time (See Figure 1) H-Grade Maximum Sampling Frequency H-Grade Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF H-Grade , H-Grade ten thDO tr tf Delay Time, CONV↓ to SDO Enabled Time Output Data Remains Valid After SCK↓ SDO Rise Time SDO Fall Time CLOAD = 20pF CLOAD = 20pF H-Grade , CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. CONDITIONS l l l l l l l l l l l MIN TYP 2.75 2.75 MAX 3.2 3.3 UNITS μs μs kHz kHz 250 248 15 20 25 30 60 65 60 65 ns ns ns ns ns ns ns ns ns ns tdis Delay Time, CONV↑ to SDO Hi-Z 30 30 30 30 5 10 8 4 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Guaranteed by design, not subject to test. 18601fa 6 LTC1860/LTC1861 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Sampling Frequency 1000 CONV LOW = 800ns TA = 25 C VCC = 5V SUPPLY CURRENT ( A) 1000 Supply Current vs Temperature 1000 900 800 SLEEP CURRENT (nA) 800 700 600 500 400 300 200 100 Sleep Current vs Temperature CONV = VCC = 5V 100 SUPPLY CURRENT ( A) 10 600 1 400 CONV HIGH = 3.2 S fSMPL = 250kHz VCC = 5V VREF = 5V –25 50 25 0 75 TEMPERATURE ( C) 100 125 0.1 200 0.01 0.01 0.1 10 100 1.0 SAMPLING FREQUENCY (kHz) 1000 1860/61 G01 0 –50 0 –50 –25 50 25 0 75 TEMPERATURE ( C) 100 125 1860/61 G02 1860/61 G03 Reference Current vs Sample Rate 60 50 REFERENCE CURRENT ( A) 40 30 20 10 0 CONV IS LOW FOR 800ns TA = 25 C VCC = 5V VREF = 5V 55 Reference Current vs Temperature fS = 250kHz 54 VCC = 5V = 5V V 53 REF 52 IREF ( A) –25 50 25 0 75 TEMPERATURE ( C) 100 125 51 50 49 48 47 46 60 Reference Current vs Reference Voltage fS = 250kHz TA = 25 C 50 VCC = 5V 40 30 20 10 0 REFERENCE CURRENT ( A) 250 1860/61 G04 0 50 100 150 200 SAMPLE RATE (kHz) 45 –50 0 1 2 3 VREF (V) 4 5 1860/61 G06 1860/61 G05 Typical INL Curve 1.0 TA = 25 C VCC = 5V VREF = 5V DNL EOC ERROR (LSBs) 1.0 Typical DNL Curve TA = 25 C VCC = 5V VREF = 5V 100 Analog Input Leakage vs Temperature VCC = 5V VREF = 5V CONV = 0V ANALOG INPUT LEAKAGE (nA) INL COC ERROR (LSBs) 0.5 0.5 75 0 0 50 –0.5 –0.5 25 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1860/61 G07 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 1860/61 G07 0 –50 –25 0 25 50 75 100 125 TEMPERATURE ( C) 1860/61 G09 18601fa 7 LTC1860/LTC1861 TYPICAL PERFORMANCE CHARACTERISTICS Change in Offset Error vs Reference Voltage 5 4 CHANGE IN OFFSET ERROR (LSB) 3 2 1 0 –1 –2 –3 –4 –5 0 1 3 4 2 REFERENCE VOLTAGE (V) 5 1860/61 G10 Change in Offset vs Temperature TA = 25 C VCC = 5V CHANGE IN OFFSET (LSB) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –50 –25 50 25 0 75 TEMPERATURE ( C) 100 125 VCC = 5V CHANGE IN GAIN ERROR (LSB) 5 Change in Gain Error vs Reference Voltage VCC = 5V 4 TA = 25 C 3 2 1 0 –1 –2 –3 –4 –5 0 1 4 3 2 REFERENCE VOLTAGE(V) 5 1860/61 G12 1860/61 G11 Change in Gain Error vs Temperature 1.0 0.8 CHANGE IN GAIN ERROR (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –50 –25 50 25 0 75 TEMPERATURE ( C) 100 125 SIGNAL-TO-(NOISE + DISTORTION) (dB) VCC = 5V VREF = 5V 80 70 60 50 40 30 20 10 Signal-to-(Noise + Distortion) vs Input Level fIN = 10kHz TA = 25 C VCC = 5V AMPLITUDE (dB) 0 –20 –40 –60 –80 4096 Point FFT fS = 204.1kHz fIN = 99.5kHz TA = 25 C VCC = 5V –100 –120 0 –40 –35 –30 –25 –20 –15 –10 INPUT LEVEL (dB) –5 0 0 10 20 30 40 50 60 70 80 90 100 f (kHz) 1860/61 G15 1860/61 G13 1195 G20 Signal-to-(Noise + Distortion) vs fIN 100 SIGNAL-TO-(NOISE + DISTORTION) (dB) 90 80 70 60 50 40 30 20 10 0 1 10 100 fIN (kHz) 1000 10000 1860/61 G16 SPURIOUS FREE DYNAMIC RANGE (dB) TOTAL HARMONIC DISTORTION (dB) TA = 25 C VCC = 5V VIN = 0dB SNR 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 Total Harmonic Distortion vs fIN TA = 25 C VCC = 5V VIN = 0dB 100 90 80 70 60 50 40 30 20 10 0 Spurious Free Dynamic Range vs fIN SINAD –100 TA = 25 C VCC = 5V VIN = 0dB 1 10 fIN (kHz) 100 1000 1860/61 G18 1 10 fIN (kHz) 100 1000 1860/61 G17 18601fa 8 LTC1860/LTC1861 PIN FUNCTIONS LTC1860 VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. IN +, IN– (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. LTC1861 (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. LTC1861 (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. 18601fa 9 LTC1860/LTC1861 FUNCTIONAL BLOCK DIAGRAM VCC PIN NAMES IN PARENTHESES REFER TO LTC1861 CONV (SDI) SCK CONVERT CLK BIAS AND SHUTDOWN DATA IN SERIAL PORT SDO 12-BITS IN+ (CH0) IN– (CH1) + – 12-BIT SAMPLING ADC DATA OUT 1860/61 BD GND VREF TEST CIRCUITS Load Circuit for tdDO, tr, tf, tdis and ten TEST POINT Voltage Waveforms for SDO Rise and Fall Times, tr, tf SDO VOH VOL SDO 3k 20pF VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1 1860 TC01 tr tf 1860 TC04 Voltage Waveforms for ten CONV CONV 1860 TC03 Voltage Waveforms for tdis VIH SDO ten SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2) 90% Voltage Waveforms for SDO Delay Times, tdDO and thDO SCK VIL tdDO thDO SDO 1860 TC02 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 1860 TC05 VOH VOL 18601fa 10 LTC1860/LTC1861 APPLICATIONS INFORMATION tsuCONV CONV tCONV SLEEP MODE 1 SCK 2 3 4 5 tSMPL 6 7 8 9 10 11 12 SDO Hi-Z B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER Figure 1. LTC1860 Operating Sequence 111111111111 111111111110 1F VCC • • • 000000000001 000000000000 0V 1LSB VREF – 1LSB VREF VREF – 2LSB *VIN = IN+ – IN– VIN* VIN = 0V TO VCC LTC1860 1 2 3 4 1860 F02 VREF IN+ IN– GND VCC SCK SDO CONV 8 7 6 5 1860 F03 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS Figure 2. LTC1860 Transfer Curve Figure 3. LTC1860 with Rail-to-Rail Input Span LTC1860 OPERATION Operating Sequence The LTC1860 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1860 goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1860 goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. Analog Inputs The LTC1860 has a unipolar differential analog input. The converter will measure the voltage between the “IN + ” and “IN–” inputs. A zero code will occur when IN+ minus IN– equals zero. Full scale occurs when IN+ minus IN– equals VREF minus 1LSB. See Figure 2. Both the “IN+” and “IN–” inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If “IN–” is grounded and VREF is tied to VCC, a rail-to-rail input span will result on “IN+” as shown in Figure 3. Reference Input The voltage on the reference input of the LTC1860 (and the LTC1861 MSOP package) defines the full-scale range of the A/D converter. These ADCs can operate with reference voltages from VCC to 1V. 18601fa 11 LTC1860/LTC1861 APPLICATIONS INFORMATION CONV tCONV SLEEP MODE tSMPL SDI DON’T CARE S/D O/S 1 2 3 4 5 DON’T CARE 6 7 8 9 10 11 12 SCK SDO Hi-Z B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1860 F04 Figure 4. LTC1861 Operating Sequence 111111111111 111111111110 • • • 000000000001 000000000000 0V 1LSB VCC VCC – 1LSB VCC – 2LSB VIN* Table 1. Multiplexer Channel Selection MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + – – + GND – – *VIN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) REFER TO TABLE 1 1860 F05 SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE 186465 TBL1 Figure 5. LTC1861 Transfer Curve LTC1861 OPERATION Operating Sequence The LTC1861 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1861 goes into sleep mode. The LTC1861’s 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND (or AGND). A zero code will occur when the “+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF minus 1LSB. See Figure 5. Both the “+” and “–” inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the “–” input in differential mode is grounded, a rail-to-rail input span will result on the “+” input. 18601fa 12 LTC1860/LTC1861 APPLICATIONS INFORMATION Reference Input The reference input of the LTC1861 SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1861 MSOP package defines the span of the A/D converter. The LTC1861 MSOP package can operate with reference voltages from 1V to VCC. GENERAL ANALOG CONSIDERATIONS Grounding The LTC1860/LTC1861 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1861 MSOP package and GND for the LTC1860 and LTC1861 SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1μF tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1860/LTC1861 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200Ω or high speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. 18601fa 13 LTC1860/LTC1861 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 0.102 (.118 .004) (NOTE 3) 0.52 (.0205) REF 0.889 (.035 0.127 .005) 8 7 65 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) GAUGE PLANE 0.254 (.010) DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.42 0.038 (.0165 .0015) TYP 0.65 (.0256) BSC DETAIL “A” 0.18 (.007) 1 23 4 0.53 0.152 (.021 .006) RECOMMENDED SOLDER PAD LAYOUT 1.10 (.043) MAX 0.86 (.034) REF SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) BSC 0.1016 (.004 0.0508 .002) MSOP (MS8) 0307 REV F MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 0.102 (.118 .004) (NOTE 3) 0.889 (.035 0.127 .005) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) GAUGE PLANE 0.254 (.010) DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 12345 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.18 (.007) 0.53 0.152 (.021 .006) DETAIL “A” 1.10 (.043) MAX 0.86 (.034) REF SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MS) 0307 REV E 18601fa 14 LTC1860/LTC1861 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 8 7 6 5 .045 .005 .050 BSC .245 MIN .160 .005 .228 – .244 (5.791 – 6.197) .150 – .157 (3.810 – 3.988) NOTE 3 .030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 45 (0.254 – 0.508) .008 – .010 (0.203 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 0 – 8 TYP 1 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0303 18601fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1860/LTC1861 TYPICAL APPLICATION Sample Two Channels Simultaneously with a Single Input ADC 0.1 F 5V f1 (0V TO 0.66V) 4.096V REF 28.7k + 1/2 LT1492 5k 100 100pF 20k 8 VCC IN+ IN– 3 0.1 F 100 100pF 4.096V REF 0.1 F 1F – 5pF 0.1 F 1 REF 7 SCK 6 LTC1860 SDO 5 CONV GND 4 1F 10k 10k 1F 5k 0.1 F f2 (0V TO 2V) 5V 2 + – 8 1/2 LT1492 4 1860 TA03 RELATED PARTS PART NUMBER 12-Bit Serial I/o ADCs LTC1286/LTC1298 LTC1400 LTC1401 LTC1402 LTC1404 14-Bit Serial I/O ADCs LTC1417 LTC1418 16-Bit Serial I/O ADCs LTC1609 LTC1864/LTC1865 References LT1460 LT1790 Micropower Precision Series Reference Micropower Low Dropout Reference Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23 60μA Supply Current, 10ppm/°C, SOT-23 200ksps 250ksps 65mW 4.25mW Configurable Bipolar or Unipolar Input Ranges, 5V SO-8, MS8, 1-Channel, 5V/SO-8, MS10, 2-Channel, 5V 400ksps 200ksps 20mW 15mW 16-Pin SSOP Unipolar or Bipolar, Reference, 5V , Serial/Parallel I/O, Internal Reference, 5V 12.5ksps/11.1ksps 400ksps 200ksps 2.2Msps 600ksps 1.3mW/1.7mW 75mW 15mW 90mW 25mW 1-Channel with Ref. Input (LTC1286), 2-Channel (LTC1298), 5V 1-Channel, Bipolar or Unipolar Operation, Internal Reference, 5V SO-8 with Internal Reference, 3V Serial I/O, Bipolar or Unipolar, Internal Reference SO-8 with Internal Reference, Bipolar or Unipolar, 5V SAMPLE RATE POWER DISSIPATION DESCRIPTION 18601fa 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1207 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007