LTC1864AIMS8

LTC1864/LTC1865 µPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 16-Bit 250ksps ADCs in MSOP Package Single 5V Supply Low Supply Current: 850µA (Typ) Auto Shutdown Reduces Supply Current to 2µA at 1ksps True Differential Inputs 1-Channel (LTC1864) or 2-Channel (LTC1865) Versions SPI/MICROWIRETM Compatible Serial I/O 16-Bit Upgrade to 12-Bit LTC1286/LTC1298 Pin Compatible with 12-Bit LTC1860/LTC1861 The LTC®1864/LTC1865 are 16-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 5V supply. At 250ksps, the supply current is only 850µA. The supply current drops at lower speeds because the LTC1864/LTC1865 automatically power down between conversions. These 16-bit switched capacitor successive approximation ADCs include sample-and-holds. The LTC1864 has a differential analog input with an adjustable reference pin. The LTC1865 offers a softwareselectable 2-channel MUX and an adjustable reference pin on the MSOP version. The 3-wire, serial I/O, small MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. APPLICATIO S ■ ■ ■ ■ High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition TYPICAL APPLICATIO Supply Current vs Sampling Frequency Single 5V Supply, 250ksps, 16-Bit Sampling ADC 1µF 5V 1000 100 SUPPLY CURRENT (µA) 10 LTC1864 1 2 ANALOG INPUT 0V TO 5V 3 4 VREF IN + IN – GND VCC SCK SDO CONV 8 7 6 5 1864 TA01 1 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS 0.1 0.01 0.01 U 0.1 10 100 1 SAMPLING FREQUENCY (kHz) 1000 1864 TA02 U U sn18645 18645fs 1 LTC1864/LTC1865 ABSOLUTE AXI U RATI GS Supply Voltage (VCC) ................................................. 7V Ground Voltage Difference AGND, DGND LTC1865 MSOP Package ........... ±0.3V Analog Input ............... (GND – 0.3V) to (VCC + 0.3V) Digital Input ................................ (GND – 0.3V) to 7V Digital Output .............. (GND – 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 400mW PACKAGE/ORDER I FOR ATIO TOP VIEW VREF IN + IN¯ GND 1 2 3 4 8 7 6 5 VCC SCK SDO CONV ORDER PART NUMBER TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP LTC1864CMS8 LTC1864IMS8 LTC1864ACMS8 LTC1864AIMS8 MS8 PART MARKING LTHQ ORDER PART NUMBER TJMAX = 150°C, θJA = 210°C/W TOP VIEW VREF 1 IN + 2 IN – 3 GND 4 8 VCC 7 SCK 6 SDO 5 CONV LTC1864CS8 LTC1864IS8 LTC1864ACS8 LTC1864AIS8 S8 PART MARKING 1864 1864I 1864A 1864AI S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER A D PARAMETER Resolution No Missing Codes Resolution INL Transition Noise Gain Error ULTIPLEXER CHARACTERISTICS LTC1864/LTC1865 MIN TYP MAX ● ● The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. CONDITIONS LTC1864A/LTC1865A MIN TYP MAX 16 15 ±8 1.1 ● (Note 3) 2 U U W WW U WU W (Notes 1, 2) Operating Temperature Range LTC1864C/LTC1865C/ LTC1864AC/LTC1865AC ........................ 0°C to 70°C LTC1864I/LTC1865I/ LTC1864AI/LTC1865AI ..................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER CONV CH0 CH1 AGND DGND 1 2 3 4 5 10 9 8 7 6 VREF VCC SCK SDO SDI MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 210°C/W LTC1865CMS LTC1865IMS LTC1865ACMS LTC1865AIMS MS PART MARKING LTHS ORDER PART NUMBER TOP VIEW CONV 1 CH0 2 CH1 3 GND 4 8 VCC 7 SCK 6 SDO 5 SDI LTC1865CS8 LTC1865IS8 LTC1865ACS8 LTC1865AIS8 S8 PART MARKING 1865 1865I 1865A 1865AI S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W U UNITS Bits Bits 16 14 ● ±6 1.1 ± 20 LSB LSBRMS mV ± 20 sn18645 18645fs LTC1864/LTC1865 CO VERTER A D PARAMETER Offset Error Input Differential Voltage Range Absolute Input Range VREF Input Range Analog Input Leakage Current CIN Input Capacitance The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. CONDITIONS LTC1864 SO-8 and MSOP, LTC1865 MSOP ● LTC1865 SO-8 ● VIN = IN + – IN – IN + Input IN – Input LTC1864 SO-8 and MSOP, LTC1865 MSOP (Note 4) In Sample Mode During Conversion ● ● DY A IC ACCURACY TA = 25°C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted. SYMBOL PARAMETER SNR Signal-to-Noise Ratio 10kHz Input Signal 100kHz Input Signal S/(N + D) Signal-to-Noise Plus Distortion Ratio THD CONDITIONS LTC1864/LTC1865 MIN TYP MAX 87 83 76 88 77 20 S/(N + D) ≥ 75dB 125 UNITS dB dB dB dB dB MHz kHz Total Hamonic Distortion Up to 5th Harmonic 10kHz Input Signal 100kHz Input Signal Full Power Bandwidth Full Linear Bandwidth DIGITAL A D DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PD High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current (LTC1864 SO-8 and MSOP, LTC1865 MSOP) Supply Current Power Dissipation CONDITION VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10µA VCC = 4.75V, IO = 360µA VCC = 4.75V, IO = 1.6mA CONV = VCC VOUT = 0V VOUT = VCC CONV = VCC fSMPL = fSMPL(MAX) CONV = VCC After Conversion fSMPL = fSMPL(MAX) fSMPL = fSMPL(MAX) The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted. LTC1864/LTC1865 MIN TYP MAX ● ● ● ● ● ● ● ● WU U WU U ULTIPLEXER CHARACTERISTICS LTC1864/LTC1865 MIN TYP MAX ±2 ±3 0 – 0.05 – 0.05 1 ±5 ±7 VREF VCC + 0.05 VCC /2 VCC ±1 12 5 12 5 0 – 0.05 – 0.05 1 LTC1864A/LTC1865A MIN TYP MAX ±2 ±3 ±5 ±7 VREF VCC + 0.05 VCC /2 VCC ±1 UNITS mV mV V V V V µA pF pF UNITS V V µA µA V V 2.4 0.8 2.5 – 2.5 4.5 2.4 4.74 4.72 0.4 ±3 – 25 20 V µA mA mA ● ● ● ● 0.001 0.05 0.001 0.85 4.25 3 0.1 3 1.3 µA mA µA mA mW sn18645 18645fs 3 LTC1864/LTC1865 RECO VCC fSCK tCYC tSMPL tsuCONV thDI tsuDI tWHCLK tWLCLK tWHCONV tWLCONV thCONV full operating temperature range, otherwise specifications are TA = 25°C. CONDITIONS E DED OPERATI G CO DITIO S SYMBOL PARAMETER Supply Voltage Clock Frequency Total Cycle Time Analog Input Sampling Time Setup Time CONV↓ Before First SCK ↑ (See Figure 1) Hold Time SDI After SCK ↑ Setup Time SDI Stable Before SCK ↑ SCK High Time SCK Low Time CONV High Time Between Data Transfer Cycles CONV Low Time During Data Transfer Hold Time CONV Low After Last SCK ↑ LTC1864 LTC1865 LTC1865 LTC1865 fSCK = fSCK(MAX) fSCK = fSCK(MAX) The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. SYMBOL tCONV tdDO tdis ten thDO tr tf PARAMETER Conversion Time (See Figure 1) Delay Time, SCK↓ to SDO Data Valid Delay Time, CONV↑ to SDO Hi-Z Delay Time, CONV↓ to SDO Enabled Time Output Data Remains Valid After SCK↓ SDO Rise Time SDO Fall Time CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CONDITIONS ● ● ● ● ● ● TI I G CHARACTERISTICS fSMPL(MAX) Maximum Sampling Frequency Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 4: Channel leakage current is measured while the part is in sample mode. 4 U U U U WW The ● denotes specifications which apply over the LTC1864/LTC1865 MIN TYP MAX 4.75 ● UNITS V MHz µs SCK SCK ns ns ns 1/fSCK 1/fSCK µs SCK ns 5.25 20 DC 16 • SCK + tCONV 16 14 30 15 15 40% 40% tCONV 16 13 UW LTC1864/LTC1865 MIN TYP MAX 2.75 250 15 30 30 5 10 8 4 20 25 60 60 3.2 UNITS µs kHz ns ns ns ns ns ns ns sn18645 18645fs LTC1864/LTC1865 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Sampling Frequency 1000 VCC = 5V TA = 25°C CONV LOW = 800ns 1000 100 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) SLEEP CURRENT (nA) 10 1 0.1 0.01 0.01 0.1 10 100 1.0 SAMPLING FREQUENCY (kHz) Reference Current vs Sampling Rate 60 50 VCC = 5V TA = 25°C VREF = 5V CONV LOW = 800ns REFERENCE CURRENT (µA) REFERENCE CURRENT (µA) 40 30 20 10 0 52 51 50 49 48 47 46 REFERENCE CURRENT (µA) 0 50 100 150 200 SAMPLE RATE (kHz) Typical INL Curve 4 VCC = 5V TA = 25°C VREF = 5V 2 DNL ERROR (LSBs) INL ERROR (LSBs) ANALOG INPUT LEAKAGE (nA) 0 –2 –4 0 16384 32768 CODE 49152 UW 1864/65 G01 1864/65 G04 Supply Current vs Temperature 1000 900 800 Sleep Current vs Temperature CONV = VCC = 5V 800 700 600 500 400 300 200 100 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 600 400 VCC = 5V VREF = 5V fSAMPLE = 250kHz CONV HIGH = 3.2µS –25 50 25 0 75 TEMPERATURE (°C) 100 125 200 1000 0 –50 1864/65 G02 1864/65 G03 Reference Current vs Temperature 55 VCC = 5V 54 VREF = 5V f = 250kHz 53 S 60 50 40 30 20 10 0 Reference Current vs Reference Voltage VCC = 5V TA = 25°C fS = 250kHz 250 45 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 1 2 3 VREF (V) 4 5 1864/65 G06 1864/65 G05 Typical DNL Curve 2 100 Analog Input Leakage Current vs Temperature VCC = 5V VREF = 5V CONV = 0V VCC = 5V TA = 25°C VREF = 5V 1 75 0 50 –1 25 65536 1864/65 G07 –2 0 16384 32768 CODE 49152 65536 1864/65 G08 0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 1864/65 G09 sn18645 18645fs 5 LTC1864/LTC1865 TYPICAL PERFOR A CE CHARACTERISTICS Change in Offset Error vs Reference Voltage 75 CHANGE IN OFFSET ERROR (LSB) CHANGE IN OFFSET (LSB) 3 2 1 0 –1 –2 –3 –4 CHANGE IN GAIN ERROR (LSB) 50 25 0 –25 0 1 3 4 2 REFERENCE VOLTAGE (V) Change in Gain Error vs Temperature 5 4 CHANGE IN GAIN ERROR (LSB) VCC = 5V VREF = 5V 3 2 1 0 –1 –2 –3 –4 –5 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 FREQUENCY AMPLITUDE (dB) SINAD vs Frequency 100 90 80 70 SINAD (dB) 60 50 40 30 20 10 0 1 10 FIN (kHz) 1864/5 G16 SFDR (dB) THD (dB) 100 6 UW VCC = 5V TA = 25°C 1864/65 G13 Change in Offset vs Temperature 5 VCC = 5V 4 VREF = 5V 20 Change in Gain Error vs Reference Voltage VCC = 5V 15 TA = 25°C 10 5 0 –5 –10 –15 5 1864/65 G10 –5 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 –20 0 1 4 3 2 REFERENCE VOLTAGE(V) 5 1864/65 G12 1864/65 G11 Histogram of 4096 Conversions of a DC Input Voltage 1800 1600 1400 1200 1000 800 600 400 200 0 0 0 0 1 CODE 2 127 12 3 0 4 0 5 –4 –3 –2 –1 –120 –140 729 516 1178 1534 VCC = 5V TA = 25°C VREF = 5V 0 –20 –40 –60 –80 4096 Point FFT Nonaveraged fS = 203.125kHz fIN = 99.72763kHz VCC = 5V VREF = 5V TA = 25°C –100 0 20 40 60 80 FREQUENCY (kHz) 100 120 1864/65 G14 1864/65 G15 THD vs Frequency 0 SNR –10 –20 SINAD –30 –40 –50 –60 –70 VCC = 5V VREF = 5V TA = 25°C VIN = 0dB 1000 –80 –90 –100 1 10 FIN (kHz) 1864/5 G17 SFDR vs Frequency 100 90 80 70 60 50 40 30 VCC = 5V VREF = 5V TA = 25°C VIN = 0dB 1 10 FIN (kHz) 1864/5 G18 VCC = 5V VREF = 5V TA = 25°C VIN = 0dB 100 1000 20 10 0 100 1000 sn18645 18645fs LTC1864/LTC1865 PI FU CTIO S LTC1864 VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. IN +, IN– (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers LTC1865 (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. LTC1865 (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. sn18645 18645fs U U U down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. 7 LTC1864/LTC1865 FUNCTIONAL BLOCK DIAGRA PIN NAMES IN PARENTHESES REFER TO LTC1865 CONVERT CLK IN (CH0) + IN – (CH1) GND TEST CIRCUITS Load Circuit for t dDO, t r, t f, t dis and t en TEST POINT 3k SDO 20pF VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1 1864 TC01 Voltage Waveforms for t en CONV CONV SDO ten 1864 TC03 Voltage Waveforms for SDO Delay Times, t dDO and t hDO SCK VIL tdDO thDO VOH SDO VOL 1864 TC02 8 W VCC CONV (SDI) SCK BIAS AND SHUTDOWN DATA IN 16 BITS SERIAL PORT SDO U U + – 16-BIT SAMPLING ADC DATA OUT 1864/65 BD VREF Voltage Waveforms for SDO Rise and Fall Times, t r, t f VOH VOL tr tf SDO 1864 TC04 Voltage Waveforms for t dis VIH SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2) 90% 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 1864 TC05 sn18645 18645fs LTC1864/LTC1865 APPLICATIO S I FOR ATIO LTC1864 OPERATION Operating Sequence The LTC1864 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1864 goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1864 goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. CONV tCONV SLEEP MODE 1 SCK 2 3 4 5 6 7 SDO Hi-Z Figure 1. LTC1864 Operating Sequence 1µ F VCC 1111111111111111 1111111111111110 • • • 0000000000000001 0000000000000000 VIN* *VIN = IN + – IN – Figure 2. LTC1864 Transfer Curve U Analog Inputs The LTC1864 has a unipolar differential analog input. The converter will measure the voltage between the “IN + ” and “IN – ” inputs. A zero code will occur when IN+ minus IN – equals zero. Full scale occurs when IN+ minus IN – equals VREF minus 1LSB. See Figure 2. Both the “IN+ ” and “IN – ” inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If “IN – ” is grounded and VREF is tied to VCC, a rail-to-rail input span will result on “IN+ ” as shown in Figure 3. Reference Input The voltage on the reference input of the LTC1864 defines the full-scale range of the A/D converter. The LTC1864 can operate with reference voltages from VCC to 1V. t SMPL 8 9 10 11 12 13 14 15 16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1854 F01 W UU 0V 1LSB LTC1864 1 VIN = 0V TO VCC 2 3 4 VREF VREF – 1LSB VREF – 2LSB VREF IN + IN – GND VCC SCK SDO CONV 8 7 6 5 1864 F03 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS 1864 F02 Figure 3. LTC1864 with Rail-to-Rail Input Span sn18645 18645fs 9 LTC1864/LTC1865 APPLICATIO S I FOR ATIO LTC1865 OPERATION Operating Sequence The LTC1865 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1865 goes into sleep mode drawing only leakage current. The LTC1865’s 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the “+” and “–” signs in the selected row of the following table. In CONV tCONV SLEEP MODE SDI DON’T CARE SCK SDO Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY Figure 4. LTC1865 Operating Sequence 10 U single-ended mode, all input channels are measured with respect to GND. A zero code will occur when the “+” input minus the “–” input equals zero. Full scale occurs when the “+” input minus the “–” input equals VREF minus 1LSB. See Figure 5. Both the “+” and “–” inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the “–” input in differential mode is grounded, a rail-to-rail input span will result on the “+” input. Reference Input The reference input of the LTC1865 SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1865 MSOP package defines the span of the A/D converter. The LTC1865 MSOP package can operate with reference voltages from 1V to VCC. Table 1. Multiplexer Channel Selection MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + – – + GND – – SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE 1864 TBL1 W UU t SMPL S/D O/S 1 2 3 4 5 6 7 DON’T CARE 8 9 10 11 12 13 14 15 16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z 1864 F04 sn18645 18645fs LTC1864/LTC1865 APPLICATIO S I FOR ATIO GENERAL ANALOG CONSIDERATIONS Grounding The LTC1864/LTC1865 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1865 MSOP package and GND for the LTC1864 and LTC1865 SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can 1111111111111111 1111111111111110 • • • 0000000000000001 0000000000000000 VIN* *VIN = (SELECTED “+” CHANNEL) – (SELECTED “–” CHANNEL) REFER TO TABLE 1 Figure 5. LTC1865 Transfer Curve U induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1µF tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1864/ LTC1865 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200Ω or high speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins. 1LSB VCC VCC – 1LSB VCC – 2LSB 1864 F05 W UU 0V sn18645 18645fs 11 LTC1864/LTC1865 R7 51Ω 0PT C4 0.1µF RN1 330 R5 402Ω, 1% C21 47pF U8A 74AC14 R1 510Ω C7 390pF C9 180pF R6 402Ω 1% C22 47pF U8B 74AC14 U3 LTC1864CMS8 C8 1000pF OPT 1 V 2 REF IN+ 3 IN– 4 GND 8 VCC 7 SCK 6 SDO 5 CONV 1 2 3 4 8 7 6 5 C5 15V 0.1µF JP1 C3 10µF 6.3V 1206 2 + JP2 AGND – U4 5VDIG 74HC595ADT 16 QB V 15 CC QC QA 14 QD A 13 QE OENB 12 QF LCLK 11 QG SCLK 10 RESET QH 9 GND SQH 1 2 3 4 5 6 7 8 E9 APPLICATIO S I FOR ATIO IN – C11 390pF C12 1000pF OPT R8 51Ω 0PT 2 JP3 1 ANALOG GROUND PLANE 5VDIG 5VDIG C23 0.1µF C24 0.1µF 16 15 14 13 12 11 10 9 QB VCC QC QA QD A QE OENB QF LCLK QG SCLK RESET QH GND SQH 1 2 3 4 5 6 7 8 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 C15 5VDIG 0.1µF U5 74HC595ADT U9C 74AC00 U9D 74AC00 U9B 74AC00 2 U12A 74AC109 16 6 2 VCC Q J 7 3 Q K 4 CLK 1 CLR 8 5 GND PRE 5VDIG C16 0.1µF C17 0.1µF 5VDIG U12B 74AC109 16 14 10 VCC JP4 Q J 13 91 Q K 12 CLK 15 CLR 11 8 GND PRE C25 5VDIG 0.1µF E2 CONV E3 ENABLE DATA E7 DGND U8D 74AC14 U8E 74AC14 U8F 74AC14 2 JP5 1 E6 E4 E5 DGND DOUT U9A 74AC00 5VDIG 5VDIG U7 74HC163AD R12 10k 5VDIG 5VDIG 2 4 6 U6 74HC163AD C18 0.1µF 1 OUT DIV 5 1+ V 2 GND 3 SET 4 3 JP6 2 1 3 2 JP7 CLKOUT J3 CLKIN U10 LTC1799 C19 5VDIG 0.1µF R9 51Ω JP8 1 3 5 2 4 6 1 2 3 4 5 6 7 8 VCC RCO Q0 Q1 Q2 Q3 ENT LO R10 20k 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO 16 15 14 13 12 11 10 9 JP9 RESET CLK P0 P1 P2 P3 ENP GND 16 15 14 13 12 11 10 9 U8C 74AC14 U13A 74AC32 U13D 74AC32 1 3 5 CLK U13B 74AC32 U13C 74AC32 NOTES: UNLESS OTHERWISE SPECIFIED INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2; ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5. 1864/65 AI1 U J2 C6 –15V 0.1µF R2 510Ω C10 680pF OPT IN – W E8 U2 OPT 1 UU J4 3201S40G1 12 LTC1864 Evaluation Circuit Schematic 15V 1 VIN C26 10µF 6.3V 1206 3 C1 0.1µF 5VAN C2 1µF 10V 0805 VOUT GND 2 R4 2Ω C13 0.1µF C14 0.1µF 5VAN 5VDIG 5VDIG 5VDIG R3 2Ω 2 E1 15V 15V 2 VIN C27 0.1µF 6 VOUT U1 GND LT1021-5 4 J1 IN + IN + 1 sn18645 18645fs LTC1864/LTC1865 APPLICATIO S I FOR ATIO Component Side Silk Screen for LTC1864 Evaluation Circuit Component Side Showing Traces (Note Wider Traces on Analog Side) Ground Layer with Separate Analog and Digital Grounds U Bottom Side Showing Traces (Note Almost No Analog Traces on Board Bottom) Supply Layer with 5V Digital Supply and Analog Ground Repeated sn18645 18645fs W UU 13 LTC1864/LTC1865 APPLICATIO S I FOR ATIO 5VAN C3 10µF 6.3V 1206 1V to 5V REFERENCE 0V to VREF INPUT C4 0.1µF 1 V 2 REF IN+ 3 IN– 4 GND U3 LTC1864CMS8 ANALOG GROUND PLANE 5VDIG C23 0.1µF 5VDIG C24 0.1µF U9B 74AC00 U12A 74AC109 16 6 2 VCC Q J 7 3 Q K 4 CLK 1 CLR 8 5 GND PRE v U9A 74AC00 5VDIG 5VDIG C16 0.1µF 5VDIG C17 0.1µF v 5VDIG U6 74HC163AD 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO 16 15 14 13 12 11 10 9 U7 74HC163AD 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO 16 15 14 13 12 11 10 9 U10 LTC1799 100k 1+ V 2 GND 3 SET OUT DIV 5 4 v U13C 74AC32 CLK v U13B 74AC32 Figure 6. LTC1864 Manchester Transmitter 14 U U11 15V LT1121CST-5 1 VIN VOUT GND 2 5VAN 3 R4 2Ω 5VDIG C26 10µF 6.3V 1206 5VDIG 8 VCC 7 SCK 6 SDO 5 CONV RN1 330 1 2 3 4 8 7 6 5 LTC1485 1 RO 2 RE 3 DE 4 DI 8 VCC 7 B 6 A 5 GND 5VDIG 15V 120Ω 4 CONDUCTOR TELEPHONE WIRES TO RECEIVER 4 1 U12B 74AC109 16 14 10 VCC Q J 13 9 Q K 12 CLK 15 CLR 11 8 GND PRE 5V 5 MC74VHC1G66 2 500Ω 3 5VDIG 74AC74 5VDIG C18 0.1µF PRE D CLK CLR 5VDIG 74AC74 PRE D CLK CLR Q Q 74AC86 Q Q 1864/65 AI2 W UU sn18645 18645fs LTC1864/LTC1865 APPLICATIO S I FOR ATIO VCC 4 DATA IN 2 CLK 3 1 IC1A 74AC74 PRE D CLK CLR Q 5 VCC IC5C 74AC86 IC6D 74AC32 v v v Q 6 10 12 CLK 11 13 PRE D CLK CLR Q v 9 v Q 8 DATA DATA IC1B 74AC74 VCC IC4C 74AC08 10 12 CLK 11 13 IC3B 74AC74 PRE D CLK CLR Q9 8 STROBE v RECEIVE CLOCK AT 8 X TRANSMIT CLOCK FREQUENCY U1 LTC1485 1 RO 2 RE 3 DE 4 DI 8 VCC 7 B 6 A 5 GND VCC VCC 13 OPTIONAL SERIAL TO PARALLEL CONVERTER VCC 14 11 15V SUPPLY TO TRANSMITTER v 4 CONDUCTOR TELEPHONE WIRES TO TRANSMITTER R1 120Ω 13 9 DATA v Q v Figure 7. LTC1864 Manchester Receiver U VCC IC4A 74AC08 IC2A 74AC74 4 2 CLK 3 1 PRE D CLK CLR Q 5 VCC 10 12 CLK 11 13 IC2B 74AC74 PRE D CLK CLR Q 9 VCC IC4B 74AC08 4 2 CLK 3 1 IC3A 74AC74 PRE D CLK CLR Q 5 Q 6 Q 8 Q 6 IC6C 74LS32D IC4D 74AC08 Q IC8 74AC595 14 11 10 12 SER SCK SCL RCK QA QB QC QD QE QF QG QH QHIN 15 1 2 3 4 5 6 7 9 D15 D14 D13 D12 D11 D10 D9 D8 8 IC9 74AC595 SER SCK SCL RCK QA QB QC QD QE QF QG QH QHIN 15 1 2 3 4 5 6 7 9 D7 D6 D5 D4 D3 D2 D1 D0 STROBE IC7B 74AC109 11 14 12 13 15 PRE J CLK K CLR Q 10 10 12 8 1864/65 AI3 W UU sn18645 18645fs 15 LTC1864/LTC1865 APPLICATIO S I FOR ATIO Transmit LTC1864 Data Over Modular Telephone Wire Using Simple Transmitter/Receiver Figure 6 shows a simple Manchester encoder and differential transmitter suitable for use with the LTC1864. This circuit allows transmission of data over inexpensive telephone wire. This is useful for measuring a remote sensor, particularly when the cost of preserving the analog signal over a long distance is high. Manchester encoding is a clock signal that is modulated by exclusive ORing with the data signal. The resulting signal contains both clock and data information and has an average duty cycle of 50%, that also allows transformer coupling. In practice, generating a Manchester encoded signal with an XOR gate will often produce glitches due to the skew between data and clock transitions. The D flipflops in this encoder retime the clock and data such that the respective edges are closely aligned, effectively suppressing glitches. The retimed data and clock are then XORed to produce the Manchester encoded data, which is interfaced to telephone wire with an LTC1485 RS485 transceiver. In order to synchronize to incoming data, the receiver needs a sequence to indicate the start of a data word. The transmitter schematic shows logic that will produce 31 16 U zeros, a start bit, followed by the 16 data bits (one sample every 48 clock cycles) at a clock frequency of 1MHz set by the LTC1799 oscillator. Sending at least 18 zeros before each start bit ensures that if synchronization is lost, the receiver can resynchronize to a start bit under all conditions. The serial to parallel converter shown in Figure 7 requires 18 zeros to avoid triggering on data bits. The Manchester receiver shown in Figure 7 was adopted from Xilinx application note 17-30 and would typically be implemented in an FPGA. The decoder clock frequency is nominally 8 times the transmit clock frequency and is very tolerant of frequency errors. The outputs of the decoder are data and a strobe that indicates a valid data bit. The data can be deserialized using shift registers as shown. The start bit resets the J-K/flip-flop on its way into the first shift register. When it appears at the QHIN output of the second shift register, it sets the flip-flop that loads the parallel data into the output register. With AC family CMOS logic at 5V the receiver clock frequency is limited to 20MHz; the corresponding transmitter clock frequency is 2.5MHz. If the receiver is implemented in an FPGA that can be clocked at 160MHz, the LTC1864 can be clocked at its rated clock frequency of 20MHz. sn18645 18645fs W UU LTC1864/LTC1865 PACKAGE DESCRIPTIO 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.42 ± 0.04 (.0165 ± .0015) TYP 0.65 (.0256) BSC RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 0.18 (.077) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX U MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 8 7 65 0.52 (.206) REF 0.254 (.010) GAUGE PLANE 1 23 4 DETAIL “A” 0° – 6° TYP 4.88 ± 0.1 (.192 ± .004) 3.00 ± 0.102 (.118 ± .004) NOTE 4 0.53 ± 0.015 (.021 ± .006) 1.10 (.043) MAX 0.86 (.034) REF SEATING PLANE 0.22 – 0.38 (.009 – .015) 0.65 (.0256) BCS 0.13 ± 0.05 (.005 ± .002) MSOP (MS8) 1001 sn18645 18645fs 17 LTC1864/LTC1865 PACKAGE DESCRIPTIO 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.254 (.010) GAUGE PLANE 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 18 U MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF DETAIL “A” 0° – 6° TYP 4.88 ± 0.10 (.192 ± .004) 3.00 ± 0.102 (.118 ± .004) NOTE 4 12345 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.86 (.034) REF 0.17 – 0.27 (.007 – .011) 0.50 (.0197) TYP 0.13 ± 0.05 (.005 ± .002) MSOP (MS) 1001 sn18645 18645fs LTC1864/LTC1865 PACKAGE DESCRIPTIO 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 (0.406 – 1.270) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) SO8 1298 1 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC sn18645 18645fs 19 LTC1864/LTC1865 TYPICAL APPLICATIO Sample Two Channels Simultaneously with a Single Input ADC 4096 Point FFT of Output f1 (0V TO 0.66V) 4.096V REF 28.7k 10k 10k 1µF 5k 0.1µF f2 (0V TO 2V) 5V 3 0.1µF 100Ω 100pF 1860 TA03 0.1µF + 1/2 LT1492 5k – 20k 5pF 2 8 VCC IN+ IN– + – 8 1 REF 7 SCK 6 LTC1864 SDO 5 CONV GND 4 1/2 LT1492 4 AMPLITUDE (dB) RELATED PARTS PART NUMBER 14-Bit Serial I/O ADCs LTC1417 LTC1418 16-Bit Serial I/O ADCs LTC1609 References LT1460 LT1790 Op Amps LT1468/LT1469 LT1806/LT1807 LT1809/LT1810 Single/Dual 90MHz, 16-Bit Accurate Op Amps Single/Dual 325MHz Low Noise Op Amps Single/Dual 180MHz Low Distortion Op Amps 22V/µs Slew Rate, 75µV/125µV Offset 140V/µs Slew Rate, 3.5nV/√Hz Noise, – 80dBc Distortion 350V/µs Slew Rate, – 90dBc Distortion at 5MHz Micropower Precision Series Reference Micropower Low Dropout Reference Bandgap, 130µA Supply Current, 10ppm/°C, Available in SOT-23 60µA Supply Current, 10ppm/°C, SOT-23 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V 400ksps 200ksps 20mW 15mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V Serial/Parallel I/O, Internal Reference, 5V or ±5V SAMPLE RATE POWER DISSIPATION DESCRIPTION 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U 5V 4.096V REF 0.1µF 1µF 100Ω 100pF 0.1µF 1µF 0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 5 f1 = 7.507324kHz AT 530mVP-P f2 = 45.007324kHz AT 1.7VP-P fS = 100kHz 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) 1864/65 TA03b sn18645 18645fs LT/TP 0502 2K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001