LTC1865

FEATURES n n n n n n n n n n n n n n LTC2450-1 Easy-to-Use, Ultra-Tiny 16-Bit ΔΣ ADC DESCRIPTION The LTC®2450-1 is a low power, ultra-tiny 16-bit analogto-digital converter designed for space constrained applications requiring 16-bit performance. The LTC2450-1 uses a single 2.7V to 5.5V supply, accepts a single-ended analog input voltage, and communicates through an SPI interface. It includes an integrated oscillator that does not require any external components. The delta-sigma modulator converter core provides single-cycle settling time for multiplexed applications. The converter is available in a 6-pin, 2mm × 2mm DFN package. The LTC2450-1 implements a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude. The LTC2450-1 is capable of up to 60 conversions per second and, due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. The converter uses its power supply voltage as the reference voltage and the single-ended, rail-to-rail input voltage range extends from GND to VCC. Following a conversion, the LTC2450-1 can automatically enter a sleep mode and reduce its power to less than 500nA. At an output rate of 1Hz, the LTC2450-1 consumes an average of less than 25μW from a 2.7V supply. GND to VCC Single-Ended Input Range 60 Conversions Per Second 0.02LSB RMS Noise 16-Bits, No Missing Codes 0.5mV Offset Error 4LSB Full-Scale Error Single Conversion Settling Time for Multiplexed Applications Single Cycle Operation with Auto Shutdown 350μA Supply Current 50nA Sleep Current Internal Oscillator—No External Components Required Single Supply, 2.7V to 5.5V Operation SPI Interface Ultra-Tiny, 2mm × 2mm DFN Package APPLICATIONS n n n n n n n System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6208279, 6411242, 7088280, 7164378. TYPICAL APPLICATION 3.0 2.5 2.7 TO 5.5V 0.1μF 10μF INL (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 Integral Nonlinearity VCC = VREF = 3V 1k SENSE CLOSE TO CHIP VIN 0.1μF VCC LTC2450-1 GND CS SCK SDO 24501 TA01 TA = –45°C, 25°C, 90°C 3-WIRE SPI INTERFACE 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 24501 G02 24501fb 1 LTC2450-1 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW VCC 1 VIN 2 GND 3 7 6 SCK 5 SDO 4 CS Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (VIN) ............–0.3V to (VCC + 0.3V) Digital Input Voltage......................–0.3V to (VCC + 0.3V) Digital Output Voltage ...................–0.3V to (VCC + 0.3V) Operating Temperature Range LTC2450C-1 ............................................. 0°C to 70°C LTC2450I-1 .......................................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C DC PACKAGE 6-LEAD (2mm × 2mm) PLASTIC DFN TJMAX = 125°C, θJA = 102°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C LTC2450CDC-1#TRMPBF LTC2450CDC-1#TRPBF LCTR 6-Lead (2mm × 2mm) Plastic DFN LTC2450IDC-1#TRMPBF LTC2450IDC-1#TRPBF LCTR 6-Lead (2mm × 2mm) Plastic DFN TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) PARAMETER Resolution (No missing codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise l ELECTRICAL CHARACTERISTICS (Note 3) (Note 4) CONDITIONS l l l MIN 16 TYP 2 0.5 0.02 0.01 0.02 1.4 MAX 10 2 0.02 UNITS Bits LSB mV LSB/°C % of FS LSB/°C μVRMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. SYMBOL VIN CIN IDC_LEAK (VIN) ICONV PARAMETER Input Voltage Range IN Sampling Capacitance IN DC Leakage Current Input Sampling Current (Note 9) VIN = GND (Note 5) VIN = VCC (Note 5) l l CONDITIONS l MIN 0 TYP 0.35 MAX VCC UNITS pF –10 –10 1 1 50 10 10 nA nA nA 24501fb 2 LTC2450-1 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep CS = GND (Note 6) CS = VCC (Note 6) CONDITIONS l l l MIN 2.7 TYP MAX 5.5 UNITS V μA μA 350 0.05 600 0.5 The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 2) SYMBOL VIH VIL IIN CIN VOH VOL IOZ PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current IO = –800μA IO = –1.6mA l l l DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS MIN l l l TYP MAX 0.3 UNITS V V μA pF V VCC – 0.3 –10 10 VCC – 0.5 0.4 –10 10 10 V μA range,otherwise specifications are at TA = 25°C. SYMBOL tCONV fSCK tlSCK thSCK t1 t2 t3 tKQ PARAMETER Conversion Time SCK Frequency Range SCK Low Period SCK High Period CS Falling Edge to SDO Low Z CS Rising Edge to SDO High Z TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature CONDITIONS l l l l l l l l MIN 14 250 250 0 0 100 0 TYP 16.6 MAX 21 2 UNITS ms MHz ns ns (Notes 7, 8) (Notes 7, 8) (Note 7) 100 100 100 ns ns ns ns CS Falling Edge to SCK Falling Edge SCK Falling Edge to SDO Valid Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. Note 3: Guaranteed by design, not subject to test. Note 4: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Guaranteed by design, test correlation and 3 point transfer curve measurement. Note 5: CS = VCC. A positive current is flowing into the DUT pin. Note 6: SCK = VCC or GND. SDO is high impedance. Note 7: See Figure 3. Note 8: See Figure 4. Note 9: Input sampling current is the average input current drawn from the input sampling network while the LTC2450-1 is actively sampling the input. 24501fb 3 LTC2450-1 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity 3.0 2.5 2.0 1.5 1.0 INL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 24501 G01 Integral Nonlinearity 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 TA = –45°C, 25°C, 90°C INL (LSB) 5.0 VCC = VREF = 3V 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Maximum INL vs Temperature VCC = VREF = 5V VCC = 5V VCC = 4.1V VCC = 3V TA = –45°C, 25°C, 90°C 0 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 24501 G03 24501 G02 Offset Error vs Temperature 7 VCC = 4.1V 6 GAIN ERROR (LSB) 5 OFFSET (LSB) 4 3 2 1 0 –50 VCC = 5.5V VCC = 2.7V 5 4 3 Gain Error vs Temperature 3.00 2.75 TRANSITION NOISE RMS (μV) 2.50 2.25 2.00 1.75 Transition Noise vs Temperature VCC = 2.7V 2 1 0 VCC = 4.1V –1 –50 VCC = 5.5V 1.50 VCC = 4.1V 1.25 1.00 0.50 0.75 0.25 0 –50 –30 VCC = 3V VCC = 5V –25 50 25 0 TEMPERATURE (°C) 75 100 24501 G04 –25 0 25 50 TEMPERATURE (°C) 75 100 50 –10 10 30 TEMPERATURE (°C) 70 90 24501 G06 24501 G05 Transition Noise vs Output Code 3.00 2.75 TRANSITION NOISE RMS (μV) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.50 0.75 0.25 0 0.80 1.00 0.40 0.60 0 0.20 OUTPUT CODE (NORMALIZED TO FULL SCALE) 24501 G07 Conversion Mode Power Supply Current vs Temperature 500 VCC = 5V VCC = 3V 300 VCC = 4.1V TA = 25°C CONVERSION CURRENT (μA) 400 VCC = 5V VCC = 3V 200 100 0 –45 –25 35 15 –5 55 TEMPERATURE (°C) 75 95 24501 G08 24501fb 4 LTC2450-1 TYPICAL PERFORMANCE CHARACTERISTICS Sleep Mode Power Supply Current vs Temperature 250 10000 AVERAGE SUPPLY POWER (μW) Average Supply Power vs Temperature, VCC = 3V SLEEP MODE CURRENT (nA) 200 VCC = 5V 150 VCC = 4.1V 60 Hz OUTPUT SAMPLE RATE 1000 10 Hz OUTPUT SAMPLE RATE 100 100 1 Hz OUTPUT SAMPLE RATE 50 VCC = 3V 0 –45 –25 35 15 –5 55 TEMPERATURE (°C) 75 95 10 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 24501 G10 24501 G09 Conversion Period vs Temperature 22 21 CONVERSION TIME (ms) 20 VCC = 5.5V, 4.1V, 2.7V 19 18 17 16 15 –45 –25 35 15 55 –5 TEMPERATURE (°C) 75 95 24501 G11 24501fb 5 LTC2450-1 PIN FUNCTIONS VCC (Pin 1): Positive Supply Voltage and Converter Reference Voltage. Bypass to GND (Pin 3) with a 10μF capacitor in parallel with a low series inductance 0.1μF capacitor located as close to the part as possible. VIN (Pin 2): Analog Input Voltage. GND (Pin 3): Ground. Connect to a ground plane through a low impedance connection. CS (Pin 4): Chip Select (Active LOW) Digital Input. A LOW on this pin enables the SDO digital output. A HIGH on this pin places the SDO output pin in a high impedance state. SDO (Pin 5): Three-State Serial Data Output. SDO is used for serial data output during the DATA OUTPUT state and can be used to monitor the conversion status. SCK (Pin 6): Serial Clock Input. SCK synchronizes the serial data output. While digital data is available (the ADC is not in CONVERT state) and CS is LOW (ADC is not in SLEEP state) a new data bit is produced at the SDO output pin following every falling edge applied to the SCK pin. Exposed Pad (Pin 7): Ground. The Exposed Pad must be soldered to the same point as Pin 3. FUNCTIONAL BLOCK DIAGRAM VCC VCC VIN GND REF + 16 BIT ΔΣ A/D CONVERTER REF – SPI INTERFACE CS SDO SCK INTERNAL OSCILLATOR 24501 BD Figure 1. Functional Block Diagram 24501fb 6 LTC2450-1 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2450-1 is a low power, delta-sigma analog-todigital converter with a simple 3-wire interface (see Figure 1). Its operation is composed of three successive states: CONVERT, SLEEP and DATA OUTPUT. The operating cycle begins with the CONVERT state, is followed by the SLEEP state, and ends with the DATA OUTPUT state (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock input (SCK), and the active low chip select input (CS). The CONVERT state duration is determined by the LTC24501 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. After the completion of a conversion, the LTC2450-1 enters the SLEEP state and remains there until both the chip select and clock inputs are low (CS = SCK = LOW). Following this condition the ADC transitions into the DATA OUTPUT state. POWER-ON RESET While in the SLEEP state, whenever the chip select input is pulled high (CS = HIGH), the LTC2450-1’s power supply current is reduced to less than 500nA. When the chip select input is pulled low (CS = LOW), and SCK is maintained at a HIGH logic level, the LTC2450-1 will return to a normal power consumption level. During the SLEEP state, the result of the last conversion is held indefinitely in a static register. Upon entering the DATA OUTPUT state, SDO outputs the most significant bit (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2450-1 will enter the CONVERT state and initiate a new conversion cycle. Power-Up Sequence When the power supply voltage VCC applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2450-1 starts a conversion cycle and follows the succession of states described in Figure 2. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. 24501fb CONVERT SLEEP NO SCK = LOW AND CS = LOW? YES DATA OUTPUT NO 16TH FALLING EDGE OF SCK OR CS = HIGH? YES 24501 F02 Figure 2. LTC2450-1 State Transition Diagram 7 LTC2450-1 APPLICATIONS INFORMATION Ease of Use The LTC2450-1 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2450-1 includes a proprietary input sampling scheme that reduces the average input current several orders of magnitude as compared to traditional delta sigma architectures. This allows external filter networks to interface directly to the LTC2450-1. Since the average input sampling current is 50nA, an external RC lowpass filter using a 1kΩ and 0.1μF results in