LTC1871

LTC1871 Wide Input Range, No RSENSETM Current Mode Boost, Flyback and SEPIC Controller FEATURES s s s DESCRIPTIO s s s s s s s s s s s High Efficiency (No Sense Resistor Required) Wide Input Voltage Range: 2.5V to 36V Current Mode Control Provides Excellent Transient Response High Maximum Duty Cycle (92% Typ) ±2% RUN Pin Threshold with 100mV Hysteresis ±1% Internal Voltage Reference Micropower Shutdown: IQ = 10µA Programmable Operating Frequency (50kHz to 1MHz) with One External Resistor Synchronizable to an External Clock Up to 1.3 × fOSC User-Controlled Pulse Skip or Burst Mode® Operation Internal 5.2V Low Dropout Voltage Regulator Output Overvoltage Protection Capable of Operating with a Sense Resistor for High Output Voltage Applications Small 10-Lead MSOP Package The LTC®1871 is a wide input range, current mode, boost, flyback and SEPIC controller that drives an N-channel power MOSFET and requires very few external components. Intended for low to medium power applications, it eliminates the need for a current sense resistor by utilizing the power MOSFET’s on-resistance, thereby maximizing efficiency. The IC’s operating frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchronized to an external clock using the MODE/SYNC pin. Burst Mode operation at light loads, a low minimum operating supply voltage of 2.5V and a low shutdown quiescent current of 10µA make the LTC1871 ideally suited for battery-operated systems. For applications requiring constant frequency operation, Burst Mode operation can be defeated using the MODE/ SYNC pin. Higher output voltage boost, SEPIC and flyback applications are possible with the LTC1871 by connecting the SENSE pin to a resistor in the source of the power MOSFET. The LTC1871 is available in the 10-lead MSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. APPLICATIO S s s Telecom Power Supplies Portable Electronic Equipment TYPICAL APPLICATIO VIN 3.3V L1 1µH D1 90 RUN ITH RC 22k CC1 6.8nF CC2 47pF R2 37.4k 1% R1 12.1k 1% FB FREQ RT 80.6k 1% MODE/SYNC LTC1871 INTVCC GATE GND CVCC 4.7µF X5R SENSE VIN VOUT 5V 7A (10A PEAK) COUT2 22µF 6.3V X5R ×2 GND 80 EFFICIENCY (%) 70 60 50 40 30 0.001 100 + M1 COUT1 150µF 6.3V ×4 + CIN 22µF 6.3V ×2 1871 F01a CIN: TAIYO YUDEN JMK325BJ226MM COUT1: PANASONIC EEFUEOJ151R COUT2: TAIYO YUDEN JMK325BJ226MM D1: MBRB2515L L1: SUMIDA CEP125-H 1R0MH M1: FAIRCHILD FDS7760A Figure 1. High Efficiency 3.3V Input, 5V Output Boost Converter (Bootstrapped) U Efficiency of Figure 1 Burst Mode OPERATION PULSE-SKIP MODE 0.01 0.1 1 OUTPUT CURRENT (A) 10 1871 F01b U U 1 LTC1871 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW RUN ITH FB FREQ MODE/ SYNC 1 2 3 4 5 10 9 8 7 6 SENSE VIN INTVCC GATE GND VIN Voltage ............................................... – 0.3V to 36V INTVCC Voltage ........................................... – 0.3V to 7V INTVCC Output Current ........................................ 50mA GATE Voltage ........................... – 0.3V to VINTVCC + 0.3V ITH, FB Voltages ....................................... – 0.3V to 2.7V RUN, MODE/SYNC Voltages ....................... – 0.3V to 7V FREQ Voltage ............................................– 0.3V to 1.5V SENSE Pin Voltage ................................... – 0.3V to 36V Operating Temperature Range (Note 2) .. – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C LTC1871EMS MS PACKAGE 10-LEAD PLASTIC MSOP MS PART MARKING LTSX TJMAX = 125°C, θJA = 120°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VIN(MIN) IQ PARAMETER Minimum Input Voltage Input Voltage Supply Current Continuous Mode Burst Mode Operation, No Load Shutdown Mode Rising RUN Input Threshold Voltage Falling RUN Input Threshold Voltage The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. CONDITIONS MIN 2.5 (Note 4) VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V VMODE/SYNC = 0V, VITH = 0.2V (Note 5) VRUN = 0V 1.223 1.198 50 VITH = 0.2V (Note 5) q TYP MAX UNITS V Main Control Loop 550 250 10 1.348 1.248 100 1 1.218 1.212 1.230 18 0.002 q q 1000 500 20 1.273 1.298 150 60 1.242 1.248 60 0.02 VRUN+ VRUN– VRUN(HYST) IRUN VFB IFB ∆VFB ∆VIN ∆VFB ∆VITH ∆VFB(OV) gm VITH(BURST) ISENSE(ON) ISENSE(OFF) RUN Pin Input Threshold Hysteresis RUN Input Current Feedback Voltage FB Pin Input Current Line Regulation Load Regulation ∆FB Pin, Overvoltage Lockout Error Amplifier Transconductance Burst Mode Operation ITH Pin Voltage SENSE Pin Current (GATE High) SENSE Pin Current (GATE Low) VITH = 0.2V (Note 5) 2.5V ≤ VIN ≤ 30V VMODE/SYNC = 0V, VTH = 0.5V to 0.90V (Note 5) VFB(OV) – VFB(NOM) in Percent ITH Pin Load = ± 5µA (Note 5) Falling ITH Voltage (Note 5) Duty Cycle < 20% VSENSE = 0V VSENSE = 30V 120 –1 2.5 – 0.1 6 650 0.3 150 35 0.1 180 50 5 10 VSENSE(MAX) Maximum Current Sense Input Threshold 2 U µA µA µA V V V mV nA V V nA %/V % % µmho V mV µA µA W U U WW W LTC1871 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL Oscillator fOSC DMAX fSYNC/fOSC tSYNC(MIN) tSYNC(MAX) VIL(MODE) VIH(MODE) RMODE/SYNC VFREQ VINTVCC ∆VINTVCC ∆VIN1 ∆VINTVCC ∆VIN2 VLDO(LOAD) VDROPOUT IINTVCC GATE Driver tr tf GATE Driver Output Rise Time GATE Driver Output Fall Time CL = 3300pF (Note 7) CL = 3300pF (Note 7) 17 8 100 100 ns ns Oscillator Frequency Oscillator Frequency Range Maximum Duty Cycle Recommended Maximum Synchronized Frequency Ratio MODE/SYNC Minimum Input Pulse Width MODE/SYNC Maximum Input Pulse Width Low Level MODE/SYNC Input Voltage High Level MODE/SYNC Input Voltage MODE/SYNC Input Pull-Down Resistance Nominal FREQ Pin Voltage INTVCC Regulator Output Voltage INTVCC Regulator Line Regulation INTVCC Regulator Line Regulation INTVCC Load Regulation INTVCC Regulator Dropout Voltage Bootstrap Mode INTVCC Supply Current in Shutdown VIN = 7.5V 7.5V ≤ VIN ≤ 15V 15V ≤ VIN ≤ 30V 0 ≤ IINTVCC ≤ 20mA, VIN = 7.5V VIN = 5V, INTVCC Load = 20mA RUN = 0V, SENSE = 5V –2 5.0 1.2 50 0.62 5.2 8 70 – 0.2 280 10 20 5.4 25 200 fOSC = 300kHz (Note 6) VSYNC = 0V to 5V VSYNC = 0V to 5V RFREQ = 80k 250 50 87 92 1.25 25 0.8/fOSC 0.3 300 350 1000 97 1.30 ns ns V V kΩ V V mV mV % mV µA kHz kHz % PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS Low Dropout Regulator Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: The LTC1871E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 120°C/W) Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (QG • fOSC). See Applications Information. Note 5: The LTC1871 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 0V and 1.4V (the no load to full load operating voltage range for the ITH pin is 0.3V to 1.23V). Note 6: In a synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. Note 7: Rise and fall times are measured at 10% and 90% levels. 3 LTC1871 TYPICAL PERFOR A CE CHARACTERISTICS FB Voltage vs Temp 1.25 FB PIN CURRENT (nA) 0 5 10 15 20 VIN (V) 25 30 35 1.24 FB VOLTAGE (V) FB VOLTAGE (V) 1.23 1.22 1.21 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G01 Shutdown Mode IQ vs VIN 30 SHUTDOWN MODE IQ (µA) SHUTDOWN MODE IQ (µA) 20 Burst Mode IQ (µA) 10 0 0 10 20 VIN (V) 30 Burst Mode IQ vs Temperature 500 18 16 400 14 12 Burst Mode IQ (µA) TIME (ns) IQ (mA) 300 200 100 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G07 4 UW 1871 G04 FB Voltage Line Regulation 1.231 60 50 40 30 20 10 1.229 FB Pin Current vs Temperature 1.230 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G03 1871 G02 Shutdown Mode IQ vs Temperature 20 VIN = 5V 600 500 Burst Mode IQ vs VIN 15 400 300 200 100 10 5 40 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G05 0 0 10 20 VIN (V) 30 40 1871 G06 Dynamic IQ vs Frequency CL = 3300pF IQ(TOT) = 550µA + Qg • f Gate Drive Rise and Fall Time vs CL 60 50 40 RISE TIME 30 20 FALL TIME 10 10 8 6 4 2 0 0 200 400 600 800 FREQUENCY (kHz) 1000 1200 0 0 2000 4000 6000 8000 CL (pF) 10000 12000 1871 G09 1871 G08 LTC1871 TYPICAL PERFOR A CE CHARACTERISTICS RUN Thresholds vs VIN 1.5 1.40 RUN THRESHOLDS (V) 1.4 RUN THRESHOLDS (V) RT (kΩ) 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G11 1.3 1.2 0 10 20 VIN (V) 30 Frequency vs Temperature 325 320 160 GATE FREQUENCY (kHz) 155 310 305 300 295 290 285 280 275 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G13 150 SENSE PIN CURRENT (µA) 315 MAX SENSE THRESHOLD (mV) INTVCC Load Regulation 5.4 VIN = 7.5V DROPOUT VOLTAGE (mV) 5.2 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) 5.1 5.0 0 10 20 30 40 50 60 INTVCC LOAD (mA) 70 80 UW 1871 G10 1871 G16 RUN Thresholds vs Temperature 1000 RT vs Frequency 1.35 1.30 100 1.25 40 1.20 –50 –25 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1871 G12 Maximum Sense Threshold vs Temperature 35 SENSE Pin Current vs Temperature GATE HIGH VSENSE = 0V 30 145 140 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G14 25 –50 – 25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1871 G15 INTVCC Line Regulation 500 450 400 350 300 250 200 150 100 50 INTVCC Dropout Voltage vs Current, Temperature 150°C 125°C 75°C 25°C 0°C –50°C 5.3 5.2 5.1 0 5 10 15 20 25 VIN (V) 30 0 35 40 0 5 10 15 INTVCC LOAD (mA) 20 1871 G18 1871 G17 5 LTC1871 PI FU CTIO S RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and programming the start-up threshold for the converter. The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the VIN supply current is kept to a low value (typ 10µA). The Absolute Maximum Rating for the voltage on this pin is 7V. ITH (Pin 2): Error Amplifier Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V. FB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulaton is 1.230V. FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.6V. MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operation is enabled. If the MODE/SYNC pin is connected to INTVCC, or if an external logic-level synchronization signal is applied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode. GND (Pin 6): Ground Pin. GATE (Pin 7): Gate Driver Output. INTVCC (Pin 8): The Internal 5.20V Regulator Output. The gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. VIN (Pin 9): Main Supply Pin. Must be closely decoupled to ground. SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to the drain of the power MOSFET for VDS sensing and highest efficiency. Alternatively, the SENSE pin may be connected to a resistor in the source of the power MOSFET. Internal leading edge blanking is provided for both sensing methods. 6 U U U LTC1871 BLOCK DIAGRA FREQ 4 0.6V MODE/SYNC 5 85mV 1.230V 50k OV IOSC PWM LATCH LOGIC S Q R BURST COMPARATOR CURRENT COMPARATOR C1 GND INTVCC V-TO-I OSC 0.30V FB 3 EA gm 1.230V ITH 2 INTVCC 8 5.2V LDO 1.230V SLOPE 1.230V UV TO START-UP CONTROL GND BIAS VREF 6 1871 BD 2.00V + – + + + – + – – W RUN SLOPE COMPENSATION BIAS AND START-UP CONTROL + C2 1 – 1.248V VIN 9 GATE 7 SENSE + – 10 V-TO-I ILOOP RLOOP VIN 7 LTC1871 OPERATIO Main Control Loop The LTC1871 is a constant frequency, current mode controller for DC/DC boost, SEPIC and flyback converter applications. The LTC1871 is distinguished from conventional current mode controllers because the current control loop can be closed by sensing the voltage drop across the power MOSFET switch instead of across a discrete sense resistor, as shown in Figure 2. This sensing technique improves efficiency, increases power density, and reduces the cost of the overall solution. L VIN VIN SENSE VSW GATE GND GND D VOUT 2a. SENSE Pin Connection for Maximum Efficiency (VSW < 36V) L VIN VIN GATE VSW D VOUT GND 2b. SENSE Pin Connection for Precise Control of Peak Current or for VSW > 36V Figure 2. Using the SENSE Pin On the LTC1871 For circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. The divided-down output voltage is compared to an internal 1.230V reference by the error amplifier EA, which outputs an error signal at the ITH pin. The voltage on the ITH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage relative to the reference voltage causes the ITH pin 8 U to rise, which causes the current comparator C1 to trip at a higher peak inductor current value. The average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. The nominal operating frequency of the LTC1871 is programmed using a resistor from the FREQ pin to ground and can be controlled over a 50kHz to 1000kHz range. In addition, the internal oscillator can be synchronized to an external clock applied to the MODE/SYNC pin and can be locked to a frequency between 100% and 130% of its nominal value. When the MODE/SYNC pin is left open, it is pulled low by an internal 50k resistor and Burst Mode operation is enabled. If this pin is taken above 2V or an external clock is applied, Burst Mode operation is disabled and the IC operates in continuous mode. With no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. The RUN pin controls whether the IC is enabled or is in a low current shutdown state. A micropower 1.248V reference and comparator C2 allow the user to program the supply voltage at which the IC turns on and off (comparator C2 has 100mV of hysteresis for noise immunity). With the RUN pin below 1.248V, the chip is off and the input supply current is typically only 10µA. An overvoltage comparator OV senses when the FB pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main RS latch. Because this RS latch is reset-dominant, the power MOSFET is actively held off for the duration of an output overvoltage condition. The LTC1871 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET, as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36V). By connecting the SENSE pin to a resistor in the source of the power MOSFET, the user is able to program output voltages significantly greater than 36V. + COUT + SENSE GND COUT RS 1871 F02 LTC1871 OPERATIO Programming the Operating Mode For applications where maximizing the efficiency at very light loads (e.g., 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with CO, causing a nearly instantaneous drop in VO. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. Boost Converter Design Example The design example given here will be for the circuit shown in Figure 1. The input voltage is 3.3V, and the output is 5V at a maximum load current of 7A (10A peak). 1. The duty cycle is:  V + V – V  5 + 0.4 – 3.3 D =  O D IN  = = 38.9%  VO + VD  5 + 0.4 2. Pulse-skip operation is chosen so the MODE/SYNC pin is shorted to INTVCC. 3. The operating frequency is chosen to be 300kHz to reduce the size of the inductor. From Figure 5, the resistor from the FREQ pin to ground is 80k. 4. An inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: 7  χ  IO(MAX) IIN(PEAK) = 1 +  • = 1.2 • = 13.8 A  2  1 – DMAX 1 – 0. 39 LTC1871 APPLICATIO S I FOR ATIO The inductor ripple current is: ∆IL = χ • IO(MAX) 7 = 0.4 • = 4.6 A 1 – DMAX 1 – 0.39 And so the inductor value is: L= VIN(MIN) 3.3V • DMAX = • 0.39 = 0.93µH ∆IL • f 4.6 A • 300kHz The component chosen is a 1µH inductor made by Sumida (part number CEP125-H 1ROMH) which has a saturation current of greater than 20A. 5. With the input voltage to the IC bootstrapped to the output of the power supply (5V), a logic-level MOSFET can be used. Because the duty cycle is 39%, the maximum SENSE pin threshold voltage is reduced from its low duty cycle typical value of 150mV to approximately 140mV. Assuming a MOSFET junction temperature of 125°C, the room temperature MOSFET RDS(ON) should be less than: RDS(ON) ≤ VSENSE(MAX) • 1 – DMAX  χ  1 +  • IO(MAX) • ρT  2 1 – 0.39 = 0.140 V • = 6.8mΩ  0.4   1+  • 7 A • 1.5  2 The MOSFET used was the Fairchild FDS7760A, which has a maximum RDS(ON) of 8mΩ at 4.5V VGS, a BVDSS of greater than 30V, and a gate charge of 37nC at 5V VGS. 6. The diode for this design must handle a maximum DC output current of 10A and be rated for a minimum reverse voltage of VOUT, or 5V. A 25A, 15V diode from On Semiconductor (MBRB2515L) was chosen for its high power dissipation capability. 7. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 50mV, the bulk C needs to be greater than: U COUT ≥ IOUT(MAX) = 0.01 • VOUT • f 7A = 466µF 0.01 • 5V • 300kHz The RMS ripple current rating for this capacitor needs to exceed: IRMS(COUT) ≥ IO(MAX) • 7A • 5V – 3.3V = 5A 3.3V VO – VIN(MIN) = VIN(MIN) W UU To satisfy this high RMS current demand, four 150µF Panasonic capacitors (EEFUEOJ151R) are required. In parallel with these bulk capacitors, two 22µF, low ESR (X5R) Taiyo Yuden ceramic capacitors (JMK325BJ226MM) are added for HF noise reduction. Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents flow. 8. The choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup a 100µF Sanyo Poscap (6TPC 100M), in parallel with two 22µF Taiyo Yuden ceramic capacitors (JMK325BJ226MM) is required (the input and return lead lengths are kept to a few inches, but the peak input current is close to 20A!). As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. PC Board Layout Checklist 1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC1871 should be connected directly to 1) the negative terminal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the source of the power MOSFET or the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane 21 LTC1871 APPLICATIO S I FOR ATIO immediately adjacent to Pin 6. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and inductance. JUMPER R3 RC R2 R1 RT CC R4 J1 PIN 1 LTC1871 CIN CVCC PSEUDO-KELVIN SIGNAL GROUND CONNECTION COUT VIAS TO GROUND PLANE TRUE REMOTE OUTPUT SENSING BULK C Figure 14. LTC1871 Boost Converter Suggested Layout R3 R4 CC 1 RC 2 10 9 J1 SWITCH NODE L1 SENSE VIN RUN ITH LTC1871 R1 R2 RT 3 4 5 FB FREQ MODE/ SYNC BOLD LINES INDICATE HIGH CURRENT PATHS Figure 15. LTC1871 Boost Converter Layout Diagram 22 + PSEUDO-KELVIN GROUND CONNECTION U 2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground plane VIN L1 M1 SWITCH NODE IS ALSO THE HEAT SPREADER FOR L1, M1, D1 COUT D1 VOUT LOW ESR CERAMIC 1871 F14 W UU VIN INTVCC GATE GND 8 7 6 CVCC M1 D1 + CIN GND COUT VOUT 1871 F15 LTC1871 APPLICATIO S I FOR ATIO is to be used for high DC currents, choose a path away from the small-signal components. 3. Place the CVCC capacitor immediately adjacent to the INTVCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. A low ESR and ESL 4.7µF ceramic capacitor works well here. 4. The high di/dt loop from the bottom terminal of the output capacitor, through the power MOSFET, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive ringing. Excess inductance can cause increased stress on the power MOSFET and increase HF noise on the output. If low ESR ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum. 5. Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power MOSFET. Not all MOSFETs are created equal (some are more equal than others). 6. Place the small-signal components away from high frequency switching nodes. In the layout shown in Figure 14, all of the small-signal components have been placed on one side of the IC and all of the power components have been placed on the other. This also allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the INTVCC decoupling capacitor) and small-signal currents flow in the other direction. 7. If a sense resistor is used in the source of the power MOSFET, minimize the capacitance between the SENSE pin trace and any high frequency switching nodes. The LTC1871 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications. VIN SW 16a. SEPIC Topology VIN VIN 16b. Current Flow During Switch On-Time VIN D1 VIN 16c. Current Flow During Switch Off-Time Figures 16. SEPIC Topolgy and Current Flow + + • + + • + U 8. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC1871 in order to keep the high impedance FB node short. 9. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC1871 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the LTC1871. A few inches of PC trace or wire (L ≈ 100nH) between the CIN of the LTC1871 and the actual source VIN should be sufficient to prevent current sharing problems. SEPIC Converter Applications The LTC1871 is also well suited to SEPIC (single-ended primary inductance converter) converter applications. The SEPIC converter shown in Figure 16 uses two inductors. The advantage of the SEPIC converter is the input voltage may be higher or lower than the output voltage, and the output is short-circuit protected. L1 C1 D1 W UU + • VOUT + L2 COUT RL • VOUT + • RL VOUT + • RL 23 LTC1871 APPLICATIO S I FOR ATIO The first inductor, L1, together with the main switch, resembles a boost converter. The second inductor, L2, together with the output diode D1, resembles a flyback or buck-boost converter. The two inductors L1 and L2 can be independent but can also be wound on the same core since identical voltages are applied to L1 and L2 throughout the switching cycle. By making L1 = L2 and winding them on the same core the input ripple is reduced along with cost and size. All of the SEPIC applications information that follows assumes L1 = L2 = L. IL1 IIN SW ON SW OFF 17a. Input Inductor Current IL2 IO 17b. Output Inductor Current IIN IC1 IO 17c. DC Coupling Capacitor Current ID1 IO 17d. Diode Current VOUT (AC) ∆VCOUT ∆VESR RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 17e. Output Ripple Voltage Figures 17. SEPIC Converter Switching Waveforms 24 U SEPIC Converter: Duty Cycle Considerations For a SEPIC converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: W UU  VO + VD  D=   VIN + VO + VD  where VD is the forward voltage of the diode. For converters where the input voltage is close to the output voltage the duty cycle is near 50%. The maximum output voltage for a SEPIC converter is: VO(MAX) = ( VIN + VD ) DMAX 1 – VD 1 – DMAX 1 – DMAX The maximum duty cycle of the LTC1871 is typically 92%. SEPIC Converter: The Peak and Average Input Currents The control circuit in the LTC1871 is measuring the input current (either using the RDS(ON) of the power MOSFET or by means of a sense resistor in the MOSFET source), so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum input current for a SEPIC converter is: IIN(MAX) = IO(MAX) • The peak input current is:  χ D IIN(PEAK) =  1 +  • IO(MAX) • MAX 1 – DMAX  2 DMAX 1 – DMAX The maximum duty cycle, DMAX, should be calculated at minimum VIN. The constant ‘χ’ represents the fraction of ripple current in the inductor relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30 and the peak current is 15% greater than the average. LTC1871 APPLICATIO S I FOR ATIO It is worth noting here that SEPIC converters that operate at high duty cycles (i.e., that develop a high output voltage from a low input voltage) can have very high input currents, relative to the output current. Be sure to check that the maximum load current will not overload the input supply. SEPIC Converter: Inductor Selection For most SEPIC applications the equal inductor values will fall in the range of 10µH to 100µH. Higher values will reduce the input ripple voltage and reduce the core loss. Lower inductor values are chosen to reduce physical size and improve transient response. Like the boost converter, the input current of the SEPIC converter is calculated at full load current and minimum input voltage. The peak inductor current can be significantly higher than the output current, especially with smaller inductors and lighter loads. The following formulas assume CCM operation and calculate the maximum peak inductor currents at minimum VIN:  χ V +V IL1(PEAK) =  1 +  • IO(MAX) • O D VIN(MIN)  2  χ VIN(MIN) + VD IL2(PEAK) =  1 +  • IO(MAX) • VIN(MIN)  2 The ripple current in the inductor is typically 20% to 40% (i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum average input current occurring at VIN(MIN) and IO(MAX) and ∆IL1 = ∆IL2. Expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: L= VIN(MIN) • DMAX ∆IL • f where: ∆IL = χ • IO(MAX) • DMAX 1 – DMAX By making L1 = L2 and winding them on the same core, the value of inductance in the equation above is replace by 2L U due to mutual inductance. Doing this maintains the same ripple current and energy storage in the inductors. For example, a Coiltronix CTX10-4 is a 10µH inductor with two windings. With the windings in parallel, 10µH inductance is obtained with a current rating of 4A (the number of turns hasn’t changed, but the wire diameter has doubled). Splitting the two windings creates two 10µH inductors with a current rating of 2A each. Therefore, substituting 2L yields the following equation for coupled inductors: L1 = L2 = VIN(MIN) • DMAX 2 • ∆IL • f Specify the maximum inductor current to safely handle IL(PK) specified in the equation above. The saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. SEPIC Converter: Power MOSFET Selection The power MOSFET serves two purposes in the LTC1871: it represents the main switching element in the power path, and its RDS(ON) represents the current sensing element for the control loop. Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the onresistance (RDS(ON)) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 5.2V INTVCC low dropout regulator. Consequently, logic-level threshold MOSFETs should be used in most LTC1871 applications. If low input voltage operation is expected (e.g., supplying power from a lithium-ion battery), then sublogic-level threshold MOSFETs should be used. The maximum voltage that the MOSFET switch must sustain during the off-time in a SEPIC converter is equal to the sum of the input and output voltages (VO + VIN). As a result, careful attention must be paid to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. Many logic-level devices are limited to 30V or less. Check the switching waveforms directly across the drain and source terminals of the power W UU 25 LTC1871 APPLICATIO S I FOR ATIO MOSFET to ensure the VDS remains below the maximum rating for the device. During the MOSFET’s on-time, the control circuit limits the maximum voltage drop across the power MOSFET to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RDS(ON). The relationship between the maximum load current, duty cycle and the RDS(ON) of the power MOSFET is: RDS(ON) ≤ VSENSE(MAX) 1 • IO(MAX)  χ  1 +  • ρT  2 • 1  VO + VD  V  +1  IN(MIN)  The VSENSE(MAX) term is typically 150mV at low duty cycle and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 8. The constant ‘χ’ in the denominator represents the ripple current in the inductors relative to their maximum current. For example, if 30% ripple current is chosen, then χ = 0.30. The ρT term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/°C. Figure 9 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. Another method of choosing which power MOSFET to use is to check what the maximum output current is for a given RDS(ON) since MOSFET on-resistances are available in discrete values. IO(MAX) ≤ VSENSE(MAX) 1 • RDS(ON)  χ  1 +  • ρT  2 • 1  VO + VD  V  +1  IN(MIN)  Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself. As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the controller is using the MOSFET as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current 26 U over all operating conditions (load, line and temperature) and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. The power dissipated by the MOSFET in a SEPIC converter is:   D PFET = IO(MAX) • MAX  • RDS(ON) • DMAX • ρT  1 – DMAX  1.85 D + k • VIN(MIN) + VO • IO(MAX) • MAX • CRSS • f 1 – DMAX 2 W UU ( ) The first term in the equation above represents the I2R losses in the device and the second term, the switching losses. The constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET •RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. This value of TJ can then be used to check the original assumption for the junction temperature in the iterative calculation process. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast-switching diode with low forward drop and low reverse leakage is desired. The output diode in a SEPIC converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to VIN(MAX) + VO. The average forward current in normal operation is equal to the output current, and the peak current is equal to: V +V   χ ID(PEAK) =  1 +  • IO(MAX) •  O D + 1  2  VIN(MIN)  The power dissipated by the diode is: PD = IO(MAX) • VD LTC1871 APPLICATIO S I FOR ATIO and the diode junction temperature is: TJ = TA + PD • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. SEPIC Converter: Output Capacitor Selection Because of the improved performance of today’s electrolytic, tantalum and ceramic capacitors, engineers need to consider the contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL, and bulk C) on the output voltage ripple waveform are illustrated in Figure 17 for a typical coupled-inductor SEPIC converter. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging ∆V. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging ∆V. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: 0.01 • VO ESRCOUT ≤ ID(PEAK) where: V +V   χ ID(PEAK) =  1 +  • IO(MAX) •  O D + 1  2  VIN(MIN)  For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ IO(MAX) 0.01 • VO • f U For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic or tantalum capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a SEPIC regulator experiences high RMS ripple currents, as shown in Figure 17. The RMS output capacitor ripple current is: IRMS(COUT) = IO(MAX) • VO VIN(MIN) W UU Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic, at a somewhat higher price. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. An excellent 27 LTC1871 APPLICATIO S I FOR ATIO choice is AVX TPS series of surface mount tantalum. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. SEPIC Converter: Input Capacitor Selection The input capacitor of a SEPIC converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. The input voltage source impedance determines the size of the input capacitor which is typically in the range of 10µF to 100µF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a SEPIC converter is: IRMS(CIN) = 1 12 • ∆IL Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! SEPIC Converter: Selecting the DC Coupling Capacitor The coupling capacitor C1 in Figure 16 sees nearly a rectangular current waveform as shown in Figure 17. During the switch off-time the current through C1 is IO(VO/ VIN) while approximately – IO flows during the on-time. This current waveform creates a triangular ripple voltage on C1: ∆VC1(P−P) = IO(MAX) C1 • f • VO VIN + VO + VD The maximum voltage on C1 is then: VC1(MAX) = VIN + ∆VC1(P−P) 2 28 U which is typically close to VIN(MAX). The ripple current through C1 is: IRMS(C1) = IO(MAX) • VO + VD VIN(MIN) W UU The value chosen for the DC coupling capacitor normally starts with the minimum value that will satisfy 1) the RMS current requirement and 2) the peak voltage requirement (typically close to VIN). Low ESR ceramic and tantalum capacitors work well here. SEPIC Converter Design Example The design example given here will be for the circuit shown in Figure 18. The input voltage is 5V to 15V and the output is 12V at a maximum load current of 1.5A (2A peak). 1. The duty cycle range is:  VO + VD  D=  = 45.5% to 71.4%  VIN + VO + VD  2. The operating mode chosen is pulse skipping, so the MODE/SYNC pin is shorted to INTVCC. 3. The operating frequency is chosen to be 300kHz to reduce the size of the inductors; the resistor from the FREQ pin to ground is 80k. 4. An inductor ripple current of 40% is chosen, so the peak input current (which is also the minimum saturation current) is: V +V  χ IL1(PEAK) =  1 +  • IO(MAX) • O D  2 VIN(MIN) 12 + 0.5  0.4  =  1+ = 4.5A  • 1.5 •  2 5 The inductor ripple current is: ∆IL = χ • IO(MAX) • DMAX 1 – DMAX 0.714 = 0.4 • 1.5 • = 1.5A 1 – 0.714 LTC1871 APPLICATIO S I FOR ATIO And so the inductor value is: L= VIN(MIN) 5 • DMAX = • 0.714 = 4µH 2 • ∆IL • f 2 • 1.5 • 300k The component chosen is a BH Electronics BH5101007, which has a saturation current of 8A. 5. With an minimum input voltage of 5V, only logic-level power MOSFETs should be considered. Because the maximum duty cycle is 71.4%, the maximum SENSE pin threshold voltage is reduced from its low duty cycle typical value of 150mV to approximately 120mV. Assuming a MOSFET junction temperature of 125°C, the room temperature MOSFET RDS(ON) should be less than: R3 1M 1 2 RC 33k CC1 R1 6.8nF 12.1k 1% R2 105k 1% 10 9 RUN ITH LTC1871 3 4 RT 80.6k 1% 5 FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 CVCC 4.7µF X5R M1 L2* CC2 47pF CIN, COUT1: KEMET T495X476K020AS CDC, COUT2: TAIYO YUDEN TMK432BJ106MM D1: INTERNATIONAL RECTIFIER 30BQ040 Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter 100 95 90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 45 0.001 VO = 12V MODE = INTVCC 0.01 0.1 1 OUTPUT CURRENT (A) 10 1871 F18b Figure 18b. SEPIC Efficiency vs Output Current U RDS(ON) ≤ VSENSE(MAX) 1 • χ IO(MAX)   1 +  • ρT  2 • 1  VO + VD  V  +1  IN(MIN)  = 0.12 1 1 • • = 12.7mΩ 1.5 1.2 • 1.5  12.5  +1   5 W UU For a SEPIC converter, the switch BVDSS rating must be greater than VIN(MAX) + VO, or 27V. This comes close to an IRF7811W, which is rated to 30V, and has a maximum room temperature RDS(ON) of 12mΩ at VGS = 4.5V. • L1* SENSE VIN CDC 10µF 25V X5R VIN 4.5V to 15V D1 + COUT1 47µF 20V ×2 VOUT 12V 1.5A (2A PEAK) COUT2 10µF 25V X5R ×2 GND 1871 F018a + CIN 47µF • L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS) M1: INTERNATIONAL RECTIFIER IRF7811W VIN = 12V VIN = 4.5V VIN = 15V 29 LTC1871 APPLICATIO S I FOR ATIO VIN = 4.5V VOUT = 12V VOUT (AC) 200mV/DIV IOUT 0.5A/DIV 50µs/DIV 1871 F19a Figure 19. LTC1871 SEPIC Converter Load Step Response 6. The diode for this design must handle a maximum DC output current of 2A and be rated for a minimum reverse voltage of VIN + VOUT, or 27V. A 3A, 40V diode from International Rectifier (30BQ040) is chosen for its small size, relatively low forward drop and acceptable reverse leakage at high temp. 7. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 120mV, the bulk C needs to be greater than: COUT ≥ IOUT(MAX) = 0.01 • VOUT • f 1.5A = 41µF 0.01 • 12V • 300kHz The RMS ripple current rating for this capacitor needs to exceed: IRMS(COUT) ≥ IO(MAX) • 1.5A • 12V = 2.3A 5V VO VIN(MIN) = To satisfy this high RMS current demand, two 47µF Kemet capacitors (T495X476K020AS) are required. As a result, the output ripple voltage is a low 50mV to 60mV. In parallel with these tantalums, two 10µF, low ESR (X5R) Taiyo Yuden ceramic capacitors (TMK432BJ106MM) are added for HF noise reduction. 30 U VIN = 15V VOUT = 12V VOUT (AC) 200mV/DIV IOUT 0.5A/DIV 50µs/DIV 1871 F19b W UU Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents flow. 8. The choice of an input capacitor for a SEPIC converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup, a single 47µF Kemet tantalum capacitor (T495X476K020AS) is adequate. As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. If any HF switching noise is observed it is a good idea to decouple the input with a low ESR, X5R ceramic capacitor as close to the VIN and GND pins as possible. 9. The DC coupling capacitor in a SEPIC converter is chosen based on its RMS current requirement and must be rated for a minimum voltage of VIN plus the AC ripple voltage. Start with the minimum value which satisfies the RMS current requirement and then check the ripple voltage to ensure that it doesn’t exceed the DC rating. IRMS(CI) ≥ IO(MAX) • = 1.5A • VO + VD VIN(MIN) 12V + 0.5V = 2.4A 5V For this design a single 10µF, low ESR (X5R) Taiyo Yuden ceramic capacitor (TMK432BJ106MM) is adequate. LTC1871 TYPICAL APPLICATIO S 2.5V to 3.3V Input, 5V/2A Output Boost Converter VIN 2.5V to 3.3V L1 1.8µH 1 2 RC 22k CC1 R1 6.8nF 12.1k 1% R2 37.4k 1% RUN ITH LTC1871 3 4 RT 80.6k 1% 5 FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 CVCC 4.7µF X5R M1 SENSE VIN 10 9 VOUT 5V 2A COUT2 10µF 6.3V X5R ×2 GND 1871 TA01a CC2 47pF CIN: COUT1: COUT2: CVCC: SANYO POSCAP 6TPA47M SANYO POSCAP 6TPB150M TAIYO YUDEN JMK316BJ106ML TAIYO YUDEN LMK316BJ475ML EFFICIENCY (%) U D1 + COUT1 150µF 6.3V ×2 + CIN 47µF 6.3V D1: INTERNATIONAL RECTIFIER 30BQ015 L1: TOKO DS104C2 B952AS-1R8N M1: SILICONIX/VISHAY Si9426 Output Efficiency at 2.5V and 3.3V Input 100 95 90 85 80 75 70 65 60 55 50 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 1871 TA01b 31 LTC1871 TYPICAL APPLICATIO S 18V to 27V Input, 28V Output, 400W 2-Phase, Low Ripple, Synchronized RF Base Station Power Supply (Boost) VIN 18V to 27V R2 8.45k 1% R1 93.1k 1% 1 2 CC1 47pF RUN ITH LTC1871 3 4 CFB1 47pF RT1 150k 5% 5 FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 CVCC1 4.7µF X5R CIN2 2.2µF 35V X5R M1 RS1 0.007Ω 1W COUT5* 330µF 50V ×4 SENSE VIN 10 9 COUT1 2.2µF 35V X5R ×3 L1 5.6µH L2 5.6µH D1 1 2 RC 22k RUN ITH CC2 47pF R4 261k 1% 3 CFB2 47pF R3 12.1k 1% 4 RT2 150k 5% 5 FB FREQ MODE/SYNC CC3 6.8nF CIN1: CIN2, 3: COUT2, 4, 5: COUT1, 3, 6: CVCC1, 2: SANYO 50MV330AX TAIYO YUDEN GMK325BJ225MN SANYO 50MV330AX TAIYO YUDEN GMK325BJ225MN TAIYO YUDEN LMK316BJ475ML 5V to 12V Input, ± 12V/0.2A Output SEPIC Converter with Undervoltage Lockout • L1* 1 2 RC 22k CC1 R4 6.8nF 127Ω 1% R3 1.10k 1% RUN ITH LTC1871 3 4 RT 60.4k 1% 5 FB FREQ MODE/SYNC INTVCC GATE GND 8 7 6 CVCC 4.7µF 10V X5R CIN1 1µF 16V X5R M1 L2* SENSE VIN 10 9 COUT1 4.7µF 16V X5R ×3 CDC1 4.7µF 16V X5R VIN 5V to 12V R2 54.9k 1% R1 127k 1% CC2 100pF NOTE: 1. VIN UVLO + = 4.47V VIN UVLO– = 4.14V 32 U + CIN1 330µF 50V + COUT2 330µF 50V GND + COUT6* 2.2µF 35V X5R VOUT 28V 14A *L5, COUT5 AND COUT6 ARE AN OPTIONAL SECONDARY FILTER TO REDUCE OUTPUT RIPPLE FROM