LTC2175-14

LTM9011-14/ LTM9010-14/LTM9009-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs FeaTures n n n n n n n n n n n Electrical Specifications Subject to Change DescripTion The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73.1dB SNR and 88dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flow-through pinout reduces overall board space requirements. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n 8-Channel Simultaneous Sampling ADC 73.1dB SNR 88dB SFDR Low Power: 140mW/113mW/94mW per Channel Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Internal Bypass Capacitance, No External Components 140-Pin (9mm × 11.25mm) BGA Package applicaTions n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing Typical applicaTion 1.8V VDD CHANNEL 1 ANALOG INPUT CHANNEL 2 ANALOG INPUT S/H 14-BIT ADC CORE 14-BIT ADC CORE 1.8V OVDD OUT1A OUT1B OUT2A DATA SERIALIZER 14-BIT ADC CORE OUT2B SERIALIZED LVDS OUTPUTS LTM9011-14, 125Msps, 2-Tone FFT, fIN = 70MHz and 75MHz 0 –10 –20 AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 S/H ••• ••• ••• CHANNEL 8 ANALOG INPUT ENCODE INPUT S/H OUT8A OUT8B DATA CLOCK OUT FRAME ••• –90 –100 –110 –120 PLL 0 10 GND OGND 9009101114 TA01 20 30 40 FREQUENCY (MHz) 50 60 9009101114 TA01b 9009101114p 1 LTM9011-14/ LTM9010-14/LTM9009-14 absoluTe MaxiMuM raTings (Notes 1, 2) pin conFiguraTion TOP VIEW Supply Voltages VDD, OVDD................................................ –0.3V to 2V Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE) (Note 3) ...........–0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9011C, 9010C, 9009C ....................... 0°C to 70°C LTM9011I, 9010I, 9009I ...................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C A B C D E F G H J K L M N P 1 2 3 4 5 6 7 8 9 10 BGA PACKAGE 140-LEAD (11.25mm × 9.00mm × 2.72mm) TJMAX = 150°C, θJA = 28°C/W orDer inForMaTion LEAD FREE FINISH LTM9011CY-14#PBF LTM9011IY-14#PBF LTM9010CY-14#PBF LTM9010IY-14#PBF LTM9009CY-14#PBF LTM9009IY-14#PBF TRAY LTM9011CY-14#PBF LTM9011IY-14#PBF LTM9010CY-14#PBF LTM9010IY-14#PBF LTM9009CY-14#PBF LTM9009IY-14#PBF PART MARKING* LTM9011Y14 LTM9011Y14 LTM9010Y14 LTM9010Y14 LTM9009Y14 LTM9009Y14 PACKAGE DESCRIPTION TEMPERATURE RANGE 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 9009101114p 2 LTM9011-14/ LTM9010-14/LTM9009-14 converTer characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS l LTM9011-14 PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise External Reference Internal Reference External Reference External Reference Differential Analog Input (Note 7) Internal Reference External Reference MIN 14 –4.1 –0.9 –12 –2.6 ±1.2 ±0.3 ±3 –1.3 –1.3 ±20 ±35 ±25 ±0.2 ±3 1.2 4.1 0.9 12 0 TYP MAX 14 LTM9010-14 MIN –3.25 –0.8 –12 –2.6 TYP ±1 ±0.3 ±3 –1.3 –1.3 ±20 ±35 ±25 ±0.2 ±3 1.2 MAX 3.25 0.8 12 0 14 LTM9009-14 MIN –2.75 –0.8 –12 –2.6 TYP ±1 ±0.3 ±3 –1.3 –1.3 ±20 ±35 ±25 ±0.2 ±3 1.2 MAX 2.75 0.8 12 0 UNITS Bits LSB LSB mV %FS %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS Differential Analog Input (Note 6) l l l l analog inpuT SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps 0 < AIN+, AIN– < VDD, 0 < PAR/SER < VDD 0.625 < SENSE < 1.3V l l l l l l MIN VCM – 100mV 0.625 TYP 1 to 2 VCM 1.250 155 130 100 MAX VCM + 100mV 1.300 UNITS VP-P V V µA µA µA Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ + AIN–)/2 Analog Input Common Mode Current External Voltage Reference Applied to SENSE External Reference Mode Analog Input Leakage Current No Encode PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth –1 –3 –6 0 0.15 80 1 3 6 µA µA µA ns psRMS dB MHz Figure 6 Test Circuit 800 9009101114p 3 LTM9011-14/ LTM9010-14/LTM9009-14 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTM9011-14 SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 70MHz Input 140MHz Input l DynaMic accuracy LTM9010-14 MIN 70.7 TYP 73 72.9 72.6 88 85 82 90 90 90 73 72.6 72 –90 –105 MAX LTM9009-14 MIN 70.9 TYP 73 72.9 72.5 88 85 82 90 90 90 72.9 72.6 72 –90 –105 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc MIN 71.1 TYP 73.1 73 72.6 88 85 82 90 90 90 73 72.6 72 –90 –105 MAX SFDR Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input l 75 75 77 l 84 84 85 S/(N+D) Signal-to-Noise Plus Distortion Ratio Crosstalk, Near Channel Crosstalk, Far Channel 5MHz Input 70MHz Input 140MHz Input 10MHz Input (Note 12) 10MHz Input (Note 12) l 69.6 70.2 70.4 inTernal reFerence characTerisTics PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation –400µA < IOUT < 1mA 1.7V < VDD < 1.9V –600µA < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) MIN 0.5 • VDD – 25mV TYP 0.5 • VDD ±25 4 1.225 1.250 ±25 7 0.6 1.275 MAX 0.5 • VDD + 25mV UNITS V ppm/°C Ω V ppm/°C Ω mV/V 9009101114p 4 LTM9011-14/ LTM9010-14/LTM9009-14 DigiTal inpuTs anD ouTpuTs SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN VIH VIL IIN CIN ROL IOH COUT VOD VOS RTERM Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN TYP MAX UNITS (Note 8) Internally Set Externally Set (Note 8) ENC+, ENC– to GND (See Figure 10) l l l 0.2 1.1 0.2 10 3.5 1.2 1.6 3.6 V V V V kΩ pF V 0.6 V V kΩ pF V 0.6 V µA pF Ω 10 3 µA pF 454 250 1.375 1.375 mV mV V V Ω 10 3 3.6 30 3.5 Single-Ended Encode Mode (ENC– Tied to GND) VDD = 1.8V VDD = 1.8V ENC+ to GND (See Figure 11) l l l 1.2 0 DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VDD = 1.8V VDD = 1.8V VIN = 0V to 3.6V l l l 1.3 –10 SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V l 200 –10 DIGITAL DATA OUTPUTS 247 125 1.125 1.125 350 175 1.250 1.250 100 9009101114p 5 LTM9011-14/ LTM9010-14/LTM9009-14 power requireMenTs SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS PSLEEP PNAP PDIFFCLK Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation Sleep Mode Power Nap Mode Power Power Increase With Differential Encode Mode Enabled (No Increase for Sleep Mode) CONDITIONS (Note 10) (Note 10) Sine Wave Input 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTM9011-14 MIN 1.7 1.7 TYP 1.8 1.8 566 54 98 1116 1196 2 170 40 MAX 1.9 1.9 610 62 108 1210 1292 1.7 1.7 LTM9010-14 MIN TYP 1.8 1.8 448 52 96 900 980 2 170 40 MAX 1.9 1.9 486 62 106 986 1066 LTM9009-14 MIN 1.7 1.7 TYP 1.8 1.8 368 50 94 752 832 2 170 40 MAX UNITS 1.9 1.9 400 58 104 824 908 V V mA mA mA mW mW mW mW mW TiMing characTerisTics SYMBOL fS tENCL tENCH tAP PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8) Sample-and-Hold Acquisition Delay Time PARAMETER Serial Data Bit Period CONDITIONS (Notes 10,11) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTM9011-14 MIN l l l l l LTM9010-14 MIN 5 4.52 2 4.52 2 4.76 4.76 4.76 4.76 0 TYP MAX 105 100 100 100 100 125 5 LTM9009-14 MIN 5.93 2 5.93 2 TYP 6.25 6.25 6.25 6.25 0 MAX 80 100 100 100 100 UNITS MHz ns ns ns ns ns TYP 4 4 4 4 0 MAX 100 100 100 100 5 3.8 2 3.8 2 Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On SYMBOL tSER CONDITIONS 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization (Note 8) (Note 8) (Note 8) Data, DCO, FR, 20% to 80% Data, DCO, FR, 20% to 80% tSER = 1ns l l l MIN TYP 1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) MAX UNITS s s s s s s Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tFRAME tDATA tPD tR tF FR to DCO Delay DATA to DCO Delay Propagation Delay Output Rise Time Output Fall Time DCO Cycle-Cycle Jitter Pipeline Latency 0.35 • tSER 0.35 • tSER 0.5 • tSER 0.5 • tSER 0.17 0.17 60 6 0.65 • tSER 0.65 • tSER s s s ns ns psP-P Cycles 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER 9009101114p 6 LTM9011-14/ LTM9010-14/LTM9009-14 TiMing characTerisTics SYMBOL tSCK tS tH tDS tDH tDO PARAMETER SCK Period SPI Port Timing (Note 8) Write Mode Read Back Mode, CSDO = 20pF , RPULLUP = 2k l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN 40 250 5 5 5 5 125 TYP MAX UNITS ns ns ns ns ns ns ns CS to SCK Setup Time SCK to CS Setup Time SDI Setup Time SDI Hold Time SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF , RPULLUP = 2k l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC+/ ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire chip, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8. Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and Ch.2 to Ch.8. 9009101114p 7 LTM9011-14/ LTM9010-14/LTM9009-14 TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B+ OUT#B– D5 D3 tFRAME tDATA tSER N tENCH tENCL tSER N+1 tPD D1 0 D13 D11 D9 D7 D5 tSER D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 SAMPLE N-5 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-4 9009101114 TD01 SAMPLE N-6 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B+ OUT#B– D7 D5 tFRAME tDATA tSER N tENCH tENCL N+1 N+2 tSER tPD D3 D1 D13 D11 D9 D7 D5 tSER D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-5 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-4 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-3 9009101114 TD02 SAMPLE N-6 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 9009101114p 8 LTM9011-14/ LTM9010-14/LTM9009-14 TiMing DiagraMs 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR+ FR– OUT#A– OUT#A+ OUT#B+ OUT#B– D9 D7 tFRAME tDATA tSER N tENCH tENCL tSER N+1 tPD D5 D3 D13 D11 D9 tSER D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-5 D6 D4 D2 D12 D10 D8 SAMPLE N-4 9009101114 TD03 SAMPLE N-6 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D1 D0 tPD 0 0 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 tFRAME tDATA tSER N tENCH tENCL tSER N+1 tSER D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10 SAMPLE N-4 9009101114 TD04 SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED 9009101114p 9 LTM9011-14/ LTM9010-14/LTM9009-14 TiMing DiagraMs One-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D3 D2 tPD D1 D0 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 tFRAME tDATA tSER N tENCH tENCL tSER N+1 tSER D4 D3 D2 D1 D0 D13 D12 D11 D10 SAMPLE N-4 9009101114 TD06 SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED One-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D5 D4 tPD D3 D2 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 tFRAME tDATA tSER N tENCH tENCL N+1 tSER tSER D4 D3 D2 D13 D12 D11 SAMPLE N-4 9009101114 TD07 SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED 9009101114p 10 LTM9011-14/ LTM9010-14/LTM9009-14 TiMing DiagraMs SPI Port Timing (Readback Mode) tS CS SCK tDS tDH tSCK tH tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 HIGH IMPEDANCE SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE 9009101114 TD08 9009101114p 11 LTM9011-14/ LTM9010-14/LTM9009-14 Typical perForMance characTerisTics LTM9011-14: Integral Nonlinearity (INL) 2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G01 LTM9011-14: Differential Nonlinearity (DNL) 1.0 0.8 0.6 0 –10 –20 –30 LTM9011-14: 8k Point FFT, fIN = 5MHz –1dBFS, 125Msps PL ER HOLD A CE 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 PL ER HOLD A CE AMPLITUDE (dBFS) 0.4 –40 –50 –60 –70 –80 PL ER HOLD A CE –90 –100 –110 –120 4096 8192 12288 OUTPUT CODE 16384 217514 G02 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G03 LTM9011-14: 8k Point FFT, fIN = 30MHz –1dBFS, 125Msps 0 –10 –20 AMPLITUDE (dBFS) –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 LTM9011-14: 8k Point FFT, fIN = 70MHz –1dBFS, 125Msps 0 –10 –20 –30 LTM9011-14: 8k Point FFT, fIN = 140MHz –1dBFS, 125Msps P L A CE ER HOLD –40 –50 –60 –70 –80 P L A CE ER HOLD AMPLITUDE (dBFS) –40 –50 –60 –70 –80 P DER EHOL L AC –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G04 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G05 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G06 LTM9011-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 5000 6000 LTM9011-14: Shorted Input Histogram 74 73 LTM9011-14: SNR vs Input Frequency, –1dB, 2V Range, 125Msps PL 3000 2000 1000 0 8178 PL SNR (dBFS) ER HOLD A CE 4000 COUNT ER HOLD A CE 72 71 70 69 68 67 PL ER HOLD A CE –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G07 8180 8182 8184 OUTPUT CODE 8186 217514 G08 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 217514 G09 9009101114p 12 LTM9011-14/ LTM9010-14/LTM9009-14 Typical perForMance characTerisTics LTM9011-14: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 95 90 SFDR (dBc AND dBFS) 85 80 75 70 65 110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 LTM9011-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps dBFS 80 70 LTM9011-14: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps dBFS SFDR (dBFS) PL ER HOLD A CE PL ER HOLD A CE dBc SNR (dBc AND dBFS) 60 50 40 30 20 10 0 –60 –50 PL ER HOLD A CE dBc –40 –30 –20 INPUT LEVEL (dBFS) –10 0 217514 G10 217514 G11 217514 G50 LTM9011-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 290 280 270 IVDD (mA) 260 250 240 230 220 210 0 25 50 75 100 SAMPLE RATE (Msps) 125 217514 G53 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 50 2-LANE, 3.5mA 40 74 73 72 SNR (dBFS) 71 70 69 68 67 0 0 25 50 75 100 SAMPLE RATE (Msps) 125 217514 G51 LTM9011-14: SNR vs SENSE, fIN = 5MHz, –1dB PL IOVDD (mA) DER EHOL AC 30 1-LANE, 3.5mA 20 10 PL DER EHOL AC 2-LANE, 1.75mA P DER EHOL L AC 1-LANE, 1.75mA 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 217514 G12 LTM9010-14: Integral Nonlinearity (INL) 2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G14 LTM9010-14: Differential Nonlinearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G15 LTM9010-14: 8k Point FFT, fIN = 5MHz –1dBFS, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 PL ER HOLD A CE PL ER HOLD A CE PL 0 10 ER HOLD A CE –90 –100 –110 –120 20 30 40 FREQUENCY (MHz) 50 217514 G16 9009101114p 13 LTM9011-14/ LTM9010-14/LTM9009-14 Typical perForMance characTerisTics LTM9010-14: 8k Point FFT, fIN = 30MHz –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 LTM9010-14: 8k Point FFT, fIN = 70MHz –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 LTM9010-14: 8k Point FFT, fIN = 140MHz –1dBFS, 105Msps PL ER HOLD A CE PL ER HOLD A CE PL ER HOLD A CE –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G17 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G18 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G19 LTM9010-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 5000 6000 LTM9010-14: Shorted Input Histogram 74 73 LTM9010-14: SNR vs Input Frequency, –1dB, 2V Range, 105Msps COUNT P 3000 2000 1000 0 8195 P SNR (dBFS) L A CE ER HOLD 4000 L A CE ER HOLD 72 71 70 69 68 67 P DER EHOL L AC –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G20 8197 8199 8201 OUTPUT CODE 8203 217514 G21 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 217514 G22 LTM9010-14: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 95 90 85 80 75 70 65 SFDR (dBc AND dBFS) 110 100 90 LTM9010-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps dBFS 230 220 LTM9010-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB SFDR (dBFS) IVDD (mA) PL ER HOLD A CE 80 70 60 50 40 30 20 10 PL ER HOLD A CE dBc 210 200 190 180 170 0 160 0 25 PL ER HOLD A CE 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 50 75 SAMPLE RATE (Msps) 100 217514 G54 217514 G23 217514 G24 9009101114p 14 LTM9011-14/ LTM9010-14/LTM9009-14 Typical perForMance characTerisTics LTM9010-14: SNR vs SENSE, fIN = 5MHz, –1dB 74 73 72 SNR (dBFS) 71 70 69 68 67 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 2.0 1.5 LTM9009-14: Integral Nonlinearity (INL) 1.0 0.8 0.6 DNL ERROR (LSB) LTM9009-14: Differential Nonlinearity (DNL) INL ERROR (LSB) PL DER EHOL AC 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 PL DER EHOL AC 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 P DER EHOL L AC 4096 8192 12288 OUTPUT CODE 16384 217514 G26 0 4096 8192 12288 OUTPUT CODE 16384 217514 G27 217514 G25 LTM9009-14: 8k Point FFT, fIN = 5MHz –1dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 –10 –20 –40 –50 –60 –70 –80 –30 LTM9009-14: 8k Point FFT, fIN = 30MHz –1dBFS, 80Msps 0 –10 –20 AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 LTM9009-14: 8k Point FFT, fIN = 70MHz –1dBFS, 80Msps PL A ER HOLD CE PL A ER HOLD CE PL ER HOLD A CE –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 217514 G28 0 10 20 30 FREQUENCY (MHz) 40 217514 G29 0 10 20 30 FREQUENCY (MHz) 40 217514 G30 LTM9009-14: 8k Point FFT, fIN = 140MHz –1dBFS, 80Msps 0 –10 –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 0 –10 –20 –30 LTM9009-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 80Msps 6000 5000 LTM9009-14: Shorted Input Histogram PL DER EHOL AC –40 –50 –60 –70 –80 PL DER EHOL AC 4000 COUNT 3000 2000 1000 0 8184 P DER EHOL L AC –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 217514 G31 0 10 20 30 FREQUENCY (MHz) 40 217514 G32 8186 8188 8190 OUTPUT CODE 8192 217514 G33 9009101114p 15 LTM9011-14/ LTM9010-14/LTM9009-14 Typical perForMance characTerisTics LTM9009-14: SNR vs Input Frequency, –1dB, 2V Range, 80Msps 74 73 72 SNR (dBFS) 71 70 69 68 67 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 70 65 95 90 85 80 75 SFDR (dBc AND dBFS) LTM9009-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps 110 100 90 LTM9009-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps dBFS SFDR (dBFS) PL DER EHOL AC PL DER EHOL AC 80 70 60 50 40 30 20 10 P DER EHOL L AC dBc 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 217514 G34 217514 G35 217514 G36 LTM9009-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 190 74 73 72 SNR (dBFS) 71 70 69 68 67 140 0 20 40 60 SAMPLE RATE (Msps) 80 217514 G55 LTM9009-14: SNR vs SENSE, fIN = 5MHz, –1dB 350 300 PEAK-TO-PEAK JITTER (ps) DCO Cycle-Cycle Jitter vs Serial Data Rate 180 IVDD (mA) 170 PL A ER HOLD CE PL A ER HOLD CE 250 200 150 100 50 PL ER HOLD A CE 160 150 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0 0 200 400 600 800 SERIAL DATA RATE (Mbps) 1000 217514 G52 217514 G37 9009101114p 16 LTM9011-14/ LTM9010-14/LTM9009-14 pin FuncTions AIN1+ (B2): Channel 1 Positive Differential Analog Input. AIN1– (B1): Channel 1 Negative Differential Analog Input. VCM12 (B3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 2. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN2+ (C2): Channel 2 Positive Differential Analog Input. AIN2– (C1): Channel 2 Negative Differential Analog Input. AIN3+ (E2): Channel 3 Positive Differential Analog Input. AIN3 – (E1): Channel 3 Negative Differential Analog Input. VCM34 (F3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 3 and 4. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN4 + (G2): Channel 4 Positive Differential Analog Input. AIN4 – (G1): Channel 4 Negative Differential Analog Input. AIN5+ (H1): Channel 5 Positive Differential Analog Input. AIN5 – (H2): Channel 5 Negative Differential Analog Input. VCM56 (J3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 5 and 6. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN6+ (K1): Channel 6 Positive Differential Analog Input. AIN6 – (K2): Channel 6 Negative Differential Analog Input. AIN7+ (M1): Channel 7 Positive Differential Analog Input. AIN7– (M2): Channel 7 Negative Differential Analog Input. VCM78 (N3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 7 and 8. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN8+ (N1): Channel 8 Positive Differential Analog Input. AIN8 – (N2): Channel 8 Negative Differential Analog Input VDD (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power Supply. VDD is internally bypassed to ground with 0.1μF ceramic capacitors. ENC+ (P5): Encode Input. Conversion starts on the rising edge. ENC – (P6): Encode Complement Input. Conversion starts on the falling edge. CSA (L5): In serial programming mode, (PAR/SER = 0V), CSA is the serial interface chip select input for registers controlling channels 1, 4, 5 and 8. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. CSB (M5): In serial programming mode, (PAR/SER = 0V), CSB is the serial interface chip select input for registers controlling channels 2, 3, 6 and 7. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (L6): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (M6): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (See Pin Configuration Table): ADC Power Ground. Use multiple vias close to pins. 9009101114p 17 LTM9011-14/ LTM9010-14/LTM9009-14 pin FuncTions OVDD (G9, G10): Output Driver Supply. OVDD is internally bypassed to ground with a 0.1µF ceramic capacitor. SDOA (E6): In serial programming mode, (PAR/SER = 0V), SDOA is the optional serial interface data output for registers controlling channels 1 through 4. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In parallel programming mode (PAR/SER = VDD), SDOA is an input that enables internal 100Ω termination resistors on the digital outputs of channels 1, 4, 5 and 8. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6 and 7. See description for SDOA. PAR/SER (A7): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CSA, CSB, SCK, SDI, SDOA and SDOB become a serial interface that control the A/D operating modes. Connect to VDD to enable parallel programming mode where CSA, CSB, SCK, SDI, SDOA and SDOB become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/ SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. VREF (B6): Reference Voltage Output. VREF is internally bypassed to ground with a 1μF ceramic capacitor, nominally 1.25V. SENSE (C5): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. SENSE is internally bypassed to ground with a 0.1µF ceramic capacitor. LVDS Outputs All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT1A–/OUT1A+, OUT1B–/OUT1B+ (E7/E8, C8/D8): Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. OUT2A – /OUT2A +, OUT2B – /OUT2B + (B8/A8, D7/C7): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. OUT3A–/OUT3A+, OUT3B –/OUT3B+ (D10/D9, E10/E9): Serial Data Outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used. OUT4A –/OUT4A +, OUT4B –/OUT4B + (C9/C10, F7/F8): Serial Data Outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used. OUT5A–/OUT5A+, OUT5B–/OUT5B+ (J8/J7, K8/K7): Serial Data Outputs for Channel 5. In 1-lane output mode only OUT5A–/OUT5A+ are used. OUT6A–/OUT6A+, OUT6B –/OUT6B+ (K9/K10, L9/L10): Serial Data Outputs for Channel 6. In 1-lane output mode only OUT6A–/OUT6A+ are used. OUT7A – /OUT7A +, OUT7B – /OUT7B + (M7/L7, P8/N8): Serial Data Outputs for Channel 7. In 1-lane output mode only OUT7A–/OUT7A+ are used. OUT8A–/OUT8A+, OUT8B –/OUT8B+ (L8/M8, M10/M9): Serial Data Outputs for Channel 8. In 1-lane output mode only OUT8A–/OUT8A+ are used. FRA–/FRA+ (H7/H8): Frame Start Outputs for Channels 1, 4, 5 and 8. FRB –/FRB+ (J9/J10): Frame Start Outputs for Channels 2, 3, 6 and 7. DCOA–/DCOA+ (G8/G7): Data Clock Outputs for Channels 1, 4, 5 and 8. DCOB –/DCOB+ (F10, F9): Data Clock Outputs for Channels 2, 3, 6 and 7. 9009101114p 18 LTM9011-14/ LTM9010-14/LTM9009-14 pin conFiguraTion Table 1 A B C D E F G H J K L M N P GND AIN1– AIN2 – 2 GND AIN1+ AIN2 + 3 GND VCM12 GND VDD VDD VCM34 GND GND VCM56 VDD VDD GND VCM78 GND 4 GND GND GND VDD VDD GND GND GND GND VDD VDD GND GND GND 5 GND GND SENSE GND GND GND GND GND GND GND CSA CSB GND CLK+ 6 GND VREF GND SDOB SDOA GND GND GND GND GND SCK SDI GND CLK– 7 PAR/SER GND O2B+ O2B– O1A– O4B– DCOA+ FRA– O5A+ O5B+ O7A+ O7A– GND GND 8 O2A+ O2A– O1B– O1B+ O1A+ O4B+ DCOA– FRA+ O5A– O5B– O8A– O8A+ O7B+ O7B– 9 OGND OGND O4A– O3A+ O3B+ DCOB+ OVDD OGND FRB– O6A– O6B– O8B+ OGND OGND 10 OGND OGND O4A+ O3A– O3B– DCOB– OVDD OGND FRB+ O6A+ O6B+ O8B– OGND OGND GND AIN3– GND AIN4– AIN5 + GND AIN3+ GND AIN4+ AIN5 – GND AIN6+ GND AIN7+ AIN8 + GND AIN6– GND AIN7– AIN8 – GND GND Top View of BGA Package (Looking Through Component). 9009101114p 19 LTM9011-14/ LTM9010-14/LTM9009-14 FuncTional block DiagraM VDD = 1.8V OVDD = 1.8V CH 1 ANALOG INPUT OUT1A+ OUT1A– OUT1B+ OUT1B– S/H 14-BIT ADC CORE CH 2 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A– OUT1B+ OUT1B– CH 3 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A– OUT1B+ OUT1B– CH 4 ANALOG INPUT S/H 14-BIT ADC CORE DATA SERIALIZER OUT1A+ OUT1A– OUT1B+ OUT1B– CH 5 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A– OUT1B+ OUT1B– CH 6 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A– OUT1B+ OUT1B– CH 7 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A– OUT1B+ OUT1B– CH 8 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A– OUT1B+ OUT1B– ENC+ PLL ENC– 1.25V REFERENCE REFH REFL MODE CONTROL REGISTERS DCOA± DCOB± FRA± FRB± SDOA SDOB SDI SCK CSA CSB PAR/SER VREF RANGE SELECT REF BUFFER DIFF REF AMP VDD/2 GND SENSE VCM12 VCM34 VCM56 VCM78 9009101114 F01 Figure 1. Functional Block Diagram 9009101114p 20 LTM9011-14/ LTM9010-14/LTM9009-14 applicaTions inForMaTion CONVERTER OPERATION The LTM9011-14/LTM9010-14/LTM9009-14 are low power, 8-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the appropriate VCM output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. The eight channels are simultaneously sampled by a shared encode circuit (Figure 2). LTM9011-14 10 CPARASITIC 1.8pF RON 25 VDD CPARASITIC 1.8pF CSAMPLE 3.5pF VDD RON 25 CSAMPLE 3.5pF INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC low pass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. 50 VCM 0.1µF 0.1µF ANALOG INPUT T1 1:1 25 25 25 0.1µF 12pF 25 AIN– 9009101114 F03 AIN+ LTM9011-14 AIN+ T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE VDD AIN– 10Ω Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 1.2V 10k ENC+ ENC– 10k 1.2V 9009101114 F02 Figure 2. Equivalent Input Circuit. Only One of the Eight Analog Channels Is Shown 9009101114p 21 LTM9011-14/ LTM9010-14/LTM9009-14 applicaTions inForMaTion Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. Reference The LTM9011-14/LTM9010-14/LTM9009-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, 50 VCM 0.1µF 50 VCM 0.1µF 0.1µF ANALOG INPUT T2 T1 25 25 0.1µF AIN+ LTM9011-14 4.7pF 0.1µF ANALOG INPUT T2 T1 25 25 0.1µF AIN+ LTM9011-14 1.8pF 0.1µF AIN– 9009101114 F04 0.1µF AIN– 9009101114 F05 T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz Figure 5. Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz 50 VCM 0.1µF HIGH SPEED DIFFERENTIAL 0.1µF AMPLIFIER LTM9011-14 ANALOG INPUT 200 200 25 VCM 0.1µF AIN+ LTM9011-14 12pF 0.1µF 25 AIN– 9009101114 F07 0.1µF ANALOG INPUT T1 0.1µF 25 2.7nH 25 0.1µF AIN+ + – + – 2.7nH AIN– 9009101114 F06 T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 6. Recommended Front End Circuit for Input Frequencies Above 300MHz Figure 7. Front End Circuit Using a High Speed Differential Amplifier 9009101114p 22 LTM9011-14/ LTM9010-14/LTM9009-14 applicaTions inForMaTion apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The reference is shared by all eight ADC channels, so it is not possible to independently adjust the input range of individual channels. The VREF , REFH and REFL pins are internally bypassed, as shown in Figure 8. Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). VREF 1.25V LTM9011-14 1µF 5 1.25V BANDGAP REFERENCE 0.625V TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.65V < VSENSE < 1.300V RANGE DETECT AND CONTROL SENSE 0.1µF INTERNAL ADC BUFFER HIGH REFERENCE REFH 2.2µF 0.1µF 0.1µF 0.8x DIFF AMP REFL INTERNAL ADC LOW REFERENCE 9009101114 F08 Figure 8. Reference Circuit 1.25V EXTERNAL REFERENCE LTM9011-14 SENSE 1µF LTM9011-14 VDD DIFFERENTIAL COMPARATOR LTM9011-14 1.8V TO 3.3V 0V ENC+ ENC– 30k CMOS LOGIC BUFFER 9009101114 F11 VDD 15k ENC+ 9009101114 F09 Figure 9. Using an External 1.25V Reference ENC– 30k Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode 9009101114 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode 9009101114p 23 LTM9011-14/ LTM9010-14/LTM9009-14 applicaTions inForMaTion The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC – should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25µs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. 0.1µF 0.1µF T1 50Ω ENC+ LTM9011-14 PECL OR LVDS CLOCK ENC+ LTM9011-14 0.1µF ENC– 9009101114 F13 100Ω 0.1µF 50Ω 0.1µF ENC– 9009101114 F12 Figure 13. PECL or LVDS Encode Drive T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive 9009101114p 24 LTM9011-14/ LTM9010-14/LTM9009-14 applicaTions inForMaTion DIGITAL OUTPUTS The digital outputs of the LTM9011-14/LTM9010-14/ LTM9009-14 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16, 14, or 12-bit serialization (see timing diagrams for details). Note that with 12-bit serialization the two LSBs are not available—this mode is included for compatibility with the 12-bit versions of these parts. The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode the SCK pin can select either 3.5mA or 1.75mA. Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the parallel programming mode the SDO pin enables internal termination. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9011-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTM9010-14) or 80MHz (LTM9009-14). SERIALIZATION MODE 2-Lane 2-Lane 2-Lane 1-Lane 1-Lane 1-Lane 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization MAXIMUM SAMPLING FREQUENCY fS (MHz) , 125 125 125 62.5 71.4 83.3 DCO FREQUENCY 4 • fS 3.5 • fS 3 • fS 8 • fS 7 • fS 6 • fS FR FREQUENCY fS 0.5 • fS fS fS fS fS SERIAL DATA RATE 8 • fS 7 • fS 6 • fS 16 • fS 14 • fS 12 • fS 9009101114p 25 LTM9011-14/ LTM9010-14/LTM9009-14 applicaTions inForMaTion DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1. Table 2. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) >1.000000V +0.999878V +0.999756V +0.000122V +0.000000V –0.000122V –0.000244V –0.999878V –1.000000V