LTC2175IUKG-14TRPBF

Electrical Specifications Subject to Change LTC2175-14/ LTC2174-14/LTC2173-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Quad ADCs FEATURES n n n n n n n n n n n n DESCRIPTION The LTC®2175-14/2174-14/2173-14 are 4-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2 LSBRMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. 4-Channel Simultaneous Sampling ADC 73.4dB SNR 88dB SFDR Low Power: 558mW/450mW/376mW Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 52-Pin (7mm × 8mm) QFN Package APPLICATIONS n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 1.8V VDD CHANNEL 1 ANALOG INPUT CHANNEL 2 ANALOG INPUT CHANNEL 3 ANALOG INPUT CHANNEL 4 ANALOG INPUT ENCODE INPUT S/H 14-BIT ADC CORE 1.8V OVDD OUT1A OUT1B OUT2A AMPLITUDE (dBFS) DATA SERIALIZER S/H 14-BIT ADC CORE OUT2B OUT3A OUT3B OUT4A OUT4B DATA CLOCK OUT FRAME SERIALIZED LVDS OUTPUTS LTC2175-14, 125Msps, 2-Tone FFT, fIN = 70MHz and 75MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 S/H 14-BIT ADC CORE S/H 14-BIT ADC CORE –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 TA01b PLL GND OGND 217514 TA01 21754314p 1 LTC2175-14/ LTC2174-14/LTC2173-14 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATIONS TOP VIEW PAR/SER OUT1A+ OUT1A– OUT1B+ OUT4A– OUT1B– 40 OUT2A+ 39 OUT2A– 38 OUT2B+ 37 OUT2B– 36 DCO+ 35 DCO– 53 34 OVDD 33 OGND 32 FR+ 31 FR– 30 OUT3A+ 29 OUT3A– 28 OUT3B+ 27 OUT3B– 15 16 17 18 19 20 21 22 23 24 25 26 VDD VDD ENC+ ENC– CS SCK SDI OUT4B– OUT4B+ OUT4A+ GND SENSE VREF GND GND SDO VDD AIN1+ 1 AIN1 AIN2 AIN2 – Supply Voltages VDD, OVDD................................................ –0.3V to 2V Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE) (Note 3) ...........–0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2175C, 2174C, 2173C ........................ 0°C to 70°C LTC2175I, 2174I, 2173I ....................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C 52 51 50 49 48 47 46 45 44 43 42 41 2 VCM12 3 + – 4 5 REFH 6 REFH 7 REFL 8 REFL 9 AIN3 10 AIN3 11 VCM34 12 AIN4 13 AIN4– 14 + – + UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 28°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2175CUKG-14#PBF LTC2175IUKG-14#PBF LTC2174CUKG-14#PBF LTC2174IUKG-14#PBF LTC2173CUKG-14#PBF LTC2173IUKG-14#PBF TAPE AND REEL LTC2175CUKG-14#TRPBF LTC2175IUKG-14#TRPBF LTC2174CUKG-14#TRPBF LTC2174IUKG-14#TRPBF LTC2173CUKG-14#TRPBF LTC2173IUKG-14#TRPBF PART MARKING* LTC2175UKG-14 LTC2175UKG-14 LTC2174UKG-14 LTC2174UKG-14 LTC2173UKG-14 LTC2173UKG-14 PACKAGE DESCRIPTION 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ VDD 21754314p 2 LTC2175-14/ LTC2174-14/LTC2173-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2175-14 PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise External Reference Internal Reference External Reference External Reference Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS l l l l LTC2174-14 MIN 14 –3.75 –0.9 –15 –1.5 TYP ±1 ±0.3 ±3 ±1.5 ±0.4 ±20 ±35 ±25 ±0.2 ±3 1.2 MAX 3.75 0.9 15 1.5 14 LTC2173-14 MIN –3.5 –0.9 –15 –1.5 TYP ±1 ±0.3 ±3 ±1.5 ±0.4 ±20 ±35 ±25 ±0.2 ±3 1.2 MAX 3.5 0.9 15 1.5 UNITS Bits LSB LSB mV %FS %FS μV/°C ppm/°C ppm/°C %FS mV LSBRMS MIN 14 TYP ±1 ±0.3 ±3 ±1.5 ±0.4 ±20 ±35 ±25 ±0.2 ±3 1.2 MAX 3.75 0.9 15 1.5 Differential Analog Input (Note 6) l –3.75 –0.9 –15 –1.5 ANALOG INPUT SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps 0 < AIN+, AIN– < VDD, 0 < PAR/SER < VDD 0.625 < SENSE < 1.3V l l l l l l MIN VCM – 100mV 0.625 TYP 1 to 2 VCM 1.250 155 130 100 MAX VCM + 100mV 1.300 UNITS VP-P V V μA μA μA Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ + AIN–)/2 Analog Input Common Mode Current External Voltage Reference Applied to SENSE External Reference Mode IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B Analog Input Leakage Current No Encode PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth –1 –3 –6 0 0.15 80 1 3 6 μA μA μA ns psRMS dB MHz Figure 6 Test Circuit 800 21754314p 3 LTC2175-14/ LTC2174-14/LTC2173-14 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTC2175-14 SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 70MHz Input 140MHz Input l DYNAMIC ACCURACY LTC2174-14 MIN 71.3 TYP 73.4 73.2 72.7 88 85 82 90 90 90 73 72.6 72 –90 –105 MAX LTC2173-14 MIN 70.9 TYP 73.1 72.9 72.4 88 85 82 90 90 90 72.9 72.6 72 –90 –105 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc MIN 71.3 TYP 73.4 73.2 72.7 88 85 82 90 90 90 73 72.6 72 –90 –105 MAX SFDR Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input l 76 76 79 l 85 83 85 S/(N+D) Signal-to-Noise Plus Distortion Ratio Crosstalk, Near Channel Crosstalk, Far Channel 5MHz Input 70MHz Input 140MHz Input 10MHz Input (Note 12) 10MHz Input (Note 12) l 70.2 70.2 70.4 INTERNAL REFERENCE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation –400μA < IOUT < 1mA 1.7V < VDD < 1.9V –600μA < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) MIN 0.5 • VDD – 25mV TYP 0.5 • VDD ±25 4 1.225 1.250 ±25 7 0.6 1.275 MAX 0.5 • VDD + 25mV UNITS V ppm/°C Ω V ppm/°C Ω mV/V 21754314p 4 LTC2175-14/ LTC2174-14/LTC2173-14 DIGITAL INPUTS AND OUTPUTS SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN VIH VIL IIN CIN ROL IOH COUT VOD VOS RTERM Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN TYP MAX UNITS (Note 8) Internally Set Externally Set (Note 8) ENC+, ENC– to GND (See Figure 10) l l l 0.2 1.2 1.1 0.2 10 3.5 1.6 3.6 V V V V kΩ pF V 0.6 V V kΩ pF V 0.6 V μA pF Ω 10 3 μA pF 454 250 1.375 1.375 mV mV V V Ω 10 3 3.6 30 3.5 Single-Ended Encode Mode (ENC– Tied to GND) VDD = 1.8V VDD = 1.8V ENC+ to GND (See Figure 11) l l l 1.2 0 DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VDD = 1.8V VDD = 1.8V VIN = 0V to 3.6V l l l 1.3 –10 SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V l 200 –10 DIGITAL DATA OUTPUTS 247 125 1.125 1.125 350 175 1.250 1.250 100 21754314p 5 LTC2175-14/ LTC2174-14/LTC2173-14 POWER REQUIREMENTS SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS PSLEEP PNAP PDIFFCLK Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation Sleep Mode Power Nap Mode Power Power Increase With Differential Encode Mode Enabled (No Increase for Sleep Mode) CONDITIONS (Note 10) (Note 10) Sine Wave Input 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2175-14 MIN 1.7 1.7 TYP 1.8 1.8 283 27 49 558 598 1 85 20 MAX 1.9 1.9 TBD TBD TBD TBD TBD MIN 1.7 1.7 LTC2174-14 TYP 1.8 1.8 224 26 48 450 490 1 85 20 MAX 1.9 1.9 TBD TBD TBD TBD TBD 1.7 1.7 LTC2173-14 MIN TYP 1.8 1.8 184 25 47 376 416 1 85 20 MAX UNITS 1.9 1.9 TBD TBD TBD TBD TBD V V mA mA mA mW mW mW mW mW TIMING CHARACTERISTICS SYMBOL fS tENCL tENCH tAP PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8) Sample-and-Hold Acquisition Delay Time PARAMETER Serial Data Bit Period CONDITIONS (Notes 10,11) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2175-14 MIN l l l l l LTC2174-14 MIN 5 4.52 2 4.52 2 4.76 4.76 4.76 4.76 0 TYP MAX 105 100 100 100 100 125 5 LTC2173-14 MIN 5.93 2 5.93 2 TYP 6.25 6.25 6.25 6.25 0 MAX 80 100 100 100 100 UNITS MHz ns ns ns ns ns TYP 4 4 4 4 0 MAX 100 100 100 100 5 3.8 2 3.8 2 Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On SYMBOL tSER CONDITIONS 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization (Note 8) (Note 8) (Note 8) Data, DCO, FR, 20% to 80% Data, DCO, FR, 20% to 80% tSER = 1ns l l l MIN TYP 1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) MAX UNITS s s s s s s Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tFRAME tDATA tPD tR tF FR to DCO Delay DATA to DCO Delay Propagation Delay Output Rise Time Output Fall Time DCO Cycle-Cycle Jitter Pipeline Latency 0.35 • tSER 0.35 • tSER 0.5 • tSER 0.5 • tSER 0.17 0.17 60 6 0.65 • tSER 0.65 • tSER s s s ns ns psP-P Cycles 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER 21754314p 6 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING CHARACTERISTICS SYMBOL tSCK PARAMETER SCK Period SPI Port Timing (Note 8) Write Mode Readback Mode, CSDO = 20pF RPULLUP , = 2k l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN 40 250 5 5 5 5 125 TYP MAX UNITS ns ns ns ns ns ns ns tS tH tDS tDH tDO CS to SCK Setup Time SCK to CS Setup Time SDI Setup Time SDI Hold Time SCK Falling to SDO Valid Readback Mode, CSDO = 20pF RPULLUP , = 2k Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz (LTC2174), or 80MHz (LTC2173), 2-lane output mode, differential ENC+/ ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2175), 105MHz (LTC2174), or 80MHz (LTC2173), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, unless otherwise noted. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4. Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and Ch.2 to Ch.4. 21754314p 7 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ tPD D5 D3 D1 0 D13 D11 D9 D7 D5 tSER D3 D1 0 D13 D11 D9 tFRAME tDATA tSER tSER N tENCH tENCL N+1 D4 D2 D0 0 D12 D10 D8 SAMPLE N-5 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-4 217514 TD01 SAMPLE N-6 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ tPD D7 D5 D3 D1 D13 D11 D9 D7 D5 tSER D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 tFRAME tDATA tSER tSER N tENCH tENCL N+1 N+2 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-5 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-4 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-3 217514 TD02 SAMPLE N-6 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– 21754314p 8 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR+ FR– OUT#A– OUT#A+ OUT#B– OUT#B+ tPD D9 D7 D5 D3 D13 D11 D9 tSER D7 D5 D3 D13 D11 D9 tFRAME tDATA tSER tSER N tENCH tENCL N+1 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-5 D6 D4 D2 D12 D10 D8 SAMPLE N-4 217514 TD03 SAMPLE N-6 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ tPD D1 D0 0 0 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 tSER D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10 SAMPLE N-4 217514 TD05 N tENCH tENCL N+1 tSER tFRAME tDATA tSER SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED 21754314p 9 LTC2175-14/ LTC2174-14/LTC2173-14 TIMING DIAGRAMS One-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ tPD D3 D2 D1 D0 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 tSER D4 D3 D2 D1 D0 D13 D12 D11 D10 SAMPLE N-4 217514 TD06 N tENCH tENCL N+1 tSER tFRAME tDATA tSER SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED One-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ tPD D5 D4 D3 D2 D13 D12 D11 D10 D9 SAMPLE N-5 D8 D7 D6 D5 tSER D4 D3 D2 D13 D12 D11 SAMPLE N-4 217514 TD07 N tENCH tENCL N+1 tSER tFRAME tDATA tSER SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED SPI Port Timing (Readback Mode) tS CS SCK tDO SDI SDO HIGH IMPEDANCE R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE 217514 TD04 21754314p 10 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2175-14: Integral Nonlinearity (INL) 2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G01 LTC2175-14: Differential Nonlinearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G02 LTC2175-14: 8k Point FFT, fIN = 5MHz –1dBFS, 125Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G03 LTC2175-14: 8k Point FFT, fIN = 30MHz –1dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2175-14: 8k Point FFT, fIN = 70MHz –1dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 0 20 30 40 FREQUENCY (MHz) 50 60 217514 G05 LTC2175-14: 8k Point FFT, fIN = 140MHz –1dBFS, 125Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G04 –90 –100 –110 –120 10 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G06 LTC2175-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 4000 5000 6000 LTC2175-14: Shorted Input Histogram 74 73 72 SNR (dBFS) 71 70 69 68 1000 0 8178 67 8180 8182 8184 OUTPUT CODE 8186 217514 G08 LTC2175-14: SNR vs Input Frequency, –1dB, 2V Range, 125Msps –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 217514 G07 COUNT 3000 2000 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 217514 G09 21754314p 11 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2175-14: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 95 90 SFDR (dBc AND dBFS) 85 80 75 70 65 110 100 90 SNR (dBc AND dBFS) 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 10 0 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 dBc 60 dBc 50 40 30 20 dBFS 70 LTC2175-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 80 LTC2175-14: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps dBFS SFDR (dBFS) 217514 G10 217514 G11 217514 G50 LTC2175-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 290 280 40 270 IOVDD (mA) IVDD (mA) 30 50 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 74 2-LANE, 3.5mA 73 72 SNR (dBFS) 125 217514 G51 LTC2175-14: SNR vs SENSE, fIN = 5MHz, –1dB 260 250 240 230 220 210 1-LANE, 3.5mA 2-LANE, 1.75mA 71 70 69 68 67 20 1-LANE, 1.75mA 10 0 0 25 50 75 100 SAMPLE RATE (Msps) 125 217514 G53 0 25 50 75 100 SAMPLE RATE (Msps) 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 217514 G12 LTC2174-14: Integral Nonlinearity (INL) 2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G14 LTC2174-14: Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G15 LTC2174-14: 8k Point FFT, fIN = 5MHz –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G16 21754314p 12 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2174-14: 8k Point FFT, fIN = 30MHz –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 20 30 40 FREQUENCY (MHz) 50 217514 G18 LTC2174-14: 8k Point FFT, fIN = 70MHz –1dBFS, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2174-14: 8k Point FFT, fIN = 140MHz –1dBFS, 105Msps –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 217517 G24 –90 –100 –110 –120 0 10 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 217514 G19 LTC2174-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 2000 1000 4000 5000 6000 LTC2174-14: Shorted Input Histogram 74 73 72 SNR (dBFS) 71 70 69 68 67 8197 8199 8201 OUTPUT CODE 8203 217514 G21 LTC2174-14: SNR vs Input Frequency, –1dB, 2V Range, 105Msps –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 226114 G20 COUNT 3000 0 8195 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 217514 G22 LTC2174-14: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 95 90 SFDR (dBc AND dBFS) 85 80 75 70 65 110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 LTC2174-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 230 dBFS 220 210 IVDD (mA) 0 dBc 200 190 180 170 160 LTC2174-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB SFDR (dBFS) 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 25 50 75 SAMPLE RATE (Msps) 100 217514 G54 217514 G23 217514 G24 21754314p 13 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2174-14: SNR vs SENSE, fIN = 5MHz, –1dB 74 73 72 INL ERROR (LSB) SNR (dBFS) 71 70 69 68 67 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384 217514 G26 LTC2173-14: Integral Nonlinearity (INL) 1.0 0.8 0.6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 LTC2173-14: Differential Nonlinearity (DNL) 0 4096 8192 12288 OUTPUT CODE 16384 217514 G27 217514 G25 LTC2173-14: 8k Point FFT, fIN = 5MHz –1dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2173-14: 8k Point FFT, fIN = 30MHz –1dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 20 30 FREQUENCY (MHz) 40 217514 G29 LTC2173-14: 8k Point FFT, fIN = 70MHz –1dBFS, 80Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 217514 G28 –90 –100 –110 –120 0 10 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 217514 G30 LTC2173-14: 8k Point FFT, fIN = 140MHz –1dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2173-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 80Msps 6000 5000 4000 COUNT 0 10 20 30 FREQUENCY (MHz) 40 217514 G32 LTC2173-14: Shorted Input Histogram 3000 2000 1000 0 8184 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 217514 G31 –90 –100 –110 –120 8186 8188 8190 OUTPUT CODE 8192 217514 G33 21754314p 14 LTC2175-14/ LTC2174-14/LTC2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2173-14: SNR vs Input Frequency, –1dB, 2V Range, 80Msps 74 73 72 SFDR (dBFS) SNR (dBFS) 71 70 69 68 67 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 70 65 85 80 75 95 90 SFDR (dBc AND dBFS) LTC2173-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps 110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 LTC2173-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps dBFS dBc 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 217514 G34 217514 G35 217514 G36 LTC2173-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 190 74 73 72 IVDD (mA) 170 SNR (dBFS) 71 70 69 68 67 140 0 20 40 60 SAMPLE RATE (Msps) 80 217514 G55 LTC2173-14: SNR vs SENSE, fIN = 5MHz, –1dB 350 300 PEAK-TO-PEAK JITTER (ps) 250 200 150 100 50 0 DCO Cycle-Cycle Jitter vs Serial Data Rate 180 160 150 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0 200 400 600 800 SERIAL DATA RATE (Mbps) 1000 217514 G52 217514 G37 21754314p 15 LTC2175-14/ LTC2174-14/LTC2173-14 PIN FUNCTIONS AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM12 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 2. Bypass to ground with a 0.1μF ceramic capacitor. AIN2+ (Pin 4): Channel 2 Positive Differential Analog Input. AIN2– (Pin 5): Channel 2 Negative Differential Analog Input. REFH (Pins 6,7): ADC High Reference. Bypass to pins 8, 9 with a 2.2μF ceramic capacitor and to ground with a 0.1μF ceramic capacitor. REFL (Pins 8,9): ADC Low Reference. Bypass to pins 6, 7 with a 2.2μF ceramic capacitor and to ground with a 0.1μF ceramic capacitor. AIN3+ (Pin 10): Channel 3 Positive Differential Analog Input. AIN3 – (Pin 11): Channel 3 Negative Differential Analog Input. VCM34 (Pin 12): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 3 and 4. Bypass to ground with a 0.1μF ceramic capacitor. AIN4 + (Pin 13): Channel 4 Positive Differential Analog Input. AIN4 – (Pin 14): Channel 4 Negative Differential Analog Input. VDD (Pins 15, 16, 51, 52): 1.8V Analog Power Supply. Bypass to ground with 0.1μF ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC+ (Pin 17): Encode Input. Conversion starts on the rising edge. ENC – (Pin 18): Encode Complement Input. Conversion starts on the falling edge. CS (Pin 19): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (Pin 20): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 21): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (Pins 22, 45, 49): ADC Power Ground. OGND (Pin 33): Output Driver Ground. OVDD (Pin 34): Output Driver Supply. Bypass to ground with a 0.1μF ceramic capacitor. SDO (Pin 46): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO is an input that enables internal 100Ω termination resistors on the digital outputs. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. PAR/ SER (Pin 47): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. 21754314p 16 LTC2175-14/ LTC2174-14/LTC2173-14 PIN FUNCTIONS VREF (Pin 48): Reference Voltage Output. Bypass to ground with a 1μF ceramic capacitor, nominally 1.25V. SENSE (Pin 50): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. Exposed Pad (Pin 53): Ground. The Exposed Pad must be soldered to the PCB ground. LVDS Outputs All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT4B –/OUT4B+, OUT4A–/OUT4A+ (Pins 23/24, 25/26): Serial data outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used. OUT3B –/OUT3B+, OUT3A–/OUT3A+ (Pins 27/28, 29/30): Serial data outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used. FR–/FR+ (Pins 31/32): Frame Start Outputs. DCO –/DCO+ (Pins 35/36): Data Clock Outputs. OUT2B –/OUT2B+, OUT2A–/OUT2A+ (Pins 37/38, 39/40): Serial data outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. OUT1B –/OUT1B+, OUT1A–/OUT1A+ (Pins 41/42, 43/44): Serial data outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. 21754314p 17 LTC2175-14/ LTC2174-14/LTC2173-14 FUNCTIONAL BLOCK DIAGRAM 1.8V VDD ENC+ ENC– 1.8V OVDD CH 1 ANALOG INPUT OUT1A S/H 14-BIT ADC CORE PLL OUT1B OUT2A CH 2 ANALOG INPUT S/H 14-BIT ADC CORE DATA SERIALIZER OUT2B OUT3A OUT3B CH 3 ANALOG INPUT S/H 14-BIT ADC CORE OUT4A OUT4B DATA CLOCK OUT CH 4 ANALOG INPUT S/H 14-BIT ADC CORE FRAME VREF 1μF 1.25V REFERENCE RANGE SELECT OGND SENSE REF BUF REFH REFL DIFF REF AMP VDD/2 MODE CONTROL REGISTERS GND REFH 0.1μF REFL VCM12 0.1μF VCM34 0.1μF PAR/SER CS SCK SDI SDO 217514 F01 2.2μF 0.1μF 0.1μF Figure 1. Functional Block Diagram 21754314p 18 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2175-14/LTC2174-14/LTC2173-14 are low power, 4-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM12 or VCM34 output pins, which are nominally VDD/2. For the LTC2175-14 VDD 10Ω CPARASITIC 1.8pF RON 25Ω CPARASITIC 1.8pF VDD CSAMPLE 3.5pF RON 25Ω 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. The four channels are simultaneously sampled by a shared encode circuit (Figure 2). INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC low pass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center 50Ω CSAMPLE 3.5pF 0.1μF ANALOG INPUT T1 1:1 25Ω 25Ω VCM 0.1μF AIN+ VDD 10Ω 25Ω 0.1μF AIN+ LTC2175-14 12pF AIN– 25Ω AIN– 217514 F03 T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 1.2V 10k ENC+ ENC– 10k 1.2V 217514 F02 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz. Figure 2. Equivalent Input Circuit. Only One of the Four Analog Channels is Shown. 21754314p 19 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. Reference The LTC2175-14/LTC2174-14/LTC2173-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. 50Ω VCM 0.1μF 0.1μF 50Ω VCM 0.1μF 0.1μF ANALOG INPUT T2 T1 25Ω 25Ω 0.1μF AIN+ LTC2175-14 4.7pF ANALOG INPUT 25Ω T1 0.1μF 25Ω 2.7nH 0.1μF AIN+ LTC2175-14 0.1μF AIN– 217514 F04 2.7nH AIN– 217514 F06 T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz Figure 6. Recommended Front End Circuit for Input Frequencies Above 300MHz 50Ω VCM VCM 0.1μF HIGH SPEED DIFFERENTIAL 0.1μF AMPLIFIER LTC2175-14 1.8pF ANALOG INPUT 200Ω 200Ω 25Ω 0.1μF AIN+ LTC2175-14 0.1μF ANALOG INPUT T2 T1 25Ω 25Ω 0.1μF AIN+ + – + 12pF – 0.1μF 0.1μF 25Ω AIN– 217514 F05 AIN– 217514 F07 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 7. Front End Circuit Using a High Speed Differential Amplifier Figure 5. Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz 21754314p 20 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The reference is shared by all four ADC channels, so it is not possible to independently adjust the input range of individual channels. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8. The 0.1μF capacitor between REFH and REFL should be as close to the pins as possible (not on the backside of the circuit board). Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). LTC2175-14 1.25V VREF 1μF 0.625V 5Ω 1.25V BANDGAP REFERENCE LTC2175-14 VDD DIFFERENTIAL COMPARATOR VDD 15k RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 217514 F10 ENC+ ENC– 30k TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.65V < VSENSE < 1.300V 0.1μF Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode 2.2μF 0.1μF 0.8x DIFF AMP 0.1μF REFL INTERNAL ADC LOW REFERENCE 217514 F08 LTC2175-14 1.8V TO 3.3V 0V ENC+ ENC– 30k CMOS LOGIC BUFFER 217514 F11 Figure 8. Reference Circuit Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode VREF 1μF LTC2175-14 1.25V EXTERNAL REFERENCE SENSE 1μF 217514 F09 Figure 9. Using an External 1.25V Reference 21754314p 21 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC – is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. 0.1μF 0.1μF T1 50Ω 100Ω 0.1μF 50Ω ENC– 217514 F12 ENC+ ENC+ LTC2175-14 PECL OR LVDS CLOCK LTC2175-14 0.1μF ENC– 217514 F13 0.1μF Figure 13. PECL or LVDS Encode Drive T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive 21754314p 22 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION DIGITAL OUTPUTS The digital outputs of the LTC2175-14/LTC2174-14/ LTC2173-14 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16, 14, or 12-bit serialization (see timing diagrams for details). Note that with 12-bit serialization the two LSBs are not available—this mode is included for compatibility with the 12-bit versions of these parts. The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode the SCK pin can select either 3.5mA or 1.75mA. Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the parallel programming mode the SDO pin enables internal termination. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2175-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2174-14) or 80MHz (LTC2173-14). SERIALIZATION MODE 2-Lane 2-Lane 2-Lane 1-Lane 1-Lane 1-Lane 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization MAXIMUM SAMPLING FREQUENCY fS (MHz) , 125 125 125 62.5 71.4 83.3 DCO FREQUENCY 4 • fS 3.5 • fS 3 • fS 8 • fS 7 • fS 6 • fS FR FREQUENCY fS 0.5 • fS fS fS fS fS SERIAL DATA RATE 8 • fS 7 • fS 6 • fS 16 • fS 14 • fS 12 • fS 21754314p 23 LTC2175-14/ LTC2174-14/LTC2173-14 APPLICATIONS INFORMATION DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1. Table 2. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) >1.000000V +0.999878V +0.999756V +0.000122V +0.000000V –0.000122V –0.000244V –0.999878V –1.000000V