LTC2217IUP-TR

LTC2217 16-Bit, 105Msps Low Noise ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LTC®2217 is a 105Msps sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P. The LTC2217 is perfect for demanding communications applications, with AC performance that includes 81.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specifications include ±3.5LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. Sample Rate: 105Msps 81.3dBFS Noise Floor 100dB SFDR SFDR >90dB at 70MHz 85fsRMS Jitter 2.75VP-P Input Range 400MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer LVDS or CMOS Outputs Single 3.3V Supply Power Dissipation: 1.19W Clock Duty Cycle Stabilizer Pin Compatible with LTC2208 64-Pin (9mm × 9mm) QFN Package APPLICATIONS ■ ■ ■ ■ ■ ■ Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents Pending. TYPICAL APPLICATION 3.3V SENSE VCM 2.2μF AIN+ ANALOG INPUT AIN– 1.575V COMMON MODE BIAS VOLTAGE INTERNAL ADC REFERENCE GENERATOR OVDD 0.5V TO 3.6V 1μF OF CLKOUT D15 • • • D0 OGND CLOCK/DUTY CYCLE CONTROL VDD GND ENC + ENC – SHDN DITH MODE LVDS RAND 1μF 1μF 3.3V 1μF 2217 TA01 64k Point FFT, FIN = 4.9MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 40 30 FREQUENCY (MHz) 50 2217 TA01b S/H AMP – 16-BIT PIPELINED ADC CORE CORRECTION LOGIC AND SHIFT REGISTER OUTPUT DRIVERS CMOS OR LVDS ADC CONTROL INPUTS AMPLITUDE (dBFS) + 2217f 1 LTC2217 ABSOLUTE MAXIMUM RATINGS OVDD = VDD (Notes 1 and 2) PIN CONFIGURATION TOP VIEW 64 NC 63 RAND 62 MODE 61 LVDS 60 OF+/OFA 59 OF–/DA15 58 D15+/DA14 57 D15–/DA13 56 D14+/DA12 55 D14–/DA11 54 D13+/DA10 53 D13–/DA9 52 D12+/DA8 51 D12–/DA7 50 OGND 49 OVDD SENSE 1 GND 2 VCM 3 GND 4 VDD 5 VDD 6 GND 7 AIN+ 8 AIN– 9 GND 10 GND 11 ENC+ 12 ENC– 13 GND 14 VDD 15 VDD 16 65 48 D11+/DA6 47 D11–/DA5 46 D10+/DA4 45 D10–/DA3 44 D9+/DA2 43 D9–/DA1 42 D8+/DA0 41 D8–/CLKOUTA 40 CLKOUT+/CLKOUTB 39 CLKOUT –/OFB 38 D7+/DB15 37 D7–/DB14 36 D6+/DB13 35 D6–/DB12 34 D5+/DB11 33 D5–/DB10 Supply Voltage (VDD) ................................... –0.3V to 4V Digital Output Ground Voltage (OGND)........ –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................–0.3V to (OVDD + 0.3V) Power Dissipation............................................ 2000mW Operating Temperature Range LTC2217C ................................................ 0°C to 70°C LTC2217I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2217CUP#PBF LTC2217IUP#PBF LEAD BASED FINISH LTC2217CUP LTC2217IUP TAPE AND REEL LTC2217CUP#TRPBF LTC2217IUP#TRPBF TAPE AND REEL LTC2217CUP#TR LTC2217IUP#TR PART MARKING LTC2217UP LTC2217UP PART MARKING LTC2217UP LTC2217UP PACKAGE DESCRIPTION 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN PACKAGE DESCRIPTION 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Integral Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Transition Noise External Reference Internal Reference External Reference External Reference ● CONVERTER CHARACTERISTICS CONDITIONS VDD 17 GND 18 SHDN 19 DITH 20 D0–/DB0 21 +/DB1 22 DO D1–/DB2 23 D1+/DB3 24 D2–/DB4 25 D2+/DB5 26 D3–/DB6 27 D3+/DB7 28 D4–/DB8 29 D4+/DB9 30 OGND 31 OVDD 32 MIN ● ● ● TYP ±1.3 ±1.3 0.18/–0.22 ±1.3 ±4 ±0.3 –65 ±12 2 MAX ±3.5 ±4 ±1 ±6 ±1 UNITS LSB LSB LSB mV μV/°C %FS ppm/°C ppm/°C Differential Analog Input (Note 5) TA = 25°C Differential Analog Input (Note 5) Differential Analog Input (Note 6) LSBRMS 2217f 2 LTC2217 ANALOG INPUT SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS CIN tAP tJITTER CMRR BW-3dB PARAMETER Analog Input Range (AIN+ – AIN–) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Analog Input Capacitance Sample-and-Hold Acquisition Delay Time Sample-and-Hold Aperture Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth 1.2V < (AIN+ = AIN–) ENC– The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 3.135V ≤ VDD ≤ 3.465V Differential Input (Note 7) 0V ≤ AIN+, AIN– ≤ VDD 0V ≤ SENSE ≤ VDD ● ● ● MIN 1.2 –1 –3 TYP 2.75 1.575 MAX 1.8 1 3 UNITS VP-P V μA μA μA μA pF pF ns fs RMS dB MHz 10 10 9.1 1.8 0.35 85 80 400 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS with 2.75V range unless otherwise noted. (Note 4) SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 15MHz Input, TA = 25°C 15MHz Input 30MHz Input, TA = 25°C 70MHz Input, TA = 25°C 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 15MHz Input, TA = 25°C 15MHz Input 30MHz Input 70MHz Input, TA = 25°C 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input ● ● ● ● ● ● DYNAMIC ACCURACY MIN 80.4 80.1 79.6 79.3 TYP 81.2 81.1 80.7 81.1 80.4 80.1 78.8 100 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 88 87 85 83 100 99 95 92 88 85 105 93 93 105 105 103 95 2217f 3 LTC2217 DYNAMIC ACCURACY SYMBOL S/(N+D) PARAMETER Signal-to-Noise Plus Distortion Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS with 2.75V range unless otherwise noted. (Note 4) CONDITIONS 5MHz Input 15MHz Input, TA = 25°C 15MHz Input 30MHz Input 70MHz Input, TA = 25°C 70MHz Input 140MHz Input ● ● MIN 79.9 79.7 78.7 78.2 TYP 81.2 81 80.6 81.1 80 79.5 78.8 105 105 105 105 100 115 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc dBc SFDR Spurious Free Dynamic Range at –25dBFS Dither “OFF” 5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range at –25dBFS Dither “ON” 5MHz Input 15MHz Input 30MHz Input 70MHz Input 140MHz Input ● 100 115 115 115 110 100 90 IMD Intermodulation Distortion fIN1 = 14MHz, fIN2 = 21MHz, –7dBFS fIN1 = 67MHz, fIN2 = 74MHz, –7dBFS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 3.135V ≤ VDD ≤ 3.465V | IOUT | ≤ 0.8mA MIN 1.475 TYP 1.575 ±60 2.4 1.1 MAX 1.675 UNITS V ppm/°C COMMON MODE BIAS CHARACTERISTICS mV/ V Ω 2217f 4 LTC2217 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VID VICM RIN CIN Logic Inputs VIH VIL IIN CIN OVDD = 3.3V VOH VOL ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL STANDARD LVDS VOD VOS Low Power LVDS VOD VOS Differential Output Voltage Output Common Mode Voltage 100Ω Differential Load 100Ω Differential Load ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance CONDITIONS (Note 7) Internally Set Externally Set (Note 7) (See Figure 2) (Note 7) VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) ● ● ● ● MIN 0.2 TYP MAX UNITS V Encode Inputs (ENC+, ENC–) 1.6 1.2 6 3 2 0.8 ±10 1.5 3 V V kΩ pF V V μA pF LOGIC OUTPUTS (CMOS MODE) High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage VDD = 3.3V VDD = 3.3V VOUT = 0V VOUT = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V IO = – 200μA IO = 1.60mA IO = – 200μA IO = 1.60mA IO = –10μA IO = – 200μA IO = 160μA IO = 1.6mA 3.299 3.29 0.01 0.10 –50 50 2.49 0.1 1.79 0.1 0.4 V V V V mA mA V V V V ● ● 3.1 LOGIC OUTPUTS (LVDS MODE) Differential Output Voltage Output Common Mode Voltage 100Ω Differential Load 100Ω Differential Load ● ● 247 1.125 125 1.125 350 1.2 175 1.2 454 1.375 250 1.375 mV V mV V 2217f 5 LTC2217 POWER REQUIREMENTS SYMBOL VDD PSHDN OVDD IVDD IOVDD PDIS OVDD IVDD IOVDD PDIS OVDD IVDD PDIS PARAMETER Analog Supply Voltage Shutdown Power Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Power Dissipation (Note 8) (Note 8) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) CONDITIONS (Note 8) SHDN = VDD (Note 8) ● ● ● ● ● MIN 3.135 TYP 3.3 17 MAX 3.465 UNITS V mW Standard LVDS Output Mode 3 3.3 365 75 1450 3 3.3 363 42 1335 0.5 360 1190 3.6 430 90 1716 3.6 430 50 1584 3.6 430 1420 V mA mA mW V mA mA mW V mA mW Low Power LVDS Output Mode ● ● ● ● CMOS Output Mode ● ● ● TIMING CHARACTERISTICS SYMBOL fS tL tH PARAMETER Sampling Frequency ENC Low Time ENC High Time The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS (Note 8) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) (Note 7) (Note 7) (tC-tD) (Note 7) ● ● ● ● ● MIN 1 4.52 3.1 4.52 3.1 1.3 1.3 –0.6 TYP 4.762 4.762 4.762 4.762 2.5 2.5 0 0.5 0.5 7 MAX 105 500 500 500 500 3.8 3.8 0.6 UNITS MHz ns ns ns ns ns ns ns ns ns Cycles LVDS Output Mode (Standard and Low Power) tD tC tSKEW tRISE tFALL Data Latency tD tC tSKEW Data Latency ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Output Rise Time Output Fall Time Data Latency ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Data Latency (Note 7) (Note 7) (tC-tD) (Note 7) Full Rate CMOS Demuxed ● ● ● ● ● ● CMOS Output Mode 1.3 1.3 –0.6 2.7 2.7 0 7 7 4 4 0.6 ns ns ns Cycles Cycles 2217f 6 LTC2217 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 105MHz, LVDS outputs, differential ENC+/ ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.75VP-P with differential drive, unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. TIMING DIAGRAM LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tAP ANALOG INPUT N+1 N+3 N+4 N+2 N tH tL ENC– ENC+ tD D0-D15, OF tC N–7 N–6 N–5 N–4 N–3 CLKOUT+ CLKOUT – 2217 TD01 2217f 7 LTC2217 TIMING DIAGRAMS Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+3 N+4 N+2 tH tL ENC– ENC+ tD DA0-DA15, OFA tC CLKOUTA CLKOUTB N–7 N–6 N–5 N–4 N–3 N DB0-DB15, OFB HIGH IMPEDANCE 2217 TD02 Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+1 N+3 N+4 N+2 tH tL ENC– ENC+ tD DA0-DA15, OFA tD DB0-DB15, OFB tC CLKOUTA CLKOUTB 2217 TD03 N N–8 N–6 N–4 N–7 N–5 N–3 2217f 8 LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) vs Output Code - Dither “Off“ 2.0 1.5 1.0 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 Integral Nonlinearity (INL) vs Output Code - Dither “On“ 1.0 0.8 0.6 Differential Nonlinearity (DNL) vs Output Code 0.5 0.0 –0.5 –1.0 –1.5 –2.0 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 49152 OUTPUT CODE 65536 2217 G01 0 16384 32768 49152 OUTPUT CODE 65536 2217 G02 0 16384 32768 49152 OUTPUT CODE 65536 2217 G03 AC Grounded Input Histogram 14000 12000 64k Point FFT, fIN = 4.9MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G05 64k Point FFT, fIN = 15.1MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G06 COUNT 8000 6000 4000 2000 0 32736 32745 OUTPUT CODE 32754 2217 G04 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 10000 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G07 64k Point FFT, fIN = 15.1MHz, –20dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G08 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, –7dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G09 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 2217f 9 LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point 2-Tone FFT, fIN = 14.25MHz and 21.5MHz, –25dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G10 SFDR vs Input Level, fIN = 15.2MHz, Dither “Off” 140 130 120 110 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 140 130 120 110 100 90 80 70 60 50 40 SFDR vs Input Level, fIN = 15.2MHz, Dither “On” AM PLITUDE (dBFS) 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 2217 G11 2217 G12 SNR vs Input Level, fIN = 15.2MHz 82 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 64k Point FFT, fIN = 28.7MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 64k Point FFT, fIN = 30.1MHz, –20dBFS, Dither “On” 81 AM PLITUDE (dBFS) SNR (dBFS) 80 79 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) AMPLITUDE (dBFS) 0 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G14 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G15 2217 G13 64k Point FFT, fIN = 70.2MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G16 64k Point FFT, fIN = 70.1MHz, –10dBFS, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G17 64k Point FFT, fIN = 70.1MHz, –20dBFS, Dither “Off” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G18 AM PLITUDE (dBFS) AM PLITUDE (dBFS) AM PLITUDE (dBFS) 2217f 10 LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT, fIN = 70.1MHz, –20dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G19 SFDR vs Input Level, fIN = 70.5MHz, Dither “Off” 140 130 120 110 140 130 120 110 SFDR vs Input Level, fIN = 70.5MHz, Dither “On” SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 0 AMPLITUDE (dBFS) 100 90 80 70 60 50 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 100 90 80 70 60 50 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 2217 G20 2217 G21 SNR vs Input Level, FIN = 70.5MHz 82 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, –7dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, –15dBFS, Dither “On” 81 AMPLITUD E (dBFS) SNR (dBFS) 80 79 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 AMPLITUDE (dBFS) 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G23 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G24 2217 G22 64k Point 2-Tone FFT, fIN = 67.2MHz and 74.4MHz, –25dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G25 64k Point FFT, fIN = 140.5MHz, –1dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G26 64k Point FFT, fIN = 140.1MHz, –20dBFS, Dither “On” 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 FREQUENCY (MHz) 50 2217 G27 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 2217f 11 LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs Input Level, fIN = 140.5MHz, Dither “Off” 140 130 120 110 SFDR (dBc AND dBFS) SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 140 130 120 110 100 90 80 70 60 50 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 78 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 SNR (dBFS) 80 81 SFDR vs Input Level, fIN = 140.5MHz, Dither “On” 82 SNR vs Input Level, fIN = 140.5MHz 79 2217 G28 2217 G29 2217 G30 SFDR (HD2 and HD3) vs Input Frequency 110 105 82 81 80 HD2 90 SFDR 85 80 75 70 0 50 100 150 200 INPUT FREQUENCY (MHz) 250 2217 G31 SNR vs Input Frequency 110 105 SNR and SFDR vs Sample Rate, fIN = 5.2MHz LIMIT SFDR SNR (dBFS) AND SFDR (dBc) SFDR, HD2, HD3 (dBc) 100 SNR (dBFS) 95 HD3 100 95 90 85 SNR 80 75 70 0 40 80 120 SAMPLE RATE (MSPS) 160 2217 G33 79 78 77 76 0 50 100 150 200 INPUT FREQUENCY (MHz) 250 2217 G32 SNR and SFDR vs Supply Voltage (VDD), fIN = 5.1MHz 110 LOWER LIMIT 105 SNR (dBFS) AND SFDR (dBc) 100 SFDR UPPER LIMIT 90 85 SNR 80 75 70 2.8 325 300 3.0 3.2 3.4 SUPPLY VOLTAGE (V) 3.6 2217 G34 IVDD vs Sample Rate and Supply Voltage, fIN = 5MHz, –1dBFS 450 425 400 IVDD (mA) 375 VDD = 3.465V 350 VDD = 3.135V VDD = 3.3V SNR (dBFS) AND SFDR (dBc) 110 SNR and SFDR vs Clock Duty Cycle, fIN = 5.2MHz 100 95 90 80 SFDR DCS OFF SNR DCS OFF SFDR DCS ON SNR DCS ON 30 40 50 60 DUTY CYCLE (%) 70 2217 G36 70 60 0 50 100 150 SAMPLE RATE (Msps) 200 2217 G35 2217f 12 LTC2217 TYPICAL PERFORMANCE CHARACTERISTICS Normalized Full Scale vs Temperature, Internal Reference, 5 Units 1.005 1.004 1.003 NORMALIZED FULL SCALE OFFSET VOLTAGE (mV) –20 0 20 40 TEMPERATURE (°C) 60 80 2217 G37 Input Offset Voltage vs Temperature, Internal Reference, 5 Units 5 4 3 2 1 0 –1 –2 –3 –4 –5 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 2217 G38 1.002 1.001 1 0.999 0.998 0.997 0.996 0.995 –40 Normalized Full Scale vs Temperature, External Reference, 5 Units 1.005 1.004 NORMALIZED FULL SCALE 1.003 1.002 1.001 1 0.999 0.998 0.997 0.996 0.995 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 2217 G39 Input Offset Voltage vs Temperature, External Reference, 5 Units 5 4 3 OFFSET VOLTAGE (mV) 2 1 0 –1 –2 –3 –4 –5 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 2217 G40 SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, –1dBFS 110 105 100 0.5 0.4 0.3 Mid-Scale Settling After Wake Up from Shutdown or Starting Encode Clock 0.5 WAKE-UP 0.4 0.3 Full-Scale Settling After Wake Up from Shutdown or Starting Encode Clock WAKE-UP FULL-SCALE ERROR (%) 95 SFDR (dBc) 90 85 80 75 70 65 60 0.5 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 CLOCK START FULL-SCALE ERROR (%) 5MHz 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 CLOCK START 70MHz 0.75 1 1.25 1.5 1.75 2 2217 G41 –0.5 0 300 600 900 1200 1500 TIME AFTER WAKE-UP OR CLOCK START (μs) 2217 G42 0 400 800 1200 1600 2000 2217 G43 ANALOG INPUT COMMON MODE VOLTAGE (V) TIME AFTER WAKE-UP OR CLOCK START (μs) 2217f 13 LTC2217 PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.75V. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recommended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors. AIN+ (Pin 8): Positive Differential Analog Input. AIN– (Pin 9): Negative Differential Analog Input. (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+. ENC– (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC –. Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1μF capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in high impedance state in full rate CMOS mode. OGND (Pins 31 and 50): Output Driver Ground. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 1μF capacitor. OFB (Pin 39): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under flow has occurred on the B bus. At high impedance state in full rate CMOS mode. ENC+ CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. OFA (Pin 60): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under flow has occurred on the A bus. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 2217f 14 LTC2217 PIN FUNCTIONS For LVDS Mode. STANDARD or LOW POWER SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.75V. GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. VCM (Pin 3): 1.575V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2μF. Ceramic chip capacitors are recommended. VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors. AIN + (Pin 8): Positive Differential Analog Input. AIN – (Pin 9): Negative Differential Analog Input. ENC + (Pin 12): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+. ENC – (Pin 13): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC –. Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1μF capacitor for a single-ended Encode signal. SHDN (Pin 19): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs are set in high impedance state. DITH (Pin 20): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of the data sheet for details on dither operation. D0–/D0+ to D15–/D15+ (Pins 21-30, 33-38, 41-48 and 51-58): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D15+/D15– is the MSB. OGND (Pins 31 and 50): Output Driver Ground. OVDD (Pins 32 and 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF capacitor. CLKOUT–/CLKOUT + (Pins 39 and 40): LVDS Data Valid 0utput. Latch data on the rising edge of CLKOUT +, falling edge of CLKOUT –. OF–/OF+ (Pins 59 and 60): Over/Under Flow Digital Output OF is high when an over or under flow has occurred. LVDS (Pin 61): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode. MODE (Pin 62): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin 63): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. The mode of operation reduces the effects of digital output interference. NC (Pin 64): Not Connected Internally. For pin compatibility with the LTC2208 this pin should be connected to GND or VDD as required. Otherwise no connection. GND (Exposed Pad Pin 65): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 2217f 15 LTC2217 BLOCK DIAGRAM AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND VDD AIN– DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER RANGE SELECT SENSE PGA VCM ADC REFERENCE ADC CLOCKS OVDD CLKOUT+ CLKOUT– OF+ OF– D15+ D15– D0+ D0– BUFFER VOLTAGE REFERENCE DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • OGND ENC+ ENC– SHDN RAND M0DE LVDS DITH 2217 F01 Figure 1. Functional Block Diagram 2217f 16 LTC2217 OPERATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency (Nyquist Frequency). Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (Nyquist Frequency). THD is expressed as: ⎛ ⎜ THD = –20Log ⎜ ⎜ ⎝ by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB from a full scale input signal. Aperture Delay Time The time from when a rising ENC + equals the ENC– voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal-to-noise ratio term due to the jitter alone will be: SNRJITTER = – 20log (2π • fIN • tJITTER) This formula states SNR due to jitter alone at any amplitude in terms of dBc. (V 2 2 + V3 + V4 +… VN V1 2 2 2 ) ⎞ ⎟ ⎟ ⎟ ⎠ where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused 2217f 17 LTC2217 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2217 is a CMOS pipelined multistep converter with a low noise front-end. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2217 has two phases of operation, determined by the state of the differential ENC+/ENC – input pins. For brevity, the text will refer to ENC+ greater than ENC – as ENC high and ENC+ less than ENC – as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2217 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transitors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the LTC2217 VDD RPARASITIC 3Ω CPARASITIC 1.8pF RPARASITIC 3Ω AIN– CPARASITIC 1.8pF VDD RON 20Ω CSAMPLE 7.3pF RON 20Ω CSAMPLE 7.3pF AIN+ VDD 1.6V 6k ENC+ ENC– 6k 1.6V 2217 F02 Figure 2. Equivalent Input Circuit 2217f 18 LTC2217 APPLICATIONS INFORMATION input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing ±0.6875V for the 2.75V range, around a common mode voltage of 1.575V. The VCM output pin (Pin 3) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2μF or greater. Input Drive Impedance As with all high performance, high speed ADCs the dynamic performance of the LTC2217 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample and hold circuit will connect the sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2 • fENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. INPUT DRIVE CIRCUITS Input Filtering A first-order RC low-pass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC2217 has a very broadband S/H circuit, DC to 400MHz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended RC filter. Figures 3 and 4 show two examples of input RC filtering for two ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated—this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2217 does not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. Transformer Coupled Circuits Figure 3 shows the LTC2217 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50Ω can reduce the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. VCM 5Ω 10Ω T1 8.2pF 35Ω 8.2pF 0.1μF 10Ω T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2μF 35Ω 5Ω AIN– 8.2pF 2217 F03 2.2μF 5Ω AIN+ LTC2217 Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 100MHz 2217f 19 LTC2217 APPLICATIONS INFORMATION Figure 4 shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high-frequency response and balance than flux coupled center-tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.575V. VCM 5Ω 10Ω 25Ω 0.1μF T1 1:1 25Ω 0.1μF 4.7pF 2.2μF 5Ω AIN+ 4.7pF LTC2217 AMPLIFIER = LTC6600-20, LTC1993, ETC. VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT 2.2μF 25Ω 12pF AIN+ LTC2217 + CM + – 25Ω – AIN– 12pF 2217 F05 0.1μF ANALOG INPUT Figure 5. DC Coupled Input with Differential Amplifier 10Ω 5Ω AIN– 4.7pF 2217 F04 T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2μF Figure 4. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 100MHz to 250MHz Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. Reference Operation Figure 6 shows the LTC2217 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2217 has three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.75VP-P. A 1.575V output, VCM, is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; which will not be stable without this capacitor. The minimum value required for stability is 2.2μF. RANGE SELECT AND GAIN CONTROL SENSE PGA TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT AN EXTERNAL 2.5V REFERENCE OR INPUT AN EXTERNAL 1.25V REFERENCE INTERNAL ADC REFERENCE 2.5V BANDGAP REFERENCE VCM 2.2μF BUFFER 1.575V 2217 F06 Figure 6. Reference Circuit 2217f 20 LTC2217 APPLICATIONS INFORMATION The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has very stringent settling requirements and therefore is not accessible for external use. The SENSE pin can be driven ±5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1μF ceramic capacitor. 1.575V VCM 2.2μF 2 6 SENSE 2.2μF VDD 2217 F07 3. If the ADC is clocked with a fixed-frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. LTC2217 VDD TO INTERNAL ADC CLOCK DRIVERS VDD 1.6V 6k ENC+ 1.6V 6k ENC– LTC2217 3.3V 1μF LTC1461-2.5 4 Figure 7. A 2.75V Range ADC with an External 2.5V Reference Driving the Encode Inputs The noise performance of the LTC2217 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 2217 F08a Figure 8a. Equivalent Encode Input Circuit 0.1μF T1 50Ω 8.2pF ENC+ 100Ω LTC2217 0.1μF 50Ω 0.1μF ENC– 2217 F08b T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 8b. Balun-Driven Encode 2217f 21 LTC2217 APPLICATIONS INFORMATION VTHRESHOLD = 1.6V ENC+ 1.6V ENC– 0.1μF 2217 F09 LTC2217 The lower limit of the LTC2217 sample rate is determined by droop affecting the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2217 is 1Msps. DIGITAL OUTPUTS Digital Output Modes Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 130Ω Q0 130Ω ENC+ D0 ENC– Q0 83Ω 83Ω 2217 F10 LTC2217 The LTC2217 can operate in four digital output modes: standard LVDS, low power LVDS, full rate CMOS, and demultiplexed CMOS. The LVDS pin selects the mode of operation. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the LVDS pin. Table 1. LVDS Pin Function LVDS DIGITAL OUTPUT MODE Full-Rate CMOS Demultiplexed CMOS Low Power LVDS LVDS 0V(GND) 1/3VDD 2/3VDD VDD Figure 10. ENC Drive Using a CMOS to PECL Translator Maximum and Minimum Encode Rates The maximum encode rate for the LTC2217 is 105Msps. For the ADC to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 4.5ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. Digital Output Buffers (CMOS Modes) Figure 11 shows an equivalent circuit for a single output buffer in CMOS Mode, Full-Rate or Demultiplexed. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2217 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the 2217f 22 LTC2217 APPLICATIONS INFORMATION output may be used, but is not required since the ADC has a series resistor of 43Ω on-chip. Lower OVDD voltages will also help reduce interference from the digital outputs. LTC2217 OVDD VDD VDD 0.5V TO 3.6V 0.1μF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT OGND resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. In Low Power LVDS Mode 1.75mA is steered between the differential outputs, resulting in ±175mV at the LVDS receiver’s 100Ω termination resistor. The output common mode voltage is 1.20V, the same as standard LVDS Mode. Data Format The LTC2217 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 2 shows the logic states for the MODE pin. Table 2. MODE Pin Function MODE 0(GND) 1/3VDD 2/3VDD VDD OUTPUT FORMAT Offset Binary Offset Binary 2’s Complement 2’s Complement CLOCK DUTY CYCLE STABILIZER Off On On Off 2217 F11 Figure 11. Equivalent Circuit for a Digital Output Buffer Digital Output Buffers (LVDS Modes) Figure 12 shows an equivalent circuit for an LVDS output pair. A 3.5mA current is steered from OUT+ to OUT– or vice versa, which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.20V. For proper operation each LVDS output pair must be terminated with an external 100Ω termination LTC2217 3.5mA VDD VDD OVDD 3.3V 0.1μF OVDD 43Ω DATA FROM LATCH PREDRIVER LOGIC 10k 10k OVDD 43Ω 100Ω LVDS RECEIVER 1.20V + – 2217 F12 OGND Figure 12. Equivalent Output Buffer in LVDS Mode 2217f 23 LTC2217 APPLICATIONS INFORMATION Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF– pins indicates an overflow or underflow. Output Clock The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated as CLKOUTA falls and CLKOUTB rises. In demultiplexed CMOS mode the B bus data will be updated as CLKOUTA falls and CLKOUTB rises. In Full Rate CMOS Mode, only the A data bus is active; data may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. In demultiplexed CMOS mode CLKOUTA and CLKOUTB will toggle at 1/2 the frequency of the encode signal. Both the A bus and the B bus may be latched on the rising edge of CLKOUTA or the falling edge of CLKOUTB. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling, or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. In CMOS mode OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In LVDS Mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND. D15 D15 ⊕ D0 LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high. LTC2217 CLKOUT CLKOUT OF OF D14 D14 ⊕ D0 D2 • • • D2 ⊕ D0 D1 D1 ⊕ D0 RAND = HIGH, SCRAMBLE ENABLED RAND D0 2217 F13 D0 Figure 13. Functional Equivalent of Digital Output Randomizer 2217f 24 LTC2217 APPLICATIONS INFORMATION PC BOARD FPGA CLKOUT Internal Dither The LTC2217 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 15, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in typically less than 0.5dB elevation in the noise floor of the ADC as compared to the noise floor with dither off, when a suitable input termination is provided (see Demo Board schematic DC996B). 2217 F14 OF D15 ⊕ D0 D15 D14 ⊕ D0 D14 LTC2217 D2 ⊕ D0 • • • D2 D1 ⊕ D0 D1 D0 D0 Figure 14. Descrambling a Scrambled Digital Output LTC2217 CLKOUT OF D15 • • • D0 AIN+ ANALOG INPUT AIN– S/H AMP 16-BIT PIPELINED ADC CORE DIGITAL SUMMATION OUTPUT DRIVERS CLOCK/DUTY CYCLE CONTROL PRECISION DAC MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 2217 F15 ENC + ENC – DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit 2217f 25 LTC2217 APPLICATIONS INFORMATION Grounding and Bypassing The LTC2217 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2217 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2217 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2217 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible. 2217f 26 LTC2217 APPLICATIONS INFORMATION Layer 1 Component Side Layer 2 GND Plane 2217f 27 LTC2217 APPLICATIONS INFORMATION Layer 3 GND Layer 4 GND 2217f 28 LTC2217 APPLICATIONS INFORMATION Layer 5 GND Layer 6 Bottom Side 2217f 29 3 VC1 VC2 VC3 VC4 VC5 5 GND R3 DNP R16 100Ω R17 100Ω 4 5 I1N I1P I2N I2P I3N I3P I4N I4P I5N I5P I6N I6P I7N I7P I8N I8P VE1 VE2 VE3 VE4 VE5 O8N O8P 29 28 O7N O7P 31 30 O6N O6P 33 32 O5N O5P 35 34 O4N O4P 39 38 O3N U3 FIN1108 O3P 41 40 O2N O2P 43 42 6 7 8 9 10 11 14 15 16 17 18 19 20 21 O1N O1P 5 44 R18 100Ω R19 100Ω R20 100Ω R21 100Ω 3 22 27 46 13 EN12 EN34 EN58 EN78 EN OFF 6 VDD ON 4 12 25 26 47 48 LTC2217 R36 R44 86.6Ω 86.6Ω R10 10Ω 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC OF+ OF– D15+ D15– D14+ D14– D13+ D13– D12+ RAND MODE LVDS D12– R22 100Ω D11+ D11– D10+ D10– D9+ D9– D8+ D8– U2 LTC2217IUP CLKCOUT+ CLKOUT– D7– D8+ D8– D5+ D5– R31 100Ω 65 4 5 6 7 8 9 R34 100Ω 2 J2 MODE 3 VDD GND R8 1000Ω 6 4 R7 1000Ω 5 R35 100Ω R38 100Ω R39 100Ω R40 100Ω 10 11 14 15 16 17 18 19 20 21 R32 100Ω R33 100Ω R6 1000Ω 1 33 34 35 VC1 VC2 VC3 VC4 VC5 36 37 12 25 26 47 48 D7+ 38 39 3.3V 40 41 1 2 23 36 37 42 43 44 45 46 R30 100Ω 47 48 R23 100Ω R12 33.2Ω R27 10Ω C8 8.2pF 1 SENSE GND2 VCM GND VDD5 VDD6 GND7 AINP AINN GND10 GND11 ENCP ENCN GND14 VDD15 VDD16 VDD17 GND18 SHDN DITH D0– D0+ D1– D1+ D2– D2+ D3– D3+ D4– D4+ OGND31 OVDD32 R15 5Ω 3 C13 2.2μF 4 5 6 C17 2.2μF R14 1000Ω 8 9 10 11 12 13 14 15 16 J3 1 3 17 18 19 20 21 22 23 24 25 26 27 27 29 30 31 5 RUN OFF 6 32 SHDN ON 4 VCC DITHER 2 R13 100Ω 7 2 OGND50 OVDD49 C10 8.2pF •• APPLICATIONS INFORMATION VE1 VE2 VE3 VE4 VE5 C20 0.1μF C22 0.1μF T2 FREQUENCY 1MHZ TO 70MHZ 70MHZ TO 140MHZ 1MHZ TO 70MHZ 2 WBC1-1LB 70MHZ TO 140MHZ 3 4 GND EN DOUT+ DOUT– 1MHZ TO 70MHZ 70MHZ TO 140MHZ C15 0.1μF MABAES0060 WBC1-1LB GND VCC 7 6 5 RIN– RIN+ 1 8 U5 FIN1101K8X MABAES0060 WBC1-1LB MABAES0060 R41 100Ω 3.3V 1 2 23 36 37 30 3.3V VCC J4 1 2 R9 10Ω R28 10Ω R11 33.2Ω C8 4.7pF C26 0.1μF C25 0.1μF C16 0.1μF C18 OPT C19 OPT R37 100Ω MEC8-150-02-L-D-EDGE_CONNRE-DIM J1E J1O 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 3 22 27 46 13 EN12 EN34 EN58 EN78 EN I1N I1P I2N I2P I3N I3P I4N I4P I5N I5P I6N I6P I7N I7P I8N I8P O1N O1P O2N O2P U4 O3N FIN1108 O3P O4N O4P O5N O5P O6N O6P O7N O7P O8N O8P 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 R24 100k 3.3V R29 4990Ω 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 C27 0.1μF R25 4990Ω R42 FERRITE BEAD R43 FERRITE BEAD 8 VCC C14 4.7μF C24 4.7μF C38 4.7μF ARRAY EEPROM U1 24LC02ST 6 6CL 6DA WP A2 A1 GND 4 A0 5 7 3 2 1 R26 4990Ω C34 0.1μF C35 0.1μF C36 0.1μF C28 0.1μF C29 0.1μF C30 0.1μF C31 0.1μF C32 0.1μF 2217 F16 R45 86.6Ω C6 J5 AIN 0.01μF L1 56nH T1 MABA-007159- T2 000000 •• C7 0.01μF C5 0.01μF C12 0.1μF TP1 EXT REF J7 ENCODE C2 T3 CLOCK 0.01μF ETC1-1-13 R5 5.1Ω •• R2 49.9Ω C1 0.01μF C3 0.01μF R1 49.9Ω C4 8.2pF R4 5.1Ω VCC VCC TP5 3.3V 1 2 3 4 TP2 PWR GND 5 J9 AUX PWR CONNECTOR 6 *VERSION TABLE ASSEMBLY U2 BITS C8 C9-10 L1 R36, 44 R45 DC996B-E LTC2217IUP 16 4.7pF 8.2pF 56nH 86.6 86.6 DC996B-F LTC2217IUP 16 1.8pF 3.9pF 18nH 43.2 182 DC996B-G LTC2216IUP 16 4.7pF 8.2pF 56nH 86.6 86.6 DC996B-H LTC2216IUP 16 1.8pF 3.9pF 18nH 43.2 182 DC996B-I LTC2215IUP 16 4.7pF 8.2pF 56nH 86.6 86.6 DC996B-J LTC2215IUP 16 1.8pF 3.9pF 18nH 43.2 182 2217f LTC2217 PACKAGE DESCRIPTION UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ± 0.05 7.15 ± 0.05 7.50 REF 8.10 ± 0.05 9.50 ± 0.05 (4 SIDES) 7.15 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP R = 0.10 TYP 63 64 0.40 ± 0.10 1 2 PIN 1 CHAMFER C = 0.35 PIN 1 TOP MARK (SEE NOTE 5) 7.15 ± 0.10 7.50 REF (4-SIDES) 7.15 ± 0.10 (UP64) QFN 0406 REV C 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 2217f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2217 RELATED PARTS PART NUMBER DESCRIPTION LTC1749 LTC1750 LT1993 LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC2215 LTC2216 LTC2220 LTC2220-1 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2299 LT5512 LT5514 LT5522 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps Wideband ADC High Speed Differential Op Amp 16-Bit, 10Msps ADC 16-Bit, 25Msps ADC 16-Bit, 40Msps ADC 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 16-Bit, 105Msps ADC 16-Bit, 130Msps ADC 16-Bit, 160Msps ADC 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 12-Bit, 170Msps ADC 12-Bit, 185Msps ADC 14-Bit, 65Msps ADC 10-Bit, 105Msps ADC 10-Bit, 125Msps ADC 12-Bit, 105Msps ADC 12-Bit, 125Msps ADC 14-Bit, 105Msps ADC 14-Bit, 125Msps ADC Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 600MHz BW, 75dBc Distortion at 70MHz 150mW, 81.6dB SNR, 100dB SFDR 230mW, 81.6dB SNR, 100dB SFDR 470mW, 79dB SNR, 100dB SFDR 530mW, 79dB SNR, 100dB SFDR 725mW, 77.9dB SNR, 100dB SFDR 900mW, 77.9dB SNR, 100dB SFDR 1250mW, 77.7dB SNR, 100dB SFDR 1450mW, 77.1dB SNR, 100dB SFDR 700mW, 81.5dB SNR, 100dB SFDR 970mW, 81.3dB SNR, 100dB SFDR 890mW, 67.5dB SNR, 9mm × 9mm QFN Package 910mW, 67.5dB SNR, 9mm × 9mm QFN Package 230mW, 73dB SNR, 5mm × 5mm QFN Package 320mW, 61.6dB SNR, 5mm × 5mm QFN Package 395mW, 61.6dB SNR, 5mm × 5mm QFN Package 320mW, 70.2dB SNR, 5mm × 5mm QFN Package 395mW, 70.2dB SNR, 5mm × 5mm QFN Package 320mW, 72.5dB SNR, 5mm × 5mm QFN Package 395mW, 72.4dB SNR, 5mm × 5mm QFN Package 445mW, 73dB SNR, 9mm × 9mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 2217f 32 Linear Technology Corporation (408) 432-1900 ● LT 0108 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007