LTC2220CUP-1

LTC2220-1 12-Bit,185Msps ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Sample Rate: 185Msps 67.5dB SNR up to 140MHz Input 80dB SFDR up to 170MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 910mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 185Msps: LTC2220-1 (12-Bit) 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) 64-Pin 9mm × 9mm QFN Package The LTC®2220-1 is a 185Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2220-1 is perfect for demanding communications applications with AC performance that includes 67.5dB SNR and 80dB spurious free dynamic range for signals up to 170MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ± 0.7LSB INL (typ), ± 0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO 3.3V REFH REFL FLEXIBLE REFERENCE VDD 0.5V TO 3.6V OVDD 100 90 4th OR HIGHER SFDR (dBFS) + ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS D11 • • • D0 80 70 2nd OR 3rd 60 50 40 CMOS OR LVDS OGND CLOCK/DUTY CYCLE CONTROL 22201 TA01 ENCODE INPUT U SFDR vs Input Frequency 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22201 TA01b 2220_1fa U U 1 LTC2220-1 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2220-1C ............................................ 0°C to 70°C LTC2220-1I .........................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AIN+ 1 AIN+ 2 AIN– 3 AIN– 4 REFHA 5 REFHA 6 REFLB 7 REFLB 8 REFHB 9 REFHB 10 REFLA 11 REFLA 12 VDD 13 VDD 14 VDD 15 GND 16 64 GND 63 VDD 62 VDD 61 GND 60 VCM 59 SENSE 58 MODE 57 LVDS 56 OF +/OFA 55 OF –/DA11 54 D11+/DA10 53 D11–/DA9 52 D10+/DA8 51 D10 –/DA7 50 OGND 49 OVDD 65 48 D9+/DA6 47 D9–/DA5 46 D8+/DA4 45 D8–/DA3 44 D7 +/DA2 43 D7 –/DA1 42 OVDD 41 OGND 40 D6+/DA0 39 D6–/CLOCKOUTA 38 D5+/CLOCKOUTB 37 D5–/OFB 36 CLOCKOUT +/DB11 35 CLOCKOUT –/DB10 34 OVDD 33 OGND TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2220CUP-1 LTC2220IUP-1 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V Differential Analog Input (Note 5) Differential Analog Input Single-Ended Analog Input (Note 5) Single-Ended Analog Input (Note 6) External Reference ● ● CONDITIONS ● ● ● ENC + 17 ENC – 18 SHDN 19 OE 20 DO–/DB0 21 + DO /DB1 22 D1–/DB2 23 D1+/DB3 24 OGND 25 OVDD 26 D2–/DB4 27 +/DB5 28 D2 D3–/DB6 29 D3+/DB7 30 D4–/DB8 31 D4+/DB9 32 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN UP PART MARKING* LTC2220UP-1 MIN 12 –1.8 –1 TYP ±0.7 ±0.5 ±1.5 ±0.5 MAX 1.8 1.2 UNITS Bits LSB LSB LSB LSB –35 –2.5 ±3 ±0.5 ± 10 ± 30 ± 15 0.5 35 2.5 ppm/C ppm/C LSBRMS 2220_1fa 2 U mV %FS µV/C W U U WW W U LTC2220-1 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS tAP tJITTER CMRR PARAMETER Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN + AIN Analog Input Leakage Current SENSE Input Leakage MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Sample and Hold Acquisition Delay Time Sample and Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth Figure 8 Test Circuit + –)/2 A ALOG I PUT DY A IC ACCURACY SYMBOL SNR PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) ● Signal-to-Noise Ratio (Note 10) SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic (Note 11) SFDR Spurious Free Dynamic Range 4th Harmonic or Higher (Note 11) S/(N+D) Signal-to-Noise Plus Distortion Ratio (Note 12) IMD Intermodulation Distortion U WU U CONDITIONS 3.1V < VDD < 3.5V (Note 7) Differential Input (Note 7) Single Ended Input (Note 7) 0 < AIN+, AIN– < VDD 0V < SENSE < 1V ● ● ● ● ● MIN 1 0.5 –1 –1 TYP ±0.5 to ±1 1.6 1.6 MAX 1.9 2.1 1 1 UNITS V V V µA µA µA µA ns psRMS dB MHz 10 10 0 0.15 80 775 MIN TYP 62.7 67.7 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc 2220_1fa 65.2 62.7 67.6 62.4 67.5 61.8 66.1 80 80 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) fIN1 = 138MHz, fIN2 = 140MHz ● ● ● 69 80 80 80 80 74 73 85 85 74 85 85 84 84 83 83 62.7 67.5 64.2 62.7 67.3 81 3 LTC2220-1 I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 3.1V < VDD < 3.5V –1mA < IOUT < 1mA CONDITIONS IOUT = 0 MIN 1.570 TYP 1.600 ±25 3 4 MAX 1.630 UNITS V ppm/°C mV/V Ω DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VID VICM RIN CIN VIH VIL IIN CIN OVDD = 3.3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL VOD VOS High Level Output Voltage Low Level Output Voltage Differential Output Voltage Output Common Mode Voltage IO = –200µA IO = 1.6mA 100Ω Differential Load 100Ω Differential Load High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 3.3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance (Note 7) VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) Internally Set Externally Set (Note 7) CONDITIONS ENCODE INPUTS (ENC +, ENC –) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● ● LOGIC INPUTS (OE, SHDN) ● ● ● LOGIC OUTPUTS (CMOS MODE) 3 50 50 ● ● LOGIC OUTPUTS (LVDS MODE) ● ● 4 U U U U U TYP MAX UNITS V 0.2 1.1 1.6 1.6 6 3 2 0.8 –10 3 10 2.5 V V kΩ pF V V µA pF pF mA mA V V 0.4 V V V V V V 454 1.375 mV V 3.1 3.295 3.29 0.005 0.09 2.49 0.09 1.79 0.09 247 1.125 350 1.250 2220_1fa LTC2220-1 POWER REQUIRE E TS SYMBOL VDD PSHDN PNAP LVDS OUTPUT MODE OVDD IVDD IOVDD PDISS OVDD IVDD PDISS Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Power Dissipation PARAMETER Analog Supply Voltage Shutdown Power Nap Mode Power The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) CONDITIONS (Note 8) SHDN = High, OE = High, No CLK SHDN = High, OE = Low, No CLK (Note 8) ● ● ● ● ● CMOS OUTPUT MODE (Note 8) ● ● TI I G CHARACTERISTICS SYMBOL fS tL tH tAP tOE tD tC PARAMETER Sampling Frequency ENC Low Time (Note 7) ENC High Time (Note 7) Sample-and-Hold Aperture Delay Output Enable Delay ENC to DATA Delay ENC to CLOCKOUT Delay DATA to CLOCKOUT Skew Rise Time Fall Time Pipeline Latency CMOS OUTPUT MODE tD tC Pipeline Latency ENC to DATA Delay ENC to CLOCKOUT Delay DATA to CLOCKOUT Skew Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) (Note 7) (Note 7) (tC - tD) (Note 7) ● ● ● ● ● ● ● ● ● LVDS OUTPUT MODE 1.3 1.3 –0.6 2.2 2.2 0 0.5 0.5 5 (Note 7) (Note 7) (tC - tD) (Note 7) ● ● ● UW MIN 3.1 TYP 3.3 2 35 MAX 3.5 UNITS V mW mW 3 3.3 273 55 1080 3.6 300 70 1221 3.6 300 V mA mA mW V mA mW 0.5 3.3 273 910 UW MIN 1 2.5 2 2.5 2 TYP 2.7 2.7 2.7 2.7 0 5 MAX 185 500 500 500 500 10 3.5 3.5 0.6 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns 1.3 1.3 –0.6 2.1 2.1 0 5 5 5 and 6 3.5 3.5 0.6 ns ns ns Cycles Cycles Cycles 2220_1fa 5 LTC2220-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 185MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: VDD = 3.3V, fSAMPLE = 185MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower. Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes. Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower. TYPICAL PERFOR A CE CHARACTERISTICS LTC2220-1: INL, 2V Range 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.4 ERROR (LSB) ERROR (LSB) 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 1024 3072 2048 OUTPUT CODE 4096 2220 G01 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 1024 3072 2048 OUTPUT CODE 4096 2220 G02 COUNT 0.2 LTC2220-1: SNR vs Input Frequency, –1dB, 2V Range, LVDS Mode 70 69 68 67 66 65 64 63 62 61 60 0 100 400 500 INPUT FREQUENCY (MHz) 200 300 600 2220 G04 66 65 64 63 62 61 60 0 100 400 500 INPUT FREQUENCY (MHz) 200 300 600 2220 G05 SFDR (dBFS) SNR (dBFS) SNR (dBFS) 6 UW (TA = 25°C unless otherwise noted, Note 4) LTC2220-1: Shorted Input Noise Histogram 100000 93571 LTC2220-1: DNL, 2V Range 80000 0.2 60000 40000 24266 20000 229 –0 2056 2057 2058 CODE 2059 2060 2220 G03 12866 140 LTC2220-1: SNR vs Input Frequency, –1dB, 1V Range, LVDS Mode 70 69 68 67 100 90 80 70 60 50 40 LTC2220-1: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 2V Range, LVDS Mode 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2220 G06 2220_1fa LTC2220-1 TYPICAL PERFOR A CE CHARACTERISTICS LTC2220-1: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range, LVDS Mode 100 90 80 70 60 50 40 100 90 80 70 60 50 40 SFDR (dBFS) SFDR (dBFS) SFDR (dBFS) 200 300 0 100 400 500 600 INPUT FREQUENCY (MHz) 2220 G07 200 300 LTC2220-1: SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, –1dB, LVDS Mode 95 90 85 SFDR SFDR AND SNR (dBFS) SFDR AND SNR (dBFS) IVDD (mA) 80 75 70 65 60 55 50 0 40 120 160 SAMPLE RATE (Msps) 80 200 2220 G10 SNR LTC2220-1: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 60 50 40 LVDS OUTPUTS, 0VDD = 3.3V SFDR (dBc AND dBFS) IOVDD (mA) 30 20 CMOS OUTPUTS, 0VDD = 1.8V 10 0 0 40 UW LTC2220-1: SFDR (HD4+) vs Input Frequency, –1dB, 2V Range, LVDS Mode 100 90 80 70 60 50 40 LTC2220-1: SFDR (HD4+) vs Input Frequency, –1dB, 1V Range, LVDS Mode 0 100 400 500 600 INPUT FREQUENCY (MHz) 2220 G08 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2220 G09 LTC2220-1: SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB, LVDS Mode 95 90 85 80 75 70 65 60 55 50 0 40 120 160 SAMPLE RATE (Msps) 80 200 2220 G11 LTC2220-1: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 290 280 270 260 250 240 230 220 210 0 40 80 120 160 SAMPLE RATE (Msps) 200 2220 G12 SFDR 2V RANGE 1V RANGE SNR LTC2220-1: SFDR vs Input Level, f IN = 70MHz, 2V Range 100 90 80 70 60 50 40 30 20 10 dBFS dBc 120 160 SAMPLE RATE (Msps) 80 200 2220 G13 0 –60 –50 –30 –20 –40 INPUT LEVEL (dBFS) –10 0 2220_1fa 2220 G14 7 LTC2220-1 TYPICAL PERFOR A CE CHARACTERISTICS LTC2220-1: 8192 Point FFT, f IN = 5MHz, –1dB, 2V Range, LVDS Mode 0 –20 AMPLITUDE (dB) AMPLITUDE (dB) –40 –60 –80 0 –20 –40 –60 –80 AMPLITUDE (dB) –100 –120 0 10 20 30 40 50 60 70 80 90 2220 G15 FREQUENCY (MHz) LTC2220-1: 8192 Point FFT, f IN = 250MHz, –1dB, 2V Range, LVDS Mode 0 –20 AMPLITUDE (dB) –40 –60 –80 AMPLITUDE (dB) –100 –120 0 10 20 30 40 50 60 70 80 90 2220 G18 FREQUENCY (MHz) 8 UW LTC2220-1: 8192 Point FFT, f IN = 70MHz, –1dB, 2V Range, LVDS Mode 0 –20 –40 –60 –80 LTC2220-1: 8192 Point FFT, f IN = 140MHz, –1dB, 2V Range, LVDS Mode –100 –120 0 10 20 30 40 50 60 70 80 90 2220 G16 FREQUENCY (MHz) –100 –120 0 10 20 30 40 50 60 70 80 90 2220 G17 FREQUENCY (MHz) LTC2220-1: 8192 Point FFT, f IN = 500MHz, –6dB, 1V Range, LVDS Mode 0 –20 –40 –60 –80 –100 –120 0 10 20 30 40 50 60 70 80 90 2220 G19 FREQUENCY (MHz) 2220_1fa LTC2220-1 PI FU CTIO S (CMOS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN – (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC – (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high impedance in full rate CMOS mode. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under flow has occurred. At high impedance in full rate CMOS mode. CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode. CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA. DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA11 is the MSB. OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 2220_1fa U U U 9 LTC2220-1 PI FU CTIO S (LVDS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN– (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+. OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 10 U U U 2220_1fa LTC2220-1 FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE AIN– SECOND PIPELINED ADC STAGE VCM 2.2µF 1.6V REFERENCE RANGE SELECT SHIFT REGISTER AND CORRECTION SENSE REF BUF REFH DIFF REF AMP REFLB REFHA 2.2µF 0.1µF 1µF Figure 1. Functional Block Diagram W VDD THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND REFL INTERNAL CLOCK SIGNALS OVDD DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • U U + OF – + D11 – + – + – D0 CLKOUT REFLA REFHB 0.1µF 1µ F ENC+ ENC– M0DE LVDS SHDN OE 22201 F01 OGND 2220_1fa 11 LTC2220-1 TI I G DIAGRA S LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD D0-D11, OF tC N–5 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 CLOCKOUT – CLOCKOUT + ANALOG INPUT ENC – ENC + tD DA0-DA11, OFA tC CLOCKOUTB CLOCKOUTA N–5 N–4 N–3 N–2 N–1 DB0-DB11, OFB 12 W UW 22201 TD01 Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP N tH tL N+1 N+2 N+3 N+4 HIGH IMPEDANCE 22201 TD02 2220_1fa LTC2220-1 TI I G DIAGRA S Demultiplexed CMOS Outputs with Interleaved Update All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD DA0-DA11, OFA N–5 tD DB0-DB11, OFB N–6 tC CLOCKOUTB CLOCKOUTA 22201 TD03 ANALOG INPUT ENC – ENC + tD DA0-DA11, OFA tD DB0-DB11, OFB tC CLOCKOUTB CLOCKOUTA 22201 TD04 W UW N+2 N+3 N+1 N+4 N–3 N–1 N–4 tC N–2 Demultiplexed CMOS Outputs with Simultaneous Update All Outputs Are Single-Ended and Have CMOS Levels tAP N tH tL N+1 N+2 N+3 N+4 N–6 N–4 N–2 N–5 N–3 N–1 2220_1fa 13 LTC2220-1 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V2 + V3 + V4 + . . . Vn )/V1) 2 2 2 2 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either 14 U input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2220-1 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The LTC2220-1 has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. 2220_1fa W U U LTC2220-1 APPLICATIO S I FOR ATIO Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2220-1 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. U When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. LTC2220-1 VDD 15Ω CPARASITIC 1pF CSAMPLE 1.6pF CPARASITIC 1pF VDD CSAMPLE 1.6pF AIN+ VDD 15Ω AIN– 1.6V 6k ENC+ ENC– 6k 1.6V 22201 F02 W UU Figure 2. Equivalent Input Circuit Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.6V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for 2220_1fa 15 LTC2220-1 APPLICATIO S I FOR ATIO the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2220-1 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sampleand-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2220-1 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. 16 U Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω 25Ω 0.1µF AIN+ AIN+ 12pF 25Ω AIN– AIN– 22201 F03 W UU LTC2220-1 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 3. Single-Ended to Differential Conversion Using a Transformer VCM HIGH SPEED DIFFERENTIAL AMPLIFIER 25Ω ANALOG INPUT 2.2µF AIN+ AIN+ 12pF AIN– AIN– AMPLIFIER = LTC6600-20, LT1993, ETC. 3pF 22201 F04 LTC2220-1 + CM + – 3pF – 25Ω Figure 4. Differential Drive with an Amplifier VCM 1k 1k 25Ω 2.2µF AIN+ AIN+ 12pF 25Ω 0.1µF AIN– AIN– 22201 F05 0.1µF ANALOG INPUT LTC2220-1 Figure 5. Single-Ended Drive 2220_1fa LTC2220-1 APPLICATIO S I FOR ATIO The AIN+ and AIN– inputs each have two pins to reduce package inductance. The two AIN+ and the two AIN– pins should be shorted together. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 12Ω 25Ω 12Ω 0.1µF AIN+ AIN+ 8pF AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22201 F06 LTC2220-1 Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22201 F07 AIN+ 25Ω 0.1µF AIN+ LTC2220-1 Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 4.7nH 25Ω 4.7nH 0.1µF AIN+ AIN+ 2pF AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22201 F08 LTC2220-1 Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz U Reference Operation Figure 9 shows the LTC2220-1 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (± 0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. The 1.6V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.6V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. LTC2220-1 1.6V VCM 2.2µF 4Ω 1.6V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE REFLB 0.1µF REFHA BUFFER INTERNAL ADC HIGH REFERENCE 0.5V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µF 2.2µF 1µF DIFF AMP REFLA 0.1µF REFHB INTERNAL ADC LOW REFERENCE 22201 F09 W UU Figure 9. Equivalent Reference Circuit 2220_1fa 17 LTC2220-1 APPLICATIO S I FOR ATIO Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. 1.6V VCM 2.2µF SENSE 1µF LTC2220-1 12k 0.8V 12k 22201 F10 Figure 10. 1.6V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC2220-1 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 18 U 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. LTC2220-1 VDD TO INTERNAL ADC CIRCUITS 1.6V BIAS 6k ENC+ 0.1µF CLOCK INPUT 50Ω 1:4 VDD 1.6V BIAS 6k ENC– VDD 22201 F11 W UU Figure 11. Transformer Driven ENC+/ENC– Maximum and Minimum Encode Rates The maximum encode rate for the LTC2220-1 is 185Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 2.5ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal 2220_1fa LTC2220-1 APPLICATIO S I FOR ATIO duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2220-1 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2220-1 is 1Msps. VTHRESHOLD = 1.6V ENC+ 1.6V ENC– 0.1µF LTC2220-1 22201 F12a Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 130Ω Q0 130Ω ENC + D0 Q0 83Ω ENC– 83Ω LTC2220-1 22201 F12b Figure 12b. ENC Drive Using a CMOS to PECL Translator DIGITAL OUTPUTS Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V –0.000488V –0.000976V –0.999512V –1.000000V 100MHz, REPLACE T1 WITH A ETC1-1-13 – + C34 4.7µF R28 1k 2/3VDD C4 0.1µF R2 4.99k 1% R3 4.99k 1% SCL VSS VCC_IN MODE C32 0.1µF VSS SCL SDA VCC_IN R6 4.7k VCC VCC ENABLE EDGE-CON-100 VDD R29 1k 1/3VDD R30 1k GND C39 0.1µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND EN/12 RIN1– RIN1+ RIN2+ RIN2– RIN3– RIN3+ RIN4+ RIN4– VCC EN RIN5– RIN5+ RIN6+ RIN6– RIN7– RIN7+ RIN8+ RIN8– EN/34 GND VBB VCC VCC EN/78 DOUT1– DOUT1+ DOUT2+ DOUT2– DOUT3– DOUT3+ DOUT4+ DOUT4– GND GND DOUT5– DOUT5+ DOUT6+ DOUT6– DOUT7– DOUT7+ DOUT8+ DOUT8– EN/56 VCC VCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VDD 3.3V C3 4.7µF JP4 1 A0 2 A1 3 A2 4 A3 8 VCC 7 WP 6 SCL 5 SDA R4 4.99k 1% SDA L1 VCC MURATA BLM18BB470SN C5 4.7µF CLK R8 100Ω C25 33pF CLK C20 0.1µF OPT VCC VCC 3.3V J9 C27 0.1µF C26 0.1µF ANALOG INPUT T1* ETC1-1T R9 24.9Ω T2 ETC1-1T R10 24.9Ω C1 0.1µF C2 0.1µF C5 0.1µF C6 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C12 0.1µF C36 4.7µF C23 0.1µF VCM LTC2220-1 23 R27 50Ω C22 0.1µF U APPLICATIO S I FOR ATIO W UU 2220_1fa LTC2220-1 APPLICATIO S I FOR ATIO U Silkscreen Top 2220_1fa 24 W UU LTC2220-1 APPLICATIO S I FOR ATIO U Layer 1 Component Side Layer 2 GND Plane 2220_1fa W UU 25 LTC2220-1 APPLICATIO S I FOR ATIO U Layer 3 Power Plane Layer 4 Bottom Side 2220_1fa 26 W UU LTC2220-1 PACKAGE DESCRIPTIO 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP PIN 1 TOP MARK (SEE NOTE 5) 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ± 0.05 7.15 ± 0.05 8.10 ± 0.05 9.50 ± 0.05 (4 SIDES) PACKAGE OUTLINE 63 64 0.40 ± 0.10 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.200 REF 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD (UP64) QFN 1003 2220_1fa 27 LTC2220-1 RELATED PARTS PART NUMBER LTC1748 LTC1750 LT1993-2 LT®1994 LTC2202 LTC2208 LTC2220 LTC2220-1 LTC2221 LTC2224 LTC2230 LTC2231 LTC2255 LTC2284 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit, 80Msps, 5V ADC 14-Bit, 80Msps, 5V Wideband ADC High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 10-Bit, 170Msps, 3.3V ADC, LVDS Outputs 10-Bit, 135Msps, 3.3V ADC, LVDS Outputs 14-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator COMMENTS 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 90dB SFDR 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: –94dBc at 1MHz 150mW, 81.6dB SNR, 100dB SFDR, 48-pin QFN 1250mW, 78dB SNR, 100dB SFDR, 64-pin QFN 890mW, 67.7dB SNR, 84dB SFDR, 64-pin QFN 910mW, 67.7dB SNR, 80dB SFDR, 64-pin QFN 660mW, 67.8dB SNR, 84dB SFDR, 64-pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-pin QFN 890mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN 660mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN 395mW, 72.5dB SNR, 88dB SFDR, 32-pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50Ω Single Ended RF and LO Ports 2220_1fa 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0106 REV A • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005