LTC2229

LTC2229 12-Bit, 80Msps Low Power 3V ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Sample Rate: 80Msps Single 3V Supply (2.7V to 3.4V) Low Power: 211mW 70.6dB SNR at 70MHz Input 90dB SFDR at 70MHz Input No Missing Codes Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm × 5mm) QFN Package The LTC®2229 is a 12-bit 80Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2229 is perfect for demanding imaging and communications applications with AC performance that includes 70.6dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Ultrasound Spectral Analysis Portable Instrumentation TYPICAL APPLICATIO REFH REFL FLEXIBLE REFERENCE OVDD SNR (dBFS) + ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS D11 • • • D0 OGND CLOCK/DUTY CYCLE CONTROL 2229 TA01 CLK 2229fa U SNR vs Input Frequency, –1dB, 2V Range 75 74 73 72 71 70 69 68 67 66 65 0 100 50 150 INPUT FREQUENCY (MHz) 200 2229 G09 U U 1 LTC2229 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW SENSE MODE VCM D11 D10 VDD D9 OF OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2229C ............................................... 0°C to 70°C LTC2229I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C 32 31 30 29 28 27 26 25 AIN+ 1 AIN– 2 REFH 3 REFH 4 REFL 5 REFL 6 VDD 7 GND 8 9 10 11 12 13 14 15 16 SHDN OE D0 D1 NC CLK NC D2 24 D8 23 D7 22 D6 33 21 OVDD 20 OGND 19 D5 18 D4 17 D3 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2229CUH LTC2229IUH QFN PART MARKING* 2229 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS ● MIN 12 –1.1 –0.8 –12 –2.5 ● ● ● ● TYP ±0.4 ±0.2 ±2 ±0.5 ±10 ±30 ±5 0.3 MAX 1.1 0.8 12 2.5 UNITS Bits LSB LSB mV %FS µV/°C ppm/°C ppm/°C LSBRMS Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference SENSE = 1V 2229fa 2 U W U U WW W U LTC2229 A ALOG I PUT SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ + AIN–)/2 Analog Input Leakage Current SENSE Input Leakage MODE Pin Leakage Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 2.7V < VDD < 3.4V (Note 7) Differential Input (Note 7) Single Ended Input (Note 7) 0V < AIN+, AIN– < VDD 0V < SENSE < 1V ● ● ● ● ● ● DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input 40MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 40MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 40MHz Input 70MHz Input 140MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 40MHz Input 70MHz Input 140MHz Input IMD Intermodulation Distortion Full Power Bandwidth fIN1 = 28.2MHz, fIN2 = 26.8MHz Figure 8 Test Circuit ● ● ● ● I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 U U WU U U MIN 1 0.5 –1 –3 –3 TYP ±0.5 to ±1 1.5 1.5 MAX 1.9 2 1 3 3 UNITS V V V µA µA µA ns psRMS dB 0 0.2 80 MIN 68.9 TYP 70.6 70.6 70.6 70.3 90 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB MHz 74 90 90 85 95 80 95 95 90 70.6 68.5 70.5 70.5 70 90 575 U (Note 4) MIN 1.475 TYP 1.500 ±25 3 4 MAX 1.525 UNITS V ppm/°C mV/V Ω 2.7V < VDD < 3.4V –1mA < IOUT < 1mA 2229fa 3 LTC2229 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA 1.79 0.09 V V High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA 2.49 0.09 V V Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V VIN = 0V to VDD (Note 7) ● ● ● LOGIC INPUTS (CLK, OE, SHDN) 2 0.8 –10 3 10 V V µA pF POWER REQUIRE E TS SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power Nap Mode Power The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) CONDITIONS (Note 9) (Note 9) ● ● ● ● 4 UW U U MIN TYP MAX UNITS 3 50 50 2.7 2.995 2.99 0.005 0.09 0.4 pF mA mA V V V V MIN 2.7 0.5 TYP 3 3 70.3 211 2 15 MAX 3.4 3.6 82 246 UNITS V V mA mW mW mW SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK 2229fa LTC2229 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fs tL tH tAP tD PARAMETER Sampling Frequency CLK Low Time CLK High Time Sample-and-Hold Aperture Delay CLK to DATA Delay Data Access Time After OE↓ BUS Relinquish Time Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential drive, unless otherwise noted. CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7) ● ● ● TI I G CHARACTERISTICS TYPICAL PERFOR A CE CHARACTERISTICS Typical INL, 2V Range 1.0 0.8 0.6 1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE 2229 G01 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 AMPLITUDE (dB) 0.4 3072 UW UW CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● ● ● ● MIN 1 5.9 5 5.9 5 1.4 TYP 6.25 6.25 6.25 6.25 0 2.7 4.3 3.3 5 MAX 80 500 500 500 500 5.4 10 8.5 UNITS MHz ns ns ns ns ns ns ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential drive. Note 9: Recommended operating conditions. Typical DNL, 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 1024 2048 CODE 2229 G02 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range 0.4 4096 3072 4096 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 2229 G03 2229fa 5 LTC2229 TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 AMPLITUDE (dB) –40 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range 0 –10 –20 –30 120000 100000 140000 AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 SNR (dBFS) COUNT 0 5 10 15 20 25 30 FREQUENCY (MHz) SFDR vs Input Frequency, –1dB, 2V Range 100 95 90 90 SFDR (dBFS) SNR AND SFDR (dBFS) SNR AND SFDR (dBFS) 85 80 75 70 65 0 50 150 INPUT FREQUENCY (MHz) 100 200 2229 G10 6 UW 2229 G04 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range –40 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 2229 G05 2229 G06 Grounded Input Histogram 75 SNR vs Input Frequency, –1dB, 2V Range 74 73 72 71 70 69 68 67 116838 80000 60000 40000 20000 5712 0 8522 2051 CODE 2052 2229 G08 66 65 0 100 50 150 INPUT FREQUENCY (MHz) 200 2229 G09 35 40 2050 2229 G07 SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 SFDR 95 SNR and SFDR vs Clock Duty Cycle SFDR: DCS ON 90 SFDR: DCS OFF 85 80 75 SNR: DCS ON 70 65 SNR: DCS OFF 30 35 40 45 50 55 60 CLOCK DUTY CYCLE (%) 65 70 80 SNR 70 60 50 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps) 2229 G11 2229 G12 2229fa LTC2229 TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Level, fIN = 70MHz, 2V Range 80 dBFS 70 60 50 40 30 20 10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 dBc 120 110 100 90 80 70 60 50 40 30 20 10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 dBc 100dBc SFDR REFERENCE LINE dBFS 2249 G13 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 85 80 IOVDD (mA) IVDD (mA) 75 2V RANGE 70 1V RANGE 65 60 55 50 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2229 G15 UW SFDR vs Input Level, fIN = 70MHz, 2V Range 2229 G14 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2229 G16 2229fa 7 LTC2229 PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. NC (Pins 12, 13): Do Not Connect These Pins. D0–D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D11 is the MSB. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 8 U U U 2229fa LTC2229 FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE AIN– SECOND PIPELINED ADC STAGE VCM 2.2µF 1.5V REFERENCE RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFH 1µ F Figure 1. Functional Block Diagram W THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION REFL INTERNAL CLOCK SIGNALS OVDD OF CLOCK/DUTY CYCLE CONTROL D11 CONTROL LOGIC OUTPUT DRIVERS • • • D0 0.1µF 2.2µF 1µF REFL CLK MODE SHDN OE 2229 F01 U U OGND 2229fa 9 LTC2229 TI I G DIAGRA ANALOG INPUT CLK tD D0-D11, OF N–5 N–4 N–3 N–2 N–1 N 2229 TD01 10 W tAP N tH tL N+1 N+2 N+3 N+4 N+5 2229fa UW LTC2229 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. U If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) 2229fa W UU 11 LTC2229 APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2229 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2229 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. 12 U SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2229 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. LTC2229 VDD 15Ω CPARASITIC 1pF CSAMPLE 4pF CPARASITIC 1pF VDD CLK CSAMPLE 4pF AIN+ VDD 15Ω AIN– 2229 F02 W UU Figure 2. Equivalent Input Circuit 2229fa LTC2229 APPLICATIO S I FOR ATIO Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2229 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. U Input Drive Circuits Figure 3 shows the LTC2229 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 25Ω 0.1µF 12pF AIN– 2229 F03 W U U AIN+ LTC2229 Figure 3. Single-Ended to Differential Conversion Using a Transformer VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT 2.2µF AIN+ LTC2229 + CM + 12pF – – 25Ω AIN– 2229 F04 Figure 4. Differential Drive with an Amplifier 2229fa 13 LTC2229 APPLICATIO S I FOR ATIO Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In VCM 1k 1k 25Ω 2.2µF AIN+ LTC2229 12pF 25Ω 0.1µF AIN– 2229 F05 0.1µF ANALOG INPUT Figure 5. Single-Ended Drive LTC2229 VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 12Ω 25Ω 12Ω 0.1µF 8pF AIN– 2229 F06 AIN+ LTC2229 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2229 F07 AIN+ 25Ω 0.1µF LTC2229 Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz 14 U Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2229 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (± 0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 6.8nH AIN– 2229 F08 W UU 6.8nH 25Ω 0.1µF AIN+ LTC2229 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz 1.5V VCM 2.2µF 4Ω 1.5V BANDGAP REFERENCE 1V 0.5V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µ F RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 2.2µF 1µ F 0.1µF DIFF AMP REFL INTERNAL ADC LOW REFERENCE 2229 F09 Figure 9. Equivalent Reference Circuit 2229fa LTC2229 APPLICATIO S I FOR ATIO The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. 1.5V VCM 2.2µF SENSE 1µF LTC2229 12k 0.75V 12k 2229 F10 Figure 10. 1.5V Range ADC U Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 4dB. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11). The noise performance of the LTC2229 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. 4.7µF FERRITE BEAD 0.1µF SINUSOIDAL CLOCK INPUT 0.1µF 1k CLK 50Ω 1k NC7SVU04 LTC2229 CLEAN SUPPLY 2229 F11 W UU Figure 11. Sinusoidal Single-Ended CLK Drive 2229fa 15 LTC2229 APPLICATIO S I FOR ATIO U Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2229 is 80Msps. For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 5.9ns for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2229 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2229 is 1Msps. ETC1-1T 5pF-30pF CLK LTC2229 DIFFERENTIAL CLOCK INPUT 2229 F13 Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. 4.7µF FERRITE BEAD 0.1µF CLEAN SUPPLY CLK 100Ω IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter 16 W UU LTC2229 2229 F12 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer 2229fa LTC2229 APPLICATIO S I FOR ATIO DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V –0.000488V –0.000976V –0.999512V –1.000000V