LTC2230IUP

Electrical Specifications Subject to Change LTC2230/LTC2231 10-Bit,170Msps/ 135Msps ADCs FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Sample Rate: 170Msps/135 Msps 61dB SNR up to 140MHz Input 75dB SFDR up to 200MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 890mW/660mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) 64-Pin 9mm x 9mmQFN Package The LTC®2230 and LTC2231 are 170Msps/135Msps, sampling 10-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2230/ LTC2231 are perfect for demanding communications applications with AC performance that includes 61dB SNR and 75dB spurious free dynamic range for signals up to 200MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ± 0.2LSB INL (typ), ± 0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.12LSBRMS. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V. The ENC+ and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO REFH REFL FLEXIBLE REFERENCE 3.3V VDD 0.5V TO 3.3V OVDD SFDR (dBFS) + ANALOG INPUT INPUT S/H – 10-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS D9 • • • D0 CMOS OR LVDS OGND CLOCK/DUTY CYCLE CONTROL 22301 TA01 ENCODE INPUT 22301p U SFDR vs Input Frequency 90 85 80 75 70 65 60 55 50 45 40 0 100 300 500 200 400 INPUT FREQUENCY (MHz) 600 2nd OR 3rd 4th OR HIGHER 2230 TA01b U U 1 LTC2230/LTC2231 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW 64 GND 63 VDD 62 VDD 61 GND 60 VCM 59 SENSE 58 MODE 57 LVDS 56 OF +/OFA 55 OF –/DA9 54 D9+/DA8 53 D9–/DA7 52 D8+/DA6 51 D8–/DA5 50 OGND 49 OVDD OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2230C, LTC2231C ............................. 0°C to 70°C LTC2230I, LTC2231I ...........................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AIN+ 1 AIN+ 2 AIN– 3 AIN– 4 REFHA 5 REFHA 6 REFLB 7 REFLB 8 REFHB 9 REFHB 10 REFLA 11 REFLA 12 VDD 13 VDD 14 VDD 15 GND 16 65 48 D7+/DA4 47 D7–/DA3 46 D6+/DA2 45 D6–/DA1 44 D5+/DA0 43 D5–/DNC 42 OVDD 41 OGND 40 D4+/DNC 39 D4–/CLOCKOUTA 38 D3+/CLOCKOUTB 37 D3–/OFB 36 CLOCKOUT +/DB9 35 CLOCKOUT –/DB8 34 OVDD 33 OGND ORDER PART NUMBER LTC2230CUP LTC2230IUP LTC2231CUP LTC2231IUP Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V External Reference Differential Analog Input Differential Analog Input Single-Ended Analog Input Single-Ended Analog Input ● ● CONDITIONS ● ● ● ENC + 17 ENC – 18 SHDN 19 OE 20 DNC 21 DNC 22 DNC/DB0 23 DNC/DB1 24 OGND 25 OVDD 26 D0–/DB2 27 D0+/DB3 28 D1–/DB4 29 D1+/DB5 30 D2–/DB6 31 D2+/DB7 32 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 65), MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 20°C/W UP PART MARKING 2230 2230 2231 2231 MIN 10 –0.8 –0.6 TYP ±0.2 ±0.1 ±0.5 ±0.1 MAX 0.8 0.6 UNITS Bits LSB LSB LSB LSB –20 –3 ±3 ±0.5 ±10 ±30 ±15 0.12 20 3 %FS µV/C ppm/C ppm/C LSBRMS 22301p 2 U mV W U U WW W U LTC2230/LTC2231 A ALOG I PUT SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS tAP tJITTER CMRR The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) PARAMETER Analog Input Range (AIN+ – AIN–) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Sample and Hold Acquisition Delay Time Sample and Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth Figure 8 Test Circuit CONDITIONS 3.1V < VDD < 3.5V Differential Input 0 < AIN+, AIN– < VDD 0V < SENSE < 1V ● ● ● ● DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio (Note 10) SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic (Note 11) SFDR Spurious Free Dynamic Range 4th Harmonic or Higher (Note 11) S/(N+D) Signal-to-Noise Plus Distortion Ratio (Note 12) IMD Intermodulation Distortion U WU U MIN 1 –1 –1 TYP ±0.5 to ±1 1.6 MAX 1.9 1 1 UNITS V V µA µA µA µA ns psRMS dB MHz 10 10 0 0.15 80 775 TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) fIN1 = 138MHz, fIN2 = 140MHz 60 75 70 60 MIN LTC2230 TYP 59.5 61.2 59.5 61.1 59.4 61.0 59.0 60.6 80 78 80 78 78 78 75 74 86 86 86 86 86 86 85 85 59.5 61.2 59.5 61.1 81 60 75 70 60 MAX MIN LTC2231 TYP 59.5 61.2 59.5 61.1 59.4 61.0 59.0 60.6 80 78 80 78 78 78 78 78 86 86 86 86 86 86 85 85 59.5 61.2 59.5 61.1 81 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB db dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc 22301p 3 LTC2230/LTC2231 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 3.1V < VDD < 3.5V –1mA < IOUT < 1mA CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VID VICM RIN CIN VIH VIL IIN CIN OVDD = 3.3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL VOD VOS High Level Output Voltage Low Level Output Voltage Differential Output Voltage Output Common Mode Voltage IO = –200µA IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 3.3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance (Note 7) VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) CONDITIONS ENCODE INPUTS (ENC +, ENC –) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● LOGIC INPUTS (OE, SHDN) ● ● ● LOGIC OUTPUTS (CMOS MODE) 3 50 50 ● ● LOGIC OUTPUTS (LVDS MODE) 100Ω Differential Load 100Ω Differential Load ● ● 4 U U U U U (Note 4) MIN 1.575 TYP 1.600 ±25 3 4 MAX 1.625 UNITS V ppm/C mV/V Ω TYP MAX UNITS V 0.2 1.1 1.6 1.6 6 3 2 0.8 –10 3 10 2.5 Internally Set Externally Set (Note 7) ● V V kΩ pF V V µA pF pF mA mA V V 0.4 V V V V V V 454 1.375 mV V 3.1 3.295 3.29 0.005 0.09 2.49 0.09 1.79 0.09 247 1.125 350 1.250 22301p LTC2230/LTC2231 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL VDD PSHDN PNAP OVDD IVDD IOVDD PDISS OVDD IVDD PDISS PARAMETER Analog Supply Voltage Shutdown Power Nap Mode Power Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Power Dissipation SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK ● ● ● ● ● ● POWER REQUIRE E TS LVDS OUTPUT MODE 3 3.3 264 55 1050 0.5 3.3 264 890 3.6 290 61 1160 3.6 290 0.5 3 3.3 196 55 828 3.3 196 660 3.6 216 61 915 3.6 216 V mA mA mW V mA mW CMOS OUTPUT MODE The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fS tL tH tAP tOE tD tC PARAMETER Sampling Frequency ENC Low Time ENC High Time Sample-and-Hold Aperture Delay Output Enable Delay ENC to DATA Delay ENC to CLOCKOUT Delay DATA to CLOCKOUT Skew Rise Time Fall Time Pipeline Latency CMOS OUTPUT MODE tD tC ENC to DATA Delay ENC to CLOCKOUT Delay DATA to CLOCKOUT Skew Pipeline Latency Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous (Note 7) (Note 7) (tC - tD) (Note 7) ● ● ● TI I G CHARACTERISTICS LVDS OUTPUT MODE (Note 7) (Note 7) (tC - tD) (Note 7) ● ● ● UW CONDITIONS ● MIN 3.1 LTC2230 TYP MAX 3.3 2 35 3.5 MIN 3.1 LTC2231 TYP MAX 3.3 2 35 3.5 UNITS V mW mW UW CONDITIONS ● MIN 1 2.8 2 2.8 2 ● ● ● ● ● LTC2230 TYP MAX 170 2.94 2.94 2.94 2.94 0 5 500 500 500 500 10 3.5 3.5 0.6 MIN 1 3.5 2 3.5 2 LTC2231 TYP MAX 135 3.7 3.7 3.7 3.7 0 5 10 3.5 3.5 0.6 500 500 500 500 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns Cycles Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) 1.3 1.3 –0.6 2.2 2.2 0 0.5 0.5 5 1.3 1.3 –0.6 2.2 2.2 0 0.5 0.5 5 1.3 1.3 –0.6 2.1 2.1 0 5 5 5 and 6 3.5 3.5 0.6 1.3 1.3 –0.6 2.1 2.1 0 5 5 5 and 6 3.5 3.5 0.6 ns ns ns Cycles Cycles Cycles 22301p 5 LTC2230/LTC2231 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 170MHz (LTC2230) or 135MHz (LTC2231), LVDS outputs differential, ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 and 11 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: VDD = 3.3V, fSAMPLE = 170MHz (LTC2230) or 135MHz (LTC2231), differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.7dB to 0.9dB lower. Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes. Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.5dB to 0.9dB lower. TYPICAL PERFOR A CE CHARACTERISTICS LTC2230: INL, 2V Range 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.4 100000 ERROR (LSB) 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 256 512 OUTPUT CODE 768 1024 2230 G01 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 256 512 OUTPUT CODE 768 1024 2230 G02 COUNT 0.2 ERROR (LSB) LTC2230: SNR vs Input Frequency, –1dB, 2V Range 63 62 61 63 62 61 SFDR (dBFS) SNR (dBFS) SNR (dBFS) 60 59 58 57 0 100 300 400 500 200 INPUT FREQUENCY (MHz) 6 UW 600 2230 G03 LTC2230: DNL, 2V Range 140000 120000 LTC2230: Noise Histogram 131059 0.2 80000 60000 40000 20000 0 6 513 514 CODE 2230 G23 7 515 LTC2230: SNR vs Input Frequency, –1dB, 1V Range 90 85 80 75 70 65 60 55 50 45 57 0 100 300 400 500 200 INPUT FREQUENCY (MHz) 600 2230 G04 LTC2230: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 2V Range 60 59 58 40 0 100 300 500 200 400 INPUT FREQUENCY (MHz) 600 2230 G05 22301p LTC2230/LTC2231 TYPICAL PERFOR A CE CHARACTERISTICS LTC2230: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range 90 85 80 75 SFDR (dBFS) SFDR (dBFS) 70 65 60 55 50 45 40 0 100 300 500 200 400 600 INPUT FREQUENCY (MHz) 2230 G06 70 65 60 55 50 45 40 0 100 300 500 200 400 600 INPUT FREQUENCY (MHz) 2230 G07 SFDR (dBFS) LTC2230: SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB 90 85 SFDR AND SNR (dBFS) SFDR AND SNR (dBFS) 80 75 70 65 SFDR IVDD (mA) SNR 60 55 50 0 20 40 60 80 100 120 140 160 180 200 SAMPLE RATE (Msps) 2230 G09 LTC2230: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 60 50 40 IOVDD (mA) SFDR (dBc AND dBFS) 30 20 CMOS OUTPUTS, 0VDD = 1.8V 10 0 0 20 40 60 80 100 120 140 160 180 200 SAMPLE RATE (Msps) 2230 G12 UW LTC2230: SFDR (HD4+) vs Input Frequency, –1dB, 2V Range 90 85 80 75 90 85 80 75 70 65 60 55 50 45 40 LTC2230: SFDR (HD4+) vs Input Frequency, –1dB, 1V Range 0 100 300 500 200 400 600 INPUT FREQUENCY (MHz) 2230 G08 LTC2230: SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, –1dB 90 85 80 75 70 65 60 55 50 0 20 40 60 80 100 120 140 160 180 200 SAMPLE RATE (Msps) 2230 G10 SNR SFDR 290 280 270 260 LTC2230: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 2V RANGE 250 1V RANGE 240 230 220 210 0 20 40 60 80 100 120 140 160 180 200 SAMPLE RATE (Msps) 2230 G11 LTC2230: SFDR vs Input Level, f IN = 70MHz, 2V Range 100 90 80 70 60 50 40 30 20 10 0 –50 –40 –30 –10 –20 INPUT LEVEL (dBFS) 0 2230 G13 LVDS OUTPUTS, 0VDD = 3.3V dBFS dBc 22301p 7 LTC2230/LTC2231 TYPICAL PERFOR A CE CHARACTERISTICS LTC2230: 8192 Point FFT, f IN = 30MHz, –1dB, 2V Range 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –50 –60 –70 –80 –90 AMPLITUDE (dB) –40 –100 –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G14 LTC2230: 8192 Point FFT, f IN = 70MHz, –1dB, 1V Range 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –50 –60 –70 –80 –90 AMPLITUDE (dB) –40 –100 –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G17 LTC2230: 8192 Point FFT, f IN = 250MHz, –1dB, 2V Range 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –50 –60 –70 –80 –90 AMPLITUDE (dB) –40 –100 –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G20 8 UW LTC2230: 8192 Point FFT, f IN = 30MHz, –1dB, 1V Range 0 –10 –20 –30 –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G15 LTC2230: 8192 Point FFT, f IN = 70MHz, –1dB, 2V Range –100 –110 –120 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G16 LTC2230: 8192 Point FFT, f IN = 140MHz, –1dB, 2V Range 0 –10 –20 –30 –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G18 LTC2230: 8192 Point FFT, f IN = 140MHz, –1dB, 1V Range –100 –110 –120 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G19 LTC2230: 8192 Point FFT, f IN = 250MHz, –1dB, 1V Range 0 –10 –20 –30 –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G21 LTC2230: 8192 Point FFT, f IN = 500MHz, –6dB, 1V Range –100 –110 –120 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 2230 G22 22301p LTC2230/LTC2231 TYPICAL PERFOR A CE CHARACTERISTICS LTC2231: INL, 2V Range 1.0 0.8 0.6 0.4 ERROR (LSB) ERROR (LSB) 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 256 512 OUTPUT CODE 768 1024 2231 G01 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 256 512 OUTPUT CODE 768 1024 2231 G02 COUNT 0.2 LTC2231: SNR vs Input Frequency, –1dB, 2V Range 65 64 63 62 SNR (dBFS) 61 60 59 58 57 56 55 0 100 500 200 300 400 INPUT FREQUENCY (MHz) 600 61 60 59 58 57 56 55 0 100 500 200 300 400 INPUT FREQUENCY (MHz) 600 SFDR (dBFS) SNR (dBFS) LTC2231: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range 90 85 80 SFDR (dBFS) SFDR (dBFS) 70 65 60 55 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 70 65 60 55 50 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 SFDR (dBFS) 75 UW 2231 G03 2231 G06 LTC2231: DNL, 2V Range 1.0 0.8 0.6 0.4 0.2 100000 80000 60000 40000 20000 0 140000 120000 LTC2231: Noise Histogram 131064 5 513 514 CODE 3 515 2231 G23 LTC2231: SNR vs Input Frequency, –1dB, 1V Range 65 64 63 62 75 70 65 60 55 50 90 85 80 LTC2231: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 2V Range 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2231 G04 2231 G05 LTC2231: SFDR (HD4+) vs Input Frequency, –1dB, 2V Range 90 85 80 75 90 85 80 75 70 65 60 55 50 LTC2231: SFDR (HD4+) vs Input Frequency, –1dB, 1V Range 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2231 G07 2231 G08 22301p 9 LTC2230/LTC2231 TYPICAL PERFOR A CE CHARACTERISTICS LTC2231: SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB 85 80 SFDR 85 80 SFDR SFDR AND SNR (dBFS) 75 70 65 SNR 60 55 50 0 20 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 2231 G09 SFDR AND SNR (dBFS) 70 65 60 55 50 0 20 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 2231 G10 IVDD (mA) LTC2231: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 60 50 40 LVDS OUTPUTS, OVDD = 3.3V 100 90 80 SFDR (dBc AND dBFS) IOVDD (mA) 30 20 10 0 0 20 40 60 80 100 120 140 160 180 SAMPLE RATE (Msps) 2231 G12 10 UW LTC2231: SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, –1dB 220 210 200 LTC2231: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 75 2V RANGE 190 180 170 160 150 0 20 40 60 80 100 120 140 160 180 SAMPLE RATE (Msps) 2231 G11 1V RANGE SNR LTC2231: SFDR vs Input Level, f IN = 70MHz, 2V Range dBFS 70 60 50 40 30 20 10 0 –50 –40 –30 –10 –20 INPUT LEVEL (dBFS) 0 2231 G13 dBc CMOS OUTPUTS, OVDD = 1.8V 22301p LTC2230/LTC2231 TYPICAL PERFOR A CE CHARACTERISTICS LTC2231: 8192 Point FFT, f IN = 30MHz, –1dB, 2V Range 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G14 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G15 AMPLITUDE (dB) –40 LTC2231: 8192 Point FFT, f IN = 70MHz, –1dB, 1V Range 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G17 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G18 AMPLITUDE (dB) –40 LTC2231: 8192 Point FFT, f IN = 250MHz, –1dB, 2V Range 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G20 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G21 AMPLITUDE (dB) –40 UW LTC2231: 8192 Point FFT, f IN = 30MHz, –1dB, 1V Range 0 –10 –20 –30 –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 LTC2231: 8192 Point FFT, f IN = 70MHz, –1dB, 2V Range 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G16 LTC2231: 8192 Point FFT, f IN = 140MHz, –1dB, 2V Range 0 –10 –20 –30 –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 LTC2231: 8192 Point FFT, f IN = 140MHz, –1dB, 1V Range 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G19 LTC2231: 8192 Point FFT, f IN = 250MHz, –1dB, 1V Range 0 –10 –20 –30 –40 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 LTC2231: 8192 Point FFT, f IN = 500MHz, –6dB, 1V Range 0 5 10 15 20 25 30 35 40 45 50 55 60 65 FREQUENCY (MHz) 2231 G22 22301p 11 LTC2230/LTC2231 PI FU CTIO S (CMOS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN – (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. The input sample starts on the positive edge. ENC – (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DNC (Pins 21, 22, 40, 43): Do not connect these pins. DB0 - DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B bus. At high impedance in full rate CMOS mode. DB9 is MSB. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 37): Over/Under Flow Output for B bus. High when an over or under flow has occurred. At high impedance in full rate CMOS mode. CLKOUTB (Pin 38): Data Valid Output for B bus. In demux mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode. CLKOUTA (Pin 39): Data Valid Output for A bus. Latch A bus data on the falling edge of CLKOUTA. DA0 - DA9 (Pins 44 to 48, 51 to 55): Digital Outputs, A bus. DA9 is the MSB. OFA (Pin 56): Over/Under Flow Output for A bus. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects straight binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects straight binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. 12 U U U 22301p LTC2230/LTC2231 PI FU CTIO S SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. (LVDS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN– (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. The input sample starts on the positive edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DNC (Pins 21, 22, 23, 24): Do not connect these pins. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. D0–/D0+ to D9–/D9+ (Pins 27 to 32, 37 to 40, 43 to 48, 51 to 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D9 –/D9+ is the MBS. CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+. OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects straight binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects straight binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. 22301p U U U 13 LTC2230/LTC2231 PI FU CTIO S SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE (4 BITS) AIN– SECOND PIPELINED ADC STAGE (3 BITS) VCM 2.2µF 1.6V REFERENCE SHIFT REGISTER AND CORRECTION RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFLB REFHA 2.2µF 0.1µF 1µ F Figure 1. Functional Block Diagram TI I G DIAGRA S LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD D0-D9, OF tC N–5 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 CLOCKOUT – CLOCKOUT + 14 W W U U U UW U U THIRD PIPELINED ADC STAGE (3 BITS) FOURTH PIPELINED ADC STAGE (3 BITS) FIFTH PIPELINED ADC STAGE (3 BITS) REFL INTERNAL CLOCK SIGNALS OVDD DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • + OF – + D9 – + – + – D0 CLKOUT REFLA REFHB ENC+ 0.1µF 1µ F ENC– M0DE LVDS SHDN OEL 22201 F01 OGND 22201 TD01 22301p LTC2230/LTC2231 TI I G DIAGRA S Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD DA0-DA9, OFA tC CLOCKOUTB CLOCKOUTA N–5 N–4 N–3 N–2 N–1 N+1 N+2 N+3 N+4 DB0-DB9, OFB DA0-DA9, OFA DB0-DB9, OFB DA0-DA9, OFA tD DB0-DB9, OFB tC CLOCKOUTB CLOCKOUTA W UW HIGH IMPEDANCE 22201 TD02 Demultiplexed CMOS Outputs with Interleaved Update All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD N–5 tD N–6 tC CLOCKOUTB CLOCKOUTA 22201 TD03 N+2 N+3 N+1 N+4 N–3 N–1 N–4 tC N–2 Demultiplexed CMOS Outputs with Simultaneous Update All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD N–6 N–4 N–2 N+1 N+2 N+3 N+4 N–5 N–3 N–1 22201 TD04 22301p 15 LTC2230/LTC2231 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log √(V2 + V3 + V4 + . . . Vn )/V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either 2 2 2 2 16 U input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2pi) • fIN • tJITTER CONVERTER OPERATION As shown in Figure 1, the LTC2230/LTC2231 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The LTC2230/LTC2231 has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. 22301p W U U LTC2230/LTC2231 APPLICATIO S I FOR ATIO Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2230/ LTC2231 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. U When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. LTC2230/LTC2231 VDD 15Ω CPARASITIC 1pF CSAMPLE 1.6pF CPARASITIC 1pF VDD CSAMPLE 1.6pF AIN+ VDD 15Ω AIN– 1.6V 6k ENC+ ENC– 6k 1.6V 22201 F02 W UU Figure 2. Equivalent Input Circuit Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.6V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 22301p 17 LTC2230/LTC2231 APPLICATIO S I FOR ATIO U width of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω 25Ω 0.1µF AIN+ AIN+ 12pF 25Ω AIN– AIN– 22301 F03 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2230/LTC2231 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2230/LTC2231 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain band- 18 W UU LTC2230/ LTC2231 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 3. Single-Ended to Differential Conversion Using a Transformer VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT 2.2µF AIN+ AIN+ 12pF AIN– AIN– AMPLIFIER = LTC6600-20, AD8138, ETC. 22301 F04 + CM + – 25Ω LTC2230/ LTC2231 – Figure 4. Differential Drive with an Amplifier VCM 10k 0.1µF ANALOG INPUT 10k 25Ω 2.2µF AIN+ AIN+ 12pF 25Ω 0.1µF AIN– AIN– 22301 F05 LTC2230/ LTC2231 Figure 5. Single-Ended Drive 22301p LTC2230/LTC2231 APPLICATIO S I FOR ATIO The AIN+ and AIN– inputs each have two pins to reduce package inductance. The two AIN+ and the two AIN– pins should be shorted together. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF ANALOG INPUT 25Ω T1 0.1µF 25Ω 12Ω 12Ω 0.1µF AIN+ AIN+ 8pF AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22301 F06 LTC2230/ LTC2231 Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz VCM 2.2µF 0.1µF ANALOG INPUT 25Ω T1 0.1µF 25Ω AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22301 F07 AIN+ 0.1µF AIN+ LTC2230/ LTC2231 Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz VCM 2.2µF 0.1µF ANALOG INPUT 25Ω T1 0.1µF 25Ω 4.7nH 4.7nH 0.1µF AIN+ AIN+ 2pF AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22301 F08 LTC2230/ LTC2231 Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz U Reference Operation Figure 9 shows the LTC2230/LTC2231 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. The 1.6V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.6V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. LTC2230/LTC2231 1.6V VCM 2.2µF 1V RANGE DETECT AND CONTROL SENSE REFLB 0.1µF REFHA BUFFER INTERNAL ADC HIGH REFERENCE 0.5V 4Ω 1.6V BANDGAP REFERENCE TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µ F 2.2µF DIFF AMP 1µ F REFLA 0.1µF REFHB INTERNAL ADC LOW REFERENCE 22301 F09 W UU Figure 9. Equivalent Reference Circuit 22301p 19 LTC2230/LTC2231 APPLICATIO S I FOR ATIO Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. 1.6V VCM 2.2µF SENSE 1µF LTC2230/ LTC2231 12k 0.8V 12k 22301 F10 Figure 10. 1.6V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 1.7dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC2230/LTC2231 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 20 U 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. LTC2230/LTC2231 VDD TO INTERNAL ADC CIRCUITS 1.6V BIAS 6k ENC+ 0.1µF CLOCK INPUT 50Ω 1:4 VDD 1.6V BIAS 6k ENC– VDD 22201 F11 W UU Figure 11. Transformer Driven ENC+/ENC– Maximum and Minimum Encode Rates The maximum encode rate for the LTC2230/LTC2231 is 170Msps (LTC2230) and 135Msps (LTC2231). For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 2.8ns (LTC2230) or 3.5ns (LTC2231) for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal 22301p LTC2230/LTC2231 APPLICATIO S I FOR ATIO duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2230/LTC2231 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2230/LTC2231 is 1Msps. VTHRESHOLD = 1.6V ENC+ – 1.6V ENC 0.1µF LTC2230/ LTC2231 22301 F12a Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 130Ω Q0 130Ω ENC+ ENC– 83Ω 83Ω 22301 F12b D0 Q0 LTC2230/ LTC2231 Figure 12b. ENC Drive Using a CMOS to PECL Translator DIGITAL OUTPUTS 22301 F13a Digital Output Modes The LTC2230/LTC2231 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams. The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be U connected to GND, 1/3VDD, 2/3VDD or VDD. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 1 shows the logic states for the LVDS pin. Table 1. LVDS Pin Function LVDS GND 1/3VDD 2/3VDD VDD Digital Output Mode Full-Rate CMOS Demultiplexed CMOS, Simultaneous Update Demultiplexed CMOS, Interleaved Update LVDS W UU Digital Output Buffers (CMOS Modes) Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. LTC2230/LTC2231 OVDD VDD VDD 0.5V TO VDD 0.1µF OVDD DATA FROM LATCH OE OGND PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT Figure 13a. Digital Output Buffer in CMOS Mode As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2230/LTC2231 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. 22301p 21 LTC2230/LTC2231 APPLICATIO S I FOR ATIO Digital Output Buffers (LVDS Mode) Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. LTC2230/LTC2231 OVDD D – + 1.25V D 10k 10k D OUT+ 100Ω OUT– D LVDS RECEIVER 3.5mA OGND 22301 F13b Figure 13b. Digital Output in LVDS Mode Data Format The LTC2230/LTC2231 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects straight binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin. Table 2. MODE Pin Function MODE Pin 0 1/3VDD 2/3VDD VDD Output Format Straight Binary Straight Binary 2’s Complement 2’s Complement Clock Duty Cycle Stablizer Off On On Off 22 U Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow or underflow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF– pins indicates an overflow or underflow. Output Clock The ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with simultaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply. In the CMOS output mode, OVDD can be powered with any voltage up to the VDD of the part. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In the LVDS output mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND. Output Enable The outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus 22301p W UU LTC2230/LTC2231 APPLICATIO S I FOR ATIO U printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2µF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2230/LTC2231 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. HEAT TRANSFER Most of the heat generated by the LTC2230/LTC2231 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. 22301p relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance between them. Therefore in the CMOS output mode, adjacent data bits will have 20k resistance in between them, even in the Hi-Z state. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 35mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state. GROUNDING AND BYPASSING The LTC2230/LTC2231 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the W UU 23 LTC2230/LTC2231 R19 100Ω 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND EN/12 RUN1– RUN1+ RUN2+ RUN2– RUN3– RUN3+ RUN4+ RUN4– VCC EN RUN5– RUN5+ RUN6+ RUN6– RUN7– RUN7+ RUN8+ RUN8– EN/34 GND VBB VCC VCC EN/78 DOUT1– DOUT1+ DOUT2+ DOUT2– DOUT3– DOUT3+ DOUT4+ DOUT4– GND GND DOUT5– DOUT5+ DOUT6+ DOUT6– DOUT7– DOUT7+ DOUT8+ DOUT8– EN/56 VCC VCC VCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 APPLICATIO S I FOR ATIO R21 100Ω R23 100Ω R24 100Ω R25 100Ω 1 2 3 4 AIN– 5 6 C16 C17 0.1µF 7 1µF 8 C19 2.2µF 9 10 C18 C11 VDD 1µF 0.1µF 11 12 C21 62 0.1µF 63 13 VDD 14 15 C24 VDD JP3 0.1µF 17 CLK 18 GND SHDN CLK 19 20 25 C29 33 2.2µF VDD GND 41 VDD 50 0E JP1 60 VCM JP20 SENSE 59 VDD 16 VCM JP21 61 VCM 64 JP22 EXT 58 REF 57 C35 VDD 0.1µF R13 100Ω R14 100Ω R15 100Ω R16 100Ω VCC R17 100Ω R18 100Ω LTC2230 AIN+ OF+/OFA AIN+ OF–/DA11 AIN– D11+/DA10 AIN– D11–/DA9 REFHA D10+/DA8 REFHA D10–/DA7 REFLB D9+/DA6 REFLB D9–/DA5 REFHB D8+/DA4 REFHB D8–/DA3 REFLA D7+/DA2 REFLA D7–/DA1 VDD D6+/DA0 VDD D6–/CLKOUTA +/CLKOUTB VDD D5 VDD DB5–/OFB VDD CLKOUT+/DB11 ENC+ CLKOUT–/DB10 ENC– D4+/DB9 SHDN D4–/DB8 OEL D3+/DB7 OGND D3–/DB6 OGND D2+/DB5 OGND D2–/DB4 OGND D1+/DB3 VCM D1–/DB2 SENSE D0+/DB1 GND D0–/DB0 GND OVDD GND OVDD MODE OVDD LVDS OVDD 56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 36 35 32 31 30 29 28 27 24 23 22 21 49 42 34 26 JP7 VCC R26 100Ω ENABLE C34 4.7µF VDD R28 1k 2/3VDD C33 0.1µF PWR GND GND R2 4.99k 1% R3 4.99k 1% SCL C4 0.1µF VSS VCC_IN JP13 MODE C32 0.1µF JP14 VSS SCL R29 1k 1/3VDD R30 1k GND C31 0.1µF VDD VDD C3 4.7µF JP4 C30 0.1µF R11 24.9k AIN+ J6 ENCODE INPUT R7 100Ω AIN– R12 24.9k C20 0.1µF C26 0.1µF T2 ETC1-1T R8 100Ω VDD 3.3V JP19 C39 0.1µF R6 4.7k VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 R20 100Ω GND GND EN/12 RUN1– RUN1+ RUN2+ RUN2– RUN3– RUN3+ RUN4+ RUN4– VCC EN RUN5– RUN5+ RUN6+ RUN6– RUN7– RUN7+ RUN8+ RUN8– EN/34 GND VBB VCC VCC EN/78 DOUT1– DOUT1+ DOUT2+ DOUT2– DOUT3– DOUT3+ DOUT4+ DOUT4– GND GND DOUT5– DOUT5+ DOUT6+ DOUT6– DOUT7– DOUT7+ DOUT8+ DOUT8– EN/56 VCC VCC VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 SDA VCC_IN VCC ENABLE EDGE-CON-100 VCC 1 A0 2 A1 3 A2 4 A3 8 VCC 7 WP 6 SCL 5 SDA 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 R4 4.99k 1% SDA CLK C25 33pF CLK OPT VCC VCC 3.3V L1 J9 C27 0.1µF ANALOG INPUT T1 ETC1-1T C5 4.7µF MURATA BLM18BB470SN R9 24.9k R10 24.9k C1 0.1µF C2 0.1µF C5 0.1µF C6 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C12 0.1µF C36 4.7µF C23 0.1µF VCM R27 1k C22 0.1µF 22301p Evaluation Circuit Schematic of the LTC2230 U W UU 24 R1 100Ω AIN+ C7 12pF LTC2230/LTC2231 APPLICATIO S I FOR ATIO U Silkscreen Top Layer 2 GND Plane 22301p Layer 1 Component Side W UU 25 LTC2230/LTC2231 APPLICATIO S I FOR ATIO U Layer 3 Power Plane Layer 4 Bottom Side 22301p 26 W UU LTC2230/LTC2231 PACKAGE DESCRIPTIO RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP PIN 1 TOP MARK (SEE NOTE 5) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ± 0.05 7.15 ± 0.05 8.10 ± 0.05 9.50 ± 0.05 (4 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 63 64 0.40 ± 0.10 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) (UP64) QFN 0903 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 22301p 27 LTC2230/LTC2231 RELATED PARTS PART NUMBER LTC1747 LTC1748 LTC1749 LTC1750 LTC2220 LTC2221 LTC2222 LT5514 DESCRIPTION 12-Bit, 80Msps ADC 14-Bit, 80Msps ADC 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps Wideband ADC 12-Bit, 170Msps ADC 12-Bit, 135Msps ADC 12-Bit, 105Mspss ADC Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain COMMENTS 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 890mW, 67.5dB SNR, 9mm x 9mm QFN Package 660mW, 67.5dB SNR, 9mm x 9mm QFN Package 475mW, 67.9dB SNR, 7mm x 7mm QFN Package 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 22301p 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/TP 0604 1K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004