LTC2241IUP-12-TR

LTC2241-12 12-Bit, 210Msps ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Sample Rate: 210Msps 65.5dB SNR 78dB SFDR 1.2GHz Full Power Bandwidth S/H Single 2.5V Supply Low Power Dissipation: 585mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit) 210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit) 170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit) 185Msps: LTC2220-1 (12-Bit)* 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)* 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)* 64-Pin 9mm × 9mm QFN Package The LTC®2241-12 is a 210Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2241-12 is perfect for demanding communications applications with AC performance that includes 65.5dB SNR and 78dB SFDR. Ultralow jitter of 95fsRMS allows IF undersampling with excellent noise performance. DC specs include ± 0.7LSB INL (typ), ± 0.4LSB DNL (typ) and no missing codes over temperature. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 2.625V. The ENC+ and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts. APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment TYPICAL APPLICATIO REFH REFL FLEXIBLE REFERENCE 2.5V VDD 0.5V TO 2.625V OVDD D11 • • • D0 ANALOG INPUT INPUT S/H CORRECTION LOGIC OUTPUT DRIVERS – CMOS OR LVDS SFDR (dBFS) + 12-BIT PIPELINED ADC CORE OGND CLOCK/DUTY CYCLE CONTROL 224112 TA01 ENCODE INPUT U SFDR vs Input Frequency 85 80 75 70 65 60 1V RANGE 55 50 2V RANGE 45 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 224112 G11 U U 224112fa 1 LTC2241-12 ABSOLUTE AXI U RATI GS Supply Voltage (VDD) .............................................. 2.8V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) PI CO FIGURATIO 64 GND 63 VDD 62 VDD 61 GND 60 VCM 59 SENSE 58 MODE 57 LVDS 56 OF +/OFA 55 OF –/DA11 54 D11+/DA10 53 D11–/DA9 52 D10+/DA8 51 D10 –/DA7 50 OGND 49 OVDD AIN+ 1 AIN+ 2 AIN– 3 AIN– 4 REFHA 5 REFHA 6 REFLB 7 REFLB 8 REFHB 9 REFHB 10 REFLA 11 REFLA 12 VDD 13 VDD 14 VDD 15 GND 16 65 48 D9+/DA6 47 D9–/DA5 46 D8+/DA4 45 D8–/DA3 44 D7 +/DA2 43 D7 –/DA1 42 OVDD 41 OGND 40 D6+/DA0 39 D6–/CLKOUTA 38 D5+/CLKOUTB 37 D5–/OFB 36 CLKOUT +/DB11 35 CLKOUT –/DB10 34 OVDD 33 OGND UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB TJMAX = 150°C, θJA = 20°C/W ORDER I FOR ATIO LEAD FREE FINISH LTC2241CUP-12#PBF LTC2241IUP-12#PBF LEAD BASED FINISH LTC2241CUP-12 LTC2241IUP-12 TAPE AND REEL LTC2241CUP-12#TRPBF LTC2241IUP-12#TRPBF TAPE AND REEL LTC2241CUP-12#TR LTC2241IUP-12#TR ENC + 17 ENC – 18 SHDN 19 OE 20 – DO /DB0 21 +/DB1 22 DO D1–/DB2 23 D1+/DB3 24 OGND 25 OVDD 26 D2–/DB4 27 D2+/DB5 28 D3–/DB6 29 D3+/DB7 30 D4–/DB8 31 D4+/DB9 32 Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 U U WW U W W OVDD = VDD (Notes 1, 2) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2241C-12 .......................................... 0°C to 70°C LTC2241I-12 .......................................–40°C to 85°C Storage Temperature Range ..................–65°C to 150°C U U U TOP VIEW PART MARKING* LTC2241UP-12 LTC2241UP-12 PART MARKING* LTC2241UP-12 LTC2241UP-12 PACKAGE DESCRIPTION 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN PACKAGE DESCRIPTION 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 125°C TEMPERATURE RANGE 0°C to 70°C –40°C to 125°C 224112fa LTC2241-12 CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference CONDITIONS ● ● ● ● ● A ALOG I PUT SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS tAP tJITTER PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 2.375V < VDD < 2.625V (Note 7) + –)/2 Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN + AIN Analog Input Leakage Current SENSE Input Leakage MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Sample and Hold Acquisition Delay Time Sample and Hold Acquisition Delay Time Jitter Full Power Bandwidth DY A IC ACCURACY SYMBOL SNR PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 10MHz Input 70MHz Input 140MHz Input 240MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic (Note 11) 10MHz Input 70MHz Input 140MHz Input 240MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher (Note 11) 10MHz Input 70MHz Input 140MHz Input 240MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio (Note 12) 10MHz Input 70MHz Input 140MHz Input 240MHz Input IMD Intermodulation Distortion fIN1 = 135MHz, fIN2 = 140MHz ● ● ● ● Signal-to-Noise Ratio (Note 10) U WU U MIN 12 –2.3 –1 –15 –3.4 TYP ±0.7 ±0.4 ±5 ±0.7 ± 10 ± 60 ± 45 0.74 MAX 2.3 1 15 3.4 UNITS Bits LSB LSB mV %FS µV/C ppm/C ppm/C LSBRMS U MIN ● ● ● ● TYP ±0.5 to ±1 1.25 MAX 1.3 1 1 UNITS V V µA µA µA µA ns fsRMS MHz Differential Input (Note 7) 0 < AIN+, AIN– < VDD 0V < SENSE < 1V 1.2 –1 –1 7 7 0.4 95 Figure 8 Test Circuit 1200 MIN 64 TYP 65.5 65.4 65.4 65.2 78 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc 224112fa 65 74 73 72 87 74 87 87 87 65.4 62.1 65.2 65.1 64.9 81 3 LTC2241-12 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 2.375V < VDD < 2.625V –1mA < IOUT < 1mA CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VID VICM RIN CIN VIH VIL IIN CIN OVDD = 2.5V COZ ISOURCE ISINK VOH VOL OVDD = 1.8V VOH VOL VOD VOS High Level Output Voltage Low Level Output Voltage Differential Output Voltage Output Common Mode Voltage IO = –500µA IO = 500µA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 2.5V IO = –10µA IO = –500µA IO = 10µA IO = 500µA PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance (Note 7) VDD = 2.5V VDD = 2.5V VIN = 0V to VDD (Note 7) CONDITIONS (Note 7) Internally Set Externally Set (Note 7) ENCODE INPUTS (ENC +, ENC –) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● ● LOGIC INPUTS (OE, SHDN) ● ● ● LOGIC OUTPUTS (CMOS MODE) 3 37 23 2.495 2.45 0.005 0.07 1.75 0.07 ● ● LOGIC OUTPUTS (LVDS MODE) 100Ω Differential Load 100Ω Differential Load 247 1.125 350 1.250 454 1.375 mV V 4 U U U U U (Note 4) MIN 1.225 TYP 1.25 ±35 3 2 MAX 1.275 UNITS V ppm/°C mV/V Ω TYP MAX UNITS V 0.2 1.2 1.5 1.5 4.8 2 1.7 0.7 –10 3 10 2.0 V V kΩ pF V V µA pF pF mA mA V V V V V V 224112fa LTC2241-12 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL VDD PSLEEP PNAP OVDD IVDD IOVDD PDISS OVDD IVDD PDISS PARAMETER Analog Supply Voltage Sleep Mode Power Nap Mode Power Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Power Dissipation (Note 8) (Note 7) CONDITIONS (Note 8) SHDN = High, OE = High, No CLK SHDN = High, OE = Low, No CLK (Note 8) ● ● ● ● ● ● ● POWER REQUIRE E TS LVDS OUTPUT MODE 2.375 2.5 226 58 710 0.5 2.5 226 585 2.625 252 70 805 2.625 252 V mA mA mW V mA mW CMOS OUTPUT MODE The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fS tL tH tAP tOE tD tC PARAMETER Sampling Frequency ENC Low Time (Note 7) ENC High Time (Note 7) Sample-and-Hold Aperture Delay Output Enable Delay ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Rise Time Fall Time Pipeline Latency CMOS OUTPUT MODE tD tC Pipeline Latency ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous (Note 7) (Note 7) (tC – tD) (Note 7) ● ● ● TI I G CHARACTERISTICS LVDS OUTPUT MODE (Note 7) (Note 7) (tC – tD) (Note 7) ● ● ● UW MIN 2.375 TYP 2.5 1 28 MAX 2.625 UNITS V mW mW UW CONDITIONS (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On ● ● ● ● ● MIN 1 2.26 1.5 2.26 1.5 TYP 2.38 2.38 2.38 2.38 0.4 MAX 210 500 500 500 500 UNITS MHz ns ns ns ns ns (Note 7) ● 5 1 1 –0.6 1.7 1.7 0 0.5 0.5 5 1 1 –0.6 1.7 1.7 0 5 5 5 and 6 10 2.8 2.8 0.6 ns ns ns ns ns ns Cycles 2.8 2.8 0.6 ns ns ns Cycles Cycles Cycles 224112fa 5 LTC2241-12 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 2.5V, fSAMPLE = 210MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: VDD = 2.5V, fSAMPLE = 210MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower. Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes. Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower. TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity 1.0 0.8 0.6 0.4 1.0 0.8 0.6 AMPLITUDE (dB) DNL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 OUTPUT CODE 4096 224112 G01 6 UW (TA = 25°C unless otherwise noted, Note 4) Differential Nonlinearity 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 1024 2048 3072 OUTPUT CODE 4096 224112 G02 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, LVDS Mode 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G03 224112fa LTC2241-12 TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –40 –50 –60 –70 –80 –90 AMPLITUDE (dB) –100 –110 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G04 8192 Point FFT, fIN = 500MHz, –1dB, 1V Range, LVDS Mode 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 AMPLITUDE (dB) AMPLITUDE (dB) –100 –110 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G07 SNR vs Input Frequency, –1dB, LVDS Mode 67 66 65 2V RANGE 64 SFDR (dBFS) SFDR (dBFS) SNR (dBFS) 63 62 61 60 59 58 1V RANGE 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 224112 G10 UW (TA = 25°C unless otherwise noted, Note 4) 8192 Point FFT, fIN = 240MHz, –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –100 –110 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G05 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G06 8192 Point FFT, fIN = 1GHz, –1dB, 1V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G08 8192 Point 2-Tone FFT, fIN = 135MHz and 140MHz, –1dB, 2V Range, LVDS Mode –40 –50 –60 –70 –80 –90 –100 –110 0 20 40 60 80 FREQUENCY (MHz) 100 224112 G09 SFDR (HD2 and HD3) vs Input Frequency, –1dB, LVDS Mode 85 80 75 SFDR (HD4+) vs Input Frequency, –1dB, LVDS Mode 95 90 2V RANGE 85 70 65 60 1V RANGE 55 50 2V RANGE 45 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 224112 G11 1V RANGE 80 75 70 65 60 0 100 200 300 400 500 600 700 800 9001000 INPUT FREQUENCY (MHz) 224112 G12 224112fa 7 LTC2241-12 TYPICAL PERFOR A CE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB, LVDS Mode 95 90 SFDR SFDR AND SNR (dBFS) SFDR (dBc AND dFBS) 85 80 75 70 65 60 55 50 0 50 200 150 100 SAMPLE RATE (Msps) 250 224112 G13 50 40 30 20 10 0 –50 –40 SNR (dBFS) SNR IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 240 230 220 210 1V RANGE 200 190 180 170 IOVDD (mA) IVDD (mA) 0 50 8 UW 2V RANGE 100 (TA = 25°C unless otherwise noted, Note 4) SFDR vs Input Level, fIN = 70MHz, 2V Range 90 80 70 60 dBc 64 63 62 61 60 66 SNR vs SENSE, fIN = 5MHz, –1dB 65 dBFS –20 –30 –10 INPUT LEVEL (dBFS) 0 224112 G14 59 0.5 0.6 0.7 0.8 0.9 1 SENSE PIN (V) 224112 G15 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 60 50 40 30 20 10 0 LVDS OUTPUTS OVDD = 2.5V CMOS OUTPUTS OVDD = 1.8V 200 150 SAMPLE RATE (Msps) 250 224112 G16 0 50 100 150 200 SAMPLE RATE (Msps) 250 224112 G17 224112fa LTC2241-12 PI FU CTIO S (CMOS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN – (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC – (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended encode signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high impedance in full rate CMOS mode. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under flow has occurred. At high impedance in full rate CMOS mode. CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode. CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA. DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA11 is the MSB. OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 224112fa U U U 9 LTC2241-12 PI FU CTIO S (LVDS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN– (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended encode signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+. OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 10 U U U 224112fa LTC2241-12 FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND AIN– VCM 2.2µF 1.25V REFERENCE RANGE SELECT SHIFT REGISTER AND CORRECTION SENSE REF BUF REFH DIFF REF AMP REFLB REFHA 2.2µF 0.1µF 1µF Figure 1. Functional Block Diagram W VDD REFL INTERNAL CLOCK SIGNALS OVDD DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS • • • U U + OF – + D11 – + – + – D0 CLKOUT REFLA REFHB 0.1µF 1µF ENC + 224112 F01 OGND ENC– M0DE LVDS SHDN OE 224112fa 11 LTC2241-12 TI I G DIAGRA S LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels ANALOG INPUT ENC – ENC + tD D0-D11, OF tC N–5 N–4 N–3 N–2 N–1 CLKOUT – CLKOUT + ANALOG INPUT ENC – ENC + tD DA0-DA11, OFA tC CLKOUTB CLKOUTA N–5 N–4 N–3 N–2 N–1 DB0-DB11, OFB 12 W UW tAP N tH tL N+1 N+2 N+3 N+4 224112 TD01 Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP N tH tL N+1 N+2 N+3 N+4 HIGH IMPEDANCE 224112 TD02 224112fa LTC2241-12 TI I G DIAGRA S Demultiplexed CMOS Outputs with Interleaved Update All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N tH tL ENC – ENC + tD DA0-DA11, OFA N–5 tD DB0-DB11, OFB N–6 tC CLKOUTB CLKOUTA 224112 TD03 ANALOG INPUT ENC – ENC + tD DA0-DA11, OFA tD DB0-DB11, OFB tC CLKOUTB CLKOUTA 224112 TD04 W UW N+2 N+3 N+1 N+4 N–3 N–1 N–4 tC N–2 Demultiplexed CMOS Outputs with Simultaneous Update All Outputs Are Single-Ended and Have CMOS Levels tAP N tH tL N+1 N+2 N+3 N+4 N–6 N–4 N–2 N–5 N–3 N–1 224112fa 13 LTC2241-12 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: ⎛ THD = 20Log ⎜ ⎝ ( ⎞ V22 + V32 + V 42 + ...Vn2 / V1 ⎟ ⎠ ) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 14 U 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2241-12 is a CMOS pipelined multi-step converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially. The encode input is differential for improved common mode noise immunity. The LTC2241-12 has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. 224112fa W U U LTC2241-12 APPLICATIO S I FOR ATIO Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2241-12 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. U LTC2241-12 VDD 10Ω CPARASITIC 1.8pF RON 14Ω CPARASITIC 1.8pF VDD CSAMPLE 2pF RON 14Ω CSAMPLE 2pF AIN+ VDD 10Ω AIN– 1.5V 6k ENC+ ENC– 6k 1.5V 224112 F02 W UU Figure 2. Equivalent Input Circuit When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.25V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp 224112fa 15 LTC2241-12 APPLICATIO S I FOR ATIO differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2241-12 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 2pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2fS); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2241-12 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the ANALOG INPUT 0.1µF 16 U limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a capacitively-coupled input circuit. The impedance seen by the analog inputs should be matched. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the 10Ω VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω 25Ω 0.1µF AIN+ AIN+ 12pF 25Ω AIN– AIN– 224112 F03 W UU LTC2241-12 T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 3. Single-Ended to Differential Conversion Using a Transformer 50Ω HIGH SPEED DIFFERENTIAL AMPLIFIER VCM 2.2µF 25Ω 3pF AIN+ AIN+ 12pF LTC2241-12 + CM + – – 25Ω 3pF AIN– AIN– 224112 F04 Figure 4. Differential Drive with an Amplifier VCM 100Ω 100Ω 25Ω 2.2µF AIN+ AIN+ ANALOG INPUT 0.1µF 25Ω 12pF AIN– AIN– 224112 F05 0.1µF LTC2241-12 Figure 5. Capacitively-Coupled Drive 224112fa LTC2241-12 APPLICATIO S I FOR ATIO sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. The AIN+ and AIN– inputs each have two pins to reduce package inductance. The two AIN+ and the two AIN– pins should be shorted together. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center-tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.25V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2241-12 reference circuitry consisting of a 1.25V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. The 1.25V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.25V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. U 10Ω VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 12Ω 25Ω 12Ω 0.1µF AIN+ AIN+ 8pF AIN– AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 224112 F06 W UU LTC2241-12 Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz 10Ω VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 25Ω 0.1µF AIN+ AIN+ AIN– AIN– LTC2241-12 T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 224112 F07 Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz 10Ω VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 25Ω 2.7nH 0.1µF AIN+ AIN+ AIN– AIN– LTC2241-12 2.7nH T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 224112 F08 Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz 224112fa 17 LTC2241-12 APPLICATIO S I FOR ATIO LTC2241-12 1.25V VCM 2.2µF 2Ω 1.25V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE REFLB 0.1µF REFHA 0.5V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µF BUFFER INTERNAL ADC HIGH REFERENCE 2.2µF 1µF DIFF AMP REFLA 0.1µF REFHB INTERNAL ADC LOW REFERENCE 224112 F09 Figure 9. Equivalent Reference Circuit 1.25V 8k 0.75V 12k VCM 2.2µF SENSE 1µF LTC2241-12 224112 F10 Figure 10. 1.5V Range ADC Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin 18 U is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC2241-12 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 4.8k resistor to a 1.5V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 2.0V. Each input may be driven from ground to VDD for single-ended drive. 224112fa W UU LTC2241-12 APPLICATIO S I FOR ATIO CLOCK INPUT T1 MA/COM 0.1µF ETC1-1-13 • • 50Ω 8.2pF 0.1µF 50Ω ENC– 0.1µF Figure 11. Transformer Driven ENC+/ENC– 0.1µF LVDS CLOCK VTHRESHOLD = 1.5V ENC+ 1.5V ENC– LTC2241-12 0.1µF 224112 F12a Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter Maximum and Minimum Encode Rates The maximum encode rate for the LTC2241-12 is 210Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 2.26ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal U LTC2241-12 VDD TO INTERNAL ADC CIRCUITS 1.5V BIAS 4.8k ENC+ VDD 100Ω VDD 1.5V BIAS 4.8k 224112 F11 W UU ENC+ LTC2241-12 ENC– 100Ω 0.1µF 224112 F12b Figure 12b. ENC Drive Using LVDS duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2241-12 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2241-12 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. 224112fa 19 LTC2241-12 APPLICATIO S I FOR ATIO Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V –0.000488V –0.000976V –0.999512V –1.000000V