LTC2255IUH

LTC2255/LTC2254 14-Bit, 125/105Msps Low Power 3V ADCs FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Sample Rate: 125Msps/105Msps Single 3V Supply (2.85V to 3.4V) Low Power: 395mW/320mW 72.4dB SNR 88dB SFDR No Missing Codes Flexible Input: 1VP-P to 2VP-P Range 640MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm × 5mm) QFN Package The LTC®2255/LTC2254 are 14-bit 125Msps/105Msps, low power 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2255/ LTC2254 are perfect for demanding imaging and communications applications with AC performance that includes 72.3dB SNR and 85dB SFDR for signals at the Nyquist frequency. DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.3 LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Ultrasound Spectral Analysis Portable Instrumentation TYPICAL APPLICATIO REFH REFL FLEXIBLE REFERENCE OVDD SNR (dBFS) + ANALOG INPUT INPUT S/H – 14-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS D13 • • • D0 OGND CLOCK/DUTY CYCLE CONTROL 22554 TA01a CLK 22554fa U LTC2255: SNR vs Input Frequency, –1dB, 2V Range, 125Msps 75 74 73 72 71 70 69 68 67 66 65 0 50 100 150 200 250 300 350 33554 G09 INPUT FREQUENCY (MHz) U U 1 LTC2255/LTC2254 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW SENSE MODE VCM D13 D12 D11 VDD OF OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2255C, LTC2254C ............................. 0°C to 70°C LTC2255I, LTC2254I ...........................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C ORDER PART NUMBER 24 D10 23 D9 22 D8 32 31 30 29 28 27 26 25 AIN+ 1 AIN– 2 REFH 3 REFH 4 REFL 5 REFL 6 VDD 7 GND 8 9 10 11 12 13 14 15 16 OE D0 D1 D2 D3 CLK SHDN D4 33 21 OVDD 20 OGND 19 D7 18 D6 17 D5 LTC2255CUH LTC2255IUH LTC2254CUH LTC2254IUH QFN PART* MARKING 2255 2254 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) IS GND MUST BE SOLDERED TO PCB Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● LTC2255 TYP MAX ±1 ±0.5 ±2 ±0.5 ±10 ±30 ±5 1.3 5 1 12 2.5 MIN 14 –5.5 –1 –12 –2.5 LTC2254 TYP MAX ±1 ±0.5 ±2 ±0.5 ±10 ±30 ±5 1.3 5.5 1 12 2.5 UNITS Bits LSB LSB mV %FS µV/°C ppm/°C ppm/°C LSBRMS 14 –5 –1 –12 –2.5 Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference ● ● ● ● 22554fa 2 U W U U WW W U LTC2255/LTC2254 A ALOG I PUT SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 2.85V < VDD < 3.4V (Note 7) Differential Input (Note 7) 0V < AIN+, AIN– < VDD 0V < SENSE < 1V ● ● ● ● ● Analog Input Range (AIN+ – AIN–) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage MODE Pin Leakage Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input IMD Intermodulation Distortion fIN1 = 28.2MHz fIN2 = 26.8MHz ● ● ● ● U WU U MIN 1 –1 –3 –3 TYP 1.5 MAX 1.9 1 3 3 UNITS V V µA µA µA ns psRMS dB MHz ± 0.5V to ±1V 0 0.2 80 Figure 8 Test Circuit 640 MIN LTC2255 TYP MAX 72.4 72.3 MIN LTC2254 TYP MAX 72.5 72.4 UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 68.9 72.1 71.7 88 85 69.4 72.3 71.7 88 88 73 82 78 90 90 71 84 80 90 90 77 90 90 72.2 72 79 90 90 72.4 72.2 68 71.9 70.2 85 68.5 72 70.6 85 22554fa 3 LTC2255/LTC2254 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V LOGIC INPUTS (CLK, OE, SHDN) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● ● ● POWER REQUIRE E TS SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power Nap Mode Power The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) CONDITIONS (Note 9) (Note 9) ● ● ● ● 4 UW U U U U U (Note 4) MIN 1.475 TYP 1.500 ±25 3 4 MAX 1.525 UNITS V ppm/°C mV/V Ω 2.85V < VDD < 3.4V –1mA < IOUT < 1mA TYP MAX UNITS V 2 0.8 –10 3 10 V µA pF VIN = 0V to VDD (Note 7) OE = High (Note 7) VOUT = 0V VOUT = 3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA ● ● 3 50 50 2.7 2.995 2.99 0.005 0.09 2.49 0.09 1.79 0.09 0.4 pF mA mA V V V V V V V V MIN 2.85 0.5 LTC2255 TYP MAX 3 3 132 395 2 15 3.4 3.6 156 468 MIN 2.85 0.5 LTC2254 TYP MAX 3 3 107 320 2 15 3.4 3.6 126 378 UNITS V V mA mW mW mW SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK 22554fa LTC2255/LTC2254 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fs tL PARAMETER Sampling Frequency CLK Low Time CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● ● ● ● TI I G CHARACTERISTICS tH tAP tD Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254), input range = 2VP-P with differential drive, clock duty cycle stabilizer on, unless otherwise noted. UW MIN 1 3.8 3 3.8 3 LTC2255 TYP MAX 125 4 4 4 4 0 500 500 500 500 MIN 1 4.5 3 4.5 3 LTC2254 TYP MAX 105 4.76 4.76 4.76 4.76 0 500 500 500 500 UNITS MHz ns ns ns ns ns CLK High Time Sample-and-Hold Aperture Delay CLK to DATA delay Data Access Time After OE↓ BUS Relinquish Time CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7) ● ● ● 1.4 2.7 4.3 3.3 5 5.4 10 8.5 1.4 2.7 4.3 3.3 5 5.4 10 8.5 ns ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254), input range = 1VP-P with differential drive. Note 9: Recommended operating conditions. 22554fa 5 LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS LTC2255: Typical INL, 2V Range, 125Msps 2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 CODE 12288 16384 22554 G01 AMPLITUDE (dB) LTC2255: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 125Msps 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 22554 G04 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 22554 G05 AMPLITUDE (dB) LTC2255: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 125Msps 0 –10 –20 –30 AMPLITUDE (dB) –40 SNR (dBFS) COUNT –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 22554 G07 6 UW LTC2255: Typical DNL, 2V Range, 125Msps 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16384 22554 G02 LTC2255: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 125Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 22554 G03 LTC2255: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 125Msps 0 –10 –20 –30 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 LTC2255: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 125Msps 0 10 20 30 40 FREQUENCY (MHz) 50 60 22554 G06 LTC2255: Grounded Input Histogram, 125Msps 25000 20331 18639 75 74 73 72 15000 11975 10000 6939 5000 3684 704 3 79 8181 8183 8185 8187 CODE 2727 419 26 1 8189 8191 22554 G08 LTC2255: SNR vs Input Frequency, –1dB, 2V Range, 125Msps 20000 71 70 69 68 67 66 65 0 50 100 150 200 250 300 350 33554 G09 INPUT FREQUENCY (MHz) 22554fa 0 LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS LTC2255: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 100 95 SNR AND SFDR (dBFS) 90 SNR (dBc AND dBFS) SFDR (dBRS) 85 80 75 70 65 0 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 22554 G10 LTC2255: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 110 100 90 dBFS 145 140 135 130 SFDR (dBc AND dBFS) 80 IVDD (mA) 70 60 50 40 30 20 10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 22554 G14 INPUT LEVEL (dBFS) dBc LTC2255: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 8 7 6 SNR (dBFS) IOVDD (mA) 5 4 3 2 1 0 0 20 40 80 100 60 SAMPLE RATE (Msps) 120 140 22554 G16 UW LTC2255: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 90 SFDR 80 SNR 70 80 70 60 50 LTC2255: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps dBFS dBc 40 30 20 10 60 50 0 20 40 60 80 100 120 140 160 22554 G11 SAMPLE RATE (Msps) 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 22554 G13 LTC2255: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 125 120 115 110 105 100 95 0 20 60 80 100 40 SAMPLE RATE (Msps) 120 140 22554 G15 2V RANGE 1V RANGE LTC2255: SNR vs SENSE, fIN = 5MHz, –1dB 74 73 72 71 70 69 68 67 66 65 64 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1.0 1.1 22554 G32 22554fa 7 LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS LTC2254: Typical INL, 2V Range, 105Msps 2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) AMPLITUDE (dB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 CODE 12288 16384 22554 G17 LTC2254: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 105Msps 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 30 40 20 FREQUENCY (MHz) 50 22554 G20 LTC2254: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 105Msps 0 –10 –20 –30 AMPLITUDE (dB) –40 –60 –70 –80 –90 –100 –110 –120 0 10 30 40 20 FREQUENCY (MHz) 50 22554 G23 COUNT –50 12000 10000 8000 6000 4000 2000 0 11299 SNR (dBFS) 8 UW LTC2254: Typical DNL, 2V Range, 105Msps 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16384 22554 G018 LTC2254: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 30 40 20 FREQUENCY (MHz) 50 22554 G19 LTC2254: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 10 30 40 20 FREQUENCY (MHz) 50 22554 G21 LTC2254: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 105Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 –120 0 10 30 40 20 FREQUENCY (MHz) 50 22554 G22 LTC2254: Grounded Input Histogram, 105Msps 20000 18000 16000 14000 10516 17646 18027 75 74 73 72 71 70 69 68 LTC2254: SNR vs Input Frequency, –1dB, 2V Range, 105Msps 3380 3 54 581 8183 8185 8187 8189 CODE 3316 637 68 1 8191 8193 22554 G24 67 66 65 0 50 100 150 200 250 300 350 33554 G25 INPUT FREQUENCY (MHz) 22554fa LTC2255/LTC2254 TYPICAL PERFOR A CE CHARACTERISTICS LTC2254: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 100 95 SNR AND SFDR (dBFS) 90 SFDR 90 SFDR (dBRS) SNR (dBc AND dBFS) 85 80 75 70 65 0 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 22554 G26 LTC2254: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 110 100 90 SFDR (dBc AND dBFS) 80 70 60 50 40 30 20 10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 22554 G29 INPUT LEVEL (dBFS) 85 80 75 0 20 40 60 80 SAMPLE RATE (Msps) 100 120 22554 G30 IVDD (mA) LTC2254: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 7 6 5 SNR (dBFS) IOVDD (mA) 4 3 2 1 0 0 20 60 80 40 SAMPLE RATE (Msps) 100 120 22554 G31 UW dBc LTC2254: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 80 70 60 50 LTC2254: SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps dBFS 80 SNR 70 dBc 40 30 20 10 60 50 0 20 40 60 80 100 SAMPLE RATE (Msps) 120 140 22554 G27 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 22554 G28 LTC2254: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 120 115 110 105 100 95 90 2V RANGE 1V RANGE dBFS LTC2254: SNR vs SENSE, fIN = 5MHz, –1dB 74 73 72 71 70 69 68 67 66 65 64 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1.0 1.1 22554 G33 22554fa 9 LTC2255/LTC2254 PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D13 is the MSB. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OVDD can be 0.5V to 3.6V. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 10 U U U 22554fa LTC2255/LTC2254 FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE AIN– VCM 2.2µF 1.5V REFERENCE RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFH 0.1µF 2.2µF 1µF Figure 1. Functional Block Diagram TI I G DIAGRA tAP ANALOG INPUT N tH tL CLK tD D0-D13, OF N–5 N–4 N–3 N–2 N–1 N 22554 TD01 N+1 W SHIFT REGISTER AND CORRECTION REFL INTERNAL CLOCK SIGNALS OVDD OF CLOCK/DUTY CYCLE CONTROL D13 CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFL CLK M0DE SHDN OE 22554 BD01 W U UW U OGND 1µF Timing Diagram N+2 N+3 N+4 N+5 22554fa 11 LTC2255/LTC2254 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2255/LTC2254 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2255/LTC2254 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and 22554fa 12 U input tone to the RMS value of the largest 3rd order intermodulation product. W UU LTC2255/LTC2254 APPLICATIO S I FOR ATIO output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2255/ LTC2254 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed U to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. LTC2255/LTC2254 VDD 15Ω CPARASITIC 1pF CSAMPLE 3.5pF CPARASITIC 1pF VDD CLK CSAMPLE 3.5pF AIN+ VDD 15Ω AIN– 22554 F02 W U U Figure 2. Equivalent Input Circuit Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. 22554fa 13 LTC2255/LTC2254 APPLICATIO S I FOR ATIO Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2255/LTC2254 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 3.5pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2255/LTC2254 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. ANALOG INPUT 14 U Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 22554 F03 W UU 25Ω 0.1µF AIN+ LTC2255/ LTC2254 12pF Figure 3. Single-Ended to Differential Conversion Using a Transformer VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER 2.2µF AIN+ LTC2255/ LTC2254 + CM + 12pF – – 25Ω AIN– 22554 F04 Figure 4. Differential Drive with an Amplifier VCM 1k 1k 25Ω 2.2µF AIN+ 0.1µF ANALOG INPUT LTC2255/ LTC2254 12pF 25Ω 0.1µF AIN– 224876 F05 Figure 5. Single-Ended Drive 22554fa LTC2255/LTC2254 APPLICATIO S I FOR ATIO For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 12Ω AIN– 22554 F06 12Ω 25Ω 0.1µF AIN+ LTC2255/ LTC2254 8pF T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 22554 F07 AIN+ 25Ω 0.1µF LTC2255/ LTC2254 1.5V VCM 2.2µF Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 8.2nH – 22554 F08 8.2nH 25Ω 0.1µF AIN+ LTC2255/ LTC2254 AIN T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz U Reference Operation Figure 9 shows the LTC2255/LTC2254 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output LTC2255/LTC2254 4Ω 1.5V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 0.5V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µ F 2.2µF 1µ F REFL INTERNAL ADC LOW REFERENCE 22554 F09 W UU 0.1µF DIFF AMP Figure 9. Equivalent Reference Circuit 22554fa 15 LTC2255/LTC2254 APPLICATIO S I FOR ATIO pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. 1.5V VCM 2.2µF SENSE 1µ F LTC2255/ LTC2254 12k 0.75V 12k 22554 F10 Figure 10. 1.5V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5.7dB. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11). The noise performance of the LTC2255/LTC2254 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. 16 U 4.7µF FERRITE BEAD 0.1µF SINUSOIDAL CLOCK INPUT 0.1µF 1k CLK 50Ω 1k NC7SVU04 LTC2255/ LTC2254 CLEAN SUPPLY 22554 F11 W UU Figure 11. Sinusoidal Single-Ended CLK Drive Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large 4.7µF FERRITE BEAD 0.1µF CLEAN SUPPLY CLK 100Ω LTC2255/ LTC2254 22554 F12 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter ETC1-1T 5pF-30pF DIFFERENTIAL CLOCK INPUT CLK LTC2255/ LTC2254 22554 F13 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer 22554fa LTC2255/LTC2254 APPLICATIO S I FOR ATIO bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2255/LTC2254 is 125Msps (LTC2255) and 105Msps (LTC2254). The lower limit of the LTC2255/LTC2254 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2255/LTC2254 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will U require a hundred clock cycles for the PLL to lock onto the input clock. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) >+1.000000V +0.999878V +0.999756V +0.000122V 0.000000V –0.000122V –0.000244V –0.999878V –1.000000V