LTC2259-14

FEATURES n n n n n n n n n n n n LTC2192 LTC2191/LTC2190 16-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs DESCRIPTION Electrical Specifications Subject to Change 2-Channel Simultaneous Sampling ADC Serial LVDS Outputs: 1, 2 or 4 Bits per Channel 77dB SNR 90dB SFDR Low Power: 198mW/146mW/104mW Total 99mW/73mW/52mW per Channel Single 1.8V Supply Selectable Input Ranges: 1VP-P to 2VP-P 550MHz Full-Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration 52-Pin (7mm × 8mm) QFN Package The LTC®2192/LTC2191/LTC2190 are 2-channel, simultaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.3LSBRMS. To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs one bit, two bits or four bits at a time. The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIONS n n n n n n Communications Cellular Base Stations Software-Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing TYPICAL APPLICATION 2-Tone FFT, fIN = 70MHz and 69MHz 1.8V VDD CH1 ANALOG INPUT CH2 ANALOG INPUT ENCODE INPUT S/H 16-BIT ADC CORE 16-BIT ADC CORE 1.8V OVDD OUT1A OUT1B OUT1C OUT1D OUT2A OUT2B OUT2C OUT2D DATA CLOCK OUT FRAME 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 S/H DATA SERIALIZER SERIALIZED LVDS OUTPUTS PLL –90 –100 –110 –120 GND OGND 219210 TA01a 0 20 10 FREQUENCY (MHz) 30 219210 G07 219210p 1 LTC2192 LTC2191/LTC2190 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW OUT1A+ OUT1A– OUT1B+ OUT2C– OUT1B– 40 OUT1C+ 39 OUT1C– 38 OUT1D+ 37 OUT1D– 36 DCO+ 35 DCO– 53 GND 34 OVDD 33 OGND 32 FR+ 31 FR– 30 OUT2A+ 29 OUT2A– 28 OUT2B+ 27 OUT2B– 15 16 17 18 19 20 21 22 23 24 25 26 VDD VDD CS SCK ENC+ ENC– SDI GND OUT2D– OUT2D+ OUT2C+ SENSE VREF GND GND GND SDO VDD VCM1 1 GND 2 AIN1+ 3 AIN1– 4 GND 5 REFH 6 REFL 7 REFH 8 REFL 9 PAR/SER 10 AIN2+ 11 AIN2– 12 GND 13 VCM2 14 VDD Supply Voltages VDD, OVDD................................................ –0.3V to 2V Analog Input Voltage AIN+, AIN–, PAR/SER, SENSE (Note 3) ....................................–0.3V to (VDD + 0.2V) Digital Input Voltage ENC+, ENC–, CS, SDI, SCK (Note 4) ...... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2192C, LTC2191C, LTC2190C............. 0°C to 70°C LTC2192I, LTC2191I, LTC2190I ............ –40°C to 85°C Storage Temperature Range................... –65°C to 150°C 52 51 50 49 48 47 46 45 44 43 42 41 UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 29°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2192CUKG#PBF LTC2192IUKG#PBF LTC2191CUKG#PBF LTC2191IUKG#PBF LTC2190CUKG#PBF LTC2190IUKG#PBF TAPE AND REEL LTC2192CUKG#TRPBF LTC2192IUKG#TRPBF LTC2191CUKG#TRPBF LTC2191IUKG#TRPBF LTC2190CUKG#TRPBF LTC2190IUKG#TRPBF PART MARKING* LTC2192UKG LTC2192UKG LTC2191UKG LTC2191UKG LTC2190UKG LTC2190UKG PACKAGE DESCRIPTION 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 219210p 2 LTC2192 LTC2191/LTC2190 CONVERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise Internal Reference External Reference Differential Analog Input (Note 6) Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN 16 tbd –1 –9 –2.1 ±2 ±0.5 ±1.5 ±1.5 –0.6 ±10 ±30 ±10 ±0.3 ±1.5 3.3 tbd 1 9 0.9 LTC2192 TYP MAX MIN 16 tbd –1 –9 –2.1 ±2 ±0.5 ±1.5 ±1.5 –0.6 ±10 ±30 ±10 ±0.3 ±1.5 3.3 tbd 1 9 0.9 LTC2191 TYP MAX MIN 16 tbd –1 –9 –2.1 ±2 ±0.5 ±1.5 ±1.5 –0.6 ±10 ±30 ±10 ±0.3 ±1.5 3.2 tbd 1 9 0.9 LTC2190 TYP MAX UNITS Bits LSB LSB mV %FS %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS ANALOG INPUT SYMBOL VIN VIN(CM) VSENSE IINCM IIN1 IIN2 IIN3 tAP tJITTER CMRR BW–3B PARAMETER The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) External Reference Mode Per Pin, 65Msps Per Pin, 40Msps Per Pin, 25Msps 0 < AIN+, AIN– < VDD 0 < PAR/SER < VDD 0.625V < SENSE < 1.3V Single-Ended Encode Differential Encode Figure 6 Test Circuit l l l l l l MIN 0.7 0.625 TYP 1 to 2 VCM 1.250 104 64 40 MAX 1.25 1.300 UNITS VP-P V V µA µA µA Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ + AIN–)/2 External Voltage Reference Applied to SENSE Analog Input Common Mode Current Analog Input Leakage Current (No Encode) PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth –1 –3 –6 0 0.07 0.09 80 550 1 3 6 µA µA µA ns psRMS psRMS dB MHz 219210p 3 LTC2192 LTC2191/LTC2190 DYNAMIC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input l MIN tbd LTC2192 TYP MAX 77 76.9 76.8 76.3 90 90 89 84 95 95 95 95 76.8 76.7 76.4 76.3 –110 MIN tbd LTC2191 TYP MAX 76.9 76.8 76.7 76.2 90 90 89 84 95 95 95 95 76.7 76.6 76.3 75.2 –110 MIN tbd LTC2190 TYP MAX 77.1 77 76.9 76.4 90 90 89 84 95 95 95 95 76.9 76.8 76.5 76.4 –110 UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc SFDR Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 30MHz Input 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 30MHz Input 70MHz Input 140MHz Input l tbd tbd tbd l tbd tbd tbd S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input 10MHz Input l tbd tbd tbd Crosstalk INTERNAL REFERENCE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation –400µA < IOUT < 1mA 1.7V < VDD < 1.9V –600µA < IOUT < 1mA IOUT = 0 1.225 CONDITIONS IOUT = 0 MIN The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) TYP 0.5 • VDD ±25 4 1.250 ±25 7 0.6 1.275 MAX 0.5 • VDD + 25mV UNITS V ppm/°C Ω V ppm/°C Ω mV/V 0.5 • VDD – 25mV DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC–) Differential Encode Mode (ENC– Not Tied to GND) VID VICM VIN RIN CIN VIH VIL Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage (Note 8) Internally Set Externally Set (Note 8) ENC+, ENC– to GND See Figure 10 (Note 8) VDD =1.8V VDD =1.8V l l l l l 0.2 1.1 0.2 10 3.5 1.2 0.6 1.2 1.6 3.6 V V V V kΩ pF V V 219210p Single-Ended Encode Mode (ENC– Tied to GND) 4 LTC2192 LTC2191/LTC2190 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance CONDITIONS ENC+ to GND See Figure 11 (Note 8) VDD =1.8V VDD =1.8V VIN = 0V to 3.6V (Note 8) VDD =1.8V, SDO = 0V SDO = 0V to 3.6V (Note 8) 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l l l l l l SYMBOL VIN RIN CIN VIH VIL IIN CIN ROL IOH COUT VOD VOS RTERM MIN 0 TYP 30 3.5 MAX 3.6 UNITS V kΩ pF V DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) 1.3 0.6 –10 3 200 –10 3 247 125 1.125 1.125 350 175 1.250 1.250 100 454 250 1.375 1.375 10 10 V µA pF Ω µA pF mV mV V V Ω SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used) DIGITAL DATA OUTPUTS POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) PARAMETER Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current CONDITIONS (Note 10) (Note 10) Sine Wave Input 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 4-Lane Mode, 1.75mA Mode 4-Lane Mode, 3.5mA Mode l l l SYMBOL VDD OVDD IVDD IOVDD MIN 1.7 1.7 LTC2192 TYP MAX 1.8 1.8 99 10.2 17.6 13.6 24.7 21.1 39.6 198 211 203 223 217 250 1 50 20 1.9 1.9 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd MIN 1.7 1.7 LTC2191 TYP MAX 1.8 1.8 72 9.2 16.6 12.8 23.9 20.3 38.8 146 159 152 172 166 199 1 50 20 1.9 1.9 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd MIN 1.7 1.7 LTC2190 TYP MAX 1.8 1.8 49 8.7 16.1 12.3 23.4 19.9 38.4 104 118 111 131 124 158 1 50 20 1.9 1.9 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd UNITS V V mA mA mA mA mA mA mA mW mW mW mW mW mW mW mW mW l l l l PDISS Power Dissipation l l l l PSLEEP PNAP PDIFFCLK Sleep Mode Power Nap Mode Power Power Increase with Diffential Encode Mode Enabled (No Increase for Sleep Mode) 219210p 5 LTC2192 LTC2191/LTC2190 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER Sampling Frequency CONDITIONS (Notes 10, 11) l l l l l SYMBOL fS tENCL tENCH tAP SYMBOL tSER tFRAME tDATA tPD tr tf MIN 5 7.3 2 7.3 2 LTC2192 TYP MAX 65 7.69 7.69 7.69 7.69 0 100 100 100 100 MIN 5 11.88 2 11.88 2 LTC2191 TYP MAX 40 12.5 12.5 12.5 12.5 0 TYP 1/(4 • fS) 1/(8 • fS) 1/(16 • fS) 100 100 100 100 MIN 5 19 2 19 2 LTC2190 TYP MAX 25 20 20 20 20 0 MAX 100 100 100 100 UNITS MHz ns ns ns ns ns UNITS Sec ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Sample-and-Hold Acquistion Delay Time PARAMETER Serial Data Bit Period CONDITIONS 4-Lane Output Mode 2-Lane Output Mode 1-Lane Output Mode (Note 8) (Note 8) (Note 8) Data, DCO, FR, 20% to 80% Data, DCO, FR, 20% to 80% tSER = 1ns MIN Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output) FR to DCO Delay Data to DCO Delay Propagation Delay Output Rise Time Output Fall Time DCO Cycle-Cycle Jitter Pipeline Latency l l l 0.35 • tSER 0.35 • tSER 0.7n + 2 • tSER 0.5 • tSER 0.5 • tSER 1.1n + 2 • tSER 0.17 0.17 60 7 0.65 • tSER 0.65 • tSER 1.5n + 2 • tSER Sec Sec Sec ns ns psP-P Cycles ns ns ns ns ns ns SPI Port Timing (Note 8) tSCK tS tH tDS tDH tDO SCK Period Write Mode Readback Mode, CSDO = 20pF RPULLUP = 2k , l l l l l l 40 250 5 5 5 5 125 CS-to-CLK Setup Time SCK-to-CS Setup Time SDI Setup Time SDI Hold Time SCK Falling to SDO Valid Readback Mode, CSDO = 20pF RPULLUP = 2k , l ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2192), 40MHz (LTC2191), or 25MHz (LTC2190), 2-lane output mode, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD=1.8V, fSAMPLE = 65MHz (LTC2192), 40MHz (LTC2191), or 25MHz (LTC2190), 2-lane output mode, ENC+ = single-ended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps, so tSER must be greater than or equal to 1ns. 219210p 6 LTC2192 LTC2191/LTC2190 TIMING DIAGRAMS 4-Lane Output Mode tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR+ FR– OUT#A– OUT#A+ OUT#B– OUT#B+ OUT#C– OUT#C+ OUT#D– OUT#D+ tFRAME N tENCH tENCL N+1 tDATA tSER tSER tPD D15 D13 D11 D9 D15 D13 D11 tSER D9 D15 D14 D12 D10 D8 D14 D12 D10 D8 D14 D7 D5 D3 D1 D7 D5 D3 D1 D7 D6 D4 D2 D0 D6 SAMPLE N–6 D4 D2 D0 D6 SAMPLE N–5 219210 TD01 SAMPLE N–7 2-Lane Output Mode tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 D7 D5 N tENCH tENCL N+1 tSER tFRAME tDATA tSER tPD D3 D1 D15 D13 D11 D9 D7 D5 tSER D3 D1 D15 D13 D11 SAMPLE N–7 SAMPLE N–6 SAMPLE N–5 219210 TD02 OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED 219210p 7 LTC2192 LTC2191/LTC2190 TIMING DIAGRAMS 1-Lane Output Mode ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D3 D2 tFRAME tDATA tSER tSER tAP N tENCH tENCL N+1 tPD D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 tSER D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 219210 TD03 SAMPLE N–7 SAMPLE N–6 SAMPLE N–5 OUT#B+, OUT#B–, OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED SPI Port Timing (Readback Mode) tS CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH HIGH IMPEDANCE SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE 219210 TD04 219210p 8 LTC2192 LTC2191/LTC2190 TYPICAL PERFORMANCE CHARACTERISTICS LTC2192: Integral Nonlinearity (INL) 4.0 3.0 2.0 DNL ERROR (LSB) INL ERROR (LSB) 1.0 0 –1.0 –2.0 –3.0 –4.0 0 16384 32768 49152 OUTPUT CODE 65536 219210 G01 LTC2192: Differential Nonlinearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 16384 32768 49152 OUTPUT CODE 65536 219210 G02 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2192: 64k Point FFT, fIN = 5MHz, –1dBFS, 65Msps 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –90 –100 –110 –120 0 20 10 FREQUENCY (MHz) 30 219210 G03 LTC2192: 64k Point FFT, fIN = 30MHz, –1dBFS, 65Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 –10 –20 –30 LTC2192: 64k Point FFT, fIN = 70MHz, –1dBFS, 65Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 LTC2192: 64k Point FFT, fIN = 140MHz, –1dBFS, 65Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 20 10 FREQUENCY (MHz) 30 219210 G04 0 20 10 FREQUENCY (MHz) 30 219210 G05 0 20 10 FREQUENCY (MHz) 30 219210 G06 LTC2192: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, –7dBFS, 65Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 10000 9000 8000 7000 LTC2192: Shorted Input Histogram 78 77 76 SNR (dBFS) 75 74 73 72 71 32837 32843 32849 OUTPUT CODE 32855 219210 G08 LTC2192: SNR vs Input Frequency, –1dBFS, 65Msps, 2V Range SINGLE-ENDED ENCODE 6000 5000 4000 3000 2000 1000 DIFFERENTIAL ENCODE –90 –100 –110 –120 0 20 10 FREQUENCY (MHz) 30 219210 G07 0 32831 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 219210 G09 219210p 9 LTC2192 LTC2191/LTC2190 TYPICAL PERFORMANCE CHARACTERISTICS LTC2192: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 2V Range 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 2ND 3RD 100 95 SFDR (dBc AND dBFS) 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 3RD LTC2192: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 1V Range 130 120 110 100 90 80 70 60 50 40 30 LTC2192: SFDR vs Input Level, fIN = 70MHz, 65Msps, 2V Range dBFS dBc 2ND 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 219210 G10 219210 G11 219210 G12 LTC2192: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Channel 110 45 LTC2192: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Input 78 4 LANE, 3.5mA 77 76 SNR (dBFS) 75 74 73 72 71 70 LTC2192: SNR vs SENSE, fIN = 5MHz, –1dBFS 100 35 IOVDD (mA) IVDD (mA) 90 25 2 LANE, 3.5mA 4 LANE, 1.75mA 1 LANE, 3.5mA 80 70 60 15 2 LANE, 1.75mA 1 LANE, 1.75mA 0 10 50 20 30 40 SAMPLE RATE (Msps) 60 219210 G13 5 0 20 40 60 SAMPLE RATE (Msps) 219210 G14 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 219210 G15 LTC2191: Integral Nonlinearity (INL) 4.0 3.0 2.0 DNL ERROR (LSB) INL ERROR (LSB) 1.0 0 –1.0 –2.0 –3.0 –4.0 0 16384 32768 49152 OUTPUT CODE 65536 219210 G16 LTC2191: Differential Nonlinearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 16384 32768 49152 OUTPUT CODE 65536 219210 G17 LTC2191: 64k Point FFT, fIN = 5MHz, –1dBFS, 40Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 219210 G18 219210p 10 LTC2192 LTC2191/LTC2190 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 LTC2191: 64k Point FFT, fIN = 30MHz, –1dBFS, 40Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2191: 64k Point FFT, fIN = 70MHz, –1dBFS, 40Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 LTC2191: 64k Point FFT, fIN = 140MHz, –1dBFS, 40Msps –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 219210 G19 0 5 10 15 FREQUENCY (MHz) 20 219210 G20 0 5 10 15 FREQUENCY (MHz) 20 219210 G21 LTC2191: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, –7dBFS, 40Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 10000 9000 8000 7000 LTC2191: Shorted Input Histogram 78 77 76 SNR (dBFS) 75 74 73 72 71 32829 32835 32841 OUTPUT CODE 32847 219210 G23 LTC2191: SNR vs Input Frequency, –1dBFS, 40Msps, 2V Range SINGLE-ENDED ENCODE 6000 5000 4000 3000 2000 1000 DIFFERENTIAL ENCODE –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 219210 G22 0 32823 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 219210 G24 LTC2191: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 40Msps, 2V Range 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 2ND 3RD 100 95 LTC2191: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 40Msps, 1V Range 130 120 3RD 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 LTC2191: SFDR vs Input Level, fIN = 70MHz, 40Msps, 2V Range dBFS 90 85 80 75 70 65 dBc 2ND 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 219210 G25 219210 G26 219210 G27 219210p 11 LTC2192 LTC2191/LTC2190 TYPICAL PERFORMANCE CHARACTERISTICS LTC2191: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 80 75 35 70 65 60 15 55 50 5 25 2 LANE, 3.5mA 4 LANE, 1.75mA 1 LANE, 3.5mA 2 LANE, 1.75mA 1 LANE, 1.75mA 0 10 20 30 SAMPLE RATE (Msps) 40 219210 G28 LTC2191: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Input 45 4 LANE, 3.5mA 78 77 76 SNR (dBFS) 75 74 73 72 71 40 219210 G29 LTC2191: SNR vs SENSE, fIN = 5MHz, –1dBFS IOVDD (mA) IVDD (mA) 0 20 30 10 SAMPLE RATE (Msps) 70 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 219210 G30 LTC2190: Integral Nonlinearity (INL) 4.0 3.0 2.0 DNL ERROR (LSB) INL ERROR (LSB) 1.0 0 –1.0 –2.0 –3.0 –4.0 0 16384 32768 49152 OUTPUT CODE 65536 219210 G31 LTC2190: Differential Nonlinearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 16384 32768 49152 OUTPUT CODE 65536 219210 G32 LTC2190: 64k Point FFT, fIN = 5MHz, –1dBFS, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –90 –100 –110 –120 0 5 FREQUENCY (MHz) 10 219210 G33 LTC2190: 64k Point FFT, fIN = 30MHz, –1dBFS, 25Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2190: 64k Point FFT, fIN = 70MHz, –1dBFS, 25Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 0 5 FREQUENCY (MHz) 10 219210 G35 LTC2190: 64k Point FFT, fIN = 140MHz, –1dBFS, 25Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 –90 –100 –110 –120 219210 G34 –90 –100 –110 –120 0 5 FREQUENCY (MHz) 10 0 5 FREQUENCY (MHz) 10 219210 G36 219210p 12 LTC2192 LTC2191/LTC2190 TYPICAL PERFORMANCE CHARACTERISTICS LTC2190: 64k Point, 2-Tone FFT, fIN = 69MHz, 70MHz, –7dBFS, 25Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 10000 9000 8000 7000 SNR (dBFS) 6000 5000 4000 3000 2000 1000 0 5 FREQUENCY (MHz) 10 219210 G37 LTC2190: Shorted Input Histogram 78 77 76 75 74 73 72 71 32842 32848 32854 OUTPUT CODE 32860 219210 G38 LTC2190: SNR vs Input Frequency, –1dBFS, 25Msps, 2V Range SINGLE-ENDED ENCODE DIFFERENTIAL ENCODE –90 –100 –110 –120 0 32836 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 219210 G39 LTC2190: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 25Msps, 2V Range 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 2ND 3RD 100 95 LTC2190: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 25Msps, 1V Range 130 120 3RD 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 LTC2190: SFDR vs Input Level, fIN = 70MHz, 25Msps, 2V Range 90 85 80 75 70 65 dBFS 2ND dBc 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 219210 G40 219210 G41 219210 G42 LTC2190: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 55 45 LTC2190: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave on Each Input 78 4 LANE, 3.5mA 77 76 SNR (dBFS) 75 74 73 72 71 25 219210 G44 LTC2190: SNR vs SENSE, fIN = 5MHz, –1dBFS 50 I0VDD (mA) IVDD (mA) 40 45 35 2 LANE, 3.5mA 4 LANE, 1.75mA 1 LANE, 3.5mA 2 LANE, 1.75mA 1 LANE, 1.75mA 40 20 35 0 5 15 20 10 SAMPLE RATE (Msps) 25 219210 G43 15 0 5 15 20 10 SAMPLE RATE (Msps) 70 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 219210 G45 219210p 13 LTC2192 LTC2191/LTC2190 PIN FUNCTIONS VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1µF ceramic capacitor. GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 65): ADC Power Ground. The exposed pad must be soldered to the PCB ground. AIN1+ (Pin 3): Channel 1 Positive Differential Analog Input. AIN1– (Pin 4): Channel 1 Negative Differential Analog Input. REFH (Pins 6, 8): ADC High Reference. See the Reference section in the Applications Information for recommended bypassing cIrcuits for REFH and REFL. REFL (Pins 7, 9): ADC Low Reference. See the Reference section in the Applications Information for recommended bypassing cIrcuits for REFH and REFL. PAR/SER (Pin 10): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. AIN2+ (Pin 11): Channel 2 Positive Differential Analog Input. AIN2– (Pin 12): Channel 2 Negative Differential Analog Input. VCM2 (Pin 14): Common Mode Bias Output, Nominally Equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs of channel 2. Bypass to ground with a 0.1µF ceramic capacitor. VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1µF ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC+ (Pin 17): Encode Input. Conversion starts on the rising edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 19): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS along with SCK selects 1-, 2- or 4-lane output mode (see Table 3). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 20): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK along with CS selects 1-, 2- or 4-lane output mode (see Table 3). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 21): In Serial Programming Mode, (PAR/SER = 0V), SDI is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming pode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 33): Output Driver Ground. This pin must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 34): Output Driver Supply. Bypass to ground with a 0.1µF ceramic capacitor. SDO (Pin 46): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V to 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO selects 3.5mA or 1.75mA LVDS output currents. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. 219210p 14 LTC2192 LTC2191/LTC2190 PIN FUNCTIONS VREF (Pin 48): Reference Voltage Output. Bypass to ground with a 2.2µF ceramic capacitor. The reference output is nominally 1.25V. SENSE (Pin 50): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. LVDS Outputs The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT2D–/OUT2D+, OUT2C–/OUT2C+, OUT2B–/OUT2B+, OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. In 2-Lane output mode only OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used. FR–/FR+ (Pins 31/32): Frame Start Outputs. DCO–/DCO+ (Pins 35/36): Data Clock Outputs. OUT1D–/OUT1D+, OUT1C–/OUT1C+, OUT1B–/OUT1B+, OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44): Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. In 2-lane output mode only OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used. 219210p 15 LTC2192 LTC2191/LTC2190 FUNCTIONAL BLOCK DIAGRAM 1.8V VDD ENC+ ENC– 1.8V OVDD CH1 ANALOG INPUT PLL S/H 16-BIT ADC CORE DATA SERIALIZER CH2 ANALOG INPUT S/H 16-BIT ADC CORE OUT1A OUT1B OUT1C OUT1D OUT2A OUT2B OUT2C OUT2D DATA CLOCK OUT FRAME OGND VREF 2.2µF 1.25V REFERENCE RANGE SELECT REF BUF SENSE REFH REFL DIFF REF AMP VDD/2 MODE CONTROL REGISTERS 219210 F01 REFH 2.2µF REFL VCM1 0.1µF VCM2 0.1µF PAR/SER CS SCK SDI SDO 0.1µF 0.1µF Figure 1. Functional Block Diagram 219210p 16 LTC2192 LTC2191/LTC2190 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2192/LTC2191/LTC2190 are low power, 2-channel, 16-bit, 65/40/25Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially or single ended for lower power consumption. To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs one bit at a time (1-lane mode), two bits at a time (2-lane mode) or four bits at a time (4-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-andhold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or VCM2 output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. The two channels are simultaneously sampled by a shared encode circuit (Figure 2). LTC2192 VDD 10 CPARASITIC 1.8pF RON 15 CPARASITIC 1.8pF VDD CSAMPLE 5pF RON 15 CSAMPLE 5pF Single-Ended Input For applications less sensitive to harmonic distortion, the AIN+ input can be driven singled ended with a 1VP-P signal centered around VCM. The AIN– input should be connected to VCM. With a singled-ended input the harmonic distortion and INL will degrade, but the noise and DNL will remain unchanged. INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal AIN+ VDD 10Ω AIN– 1.2V 10k ENC+ ENC– 10k 1.2V 219210 F02 Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown 219210p 17 LTC2192 LTC2191/LTC2190 APPLICATIONS INFORMATION 50 VCM 0.1µF 0.1µF ANALOG INPUT T1 1:1 25 25 25 0.1µF 12pF 25 AIN– 219210 F03 50 VCM 0.1µF AIN+ LTC2192 0.1µF ANALOG INPUT T1 0.1µF T2 25 25 0.1µF AIN+ LTC2192 1.8pF AIN– 219210 F05 T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1L RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 50 VCM 0.1µF 0.1µF ANALOG INPUT T1 0.1µF T2 25 25 12 0.1µF 8.2pF 12 AIN– 219210 F04 Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz to 250MHz 50 VCM 0.1µF 0.1µF ANALOG INPUT 4.7nH T1 0.1µF 25 25 0.1µF AIN+ LTC2192 AIN+ LTC2192 4.7nH AIN– 219210 F06 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1L RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front-End Circuit for Input Frequencies from 5MHz to 150MHz Figure 6. Recommended Front-End Circuit for Input Frequencies Above 250MHz VCM HIGH SPEED DIFFERENTIAL 0.1µF AMPLIFIER ANALOG INPUT 200 200 25 0.1µF AIN+ 12pF 0.1µF LTC2192 DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. + – 25 AIN– 12pF 219210 F07 Figure 7. Front-End Circuit Using a High Speed Differential Amplifier 219210p 18 LTC2192 LTC2191/LTC2190 APPLICATIONS INFORMATION Reference The LTC2192/LTC2191/LTC2190 have an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8. A low inductance 2.2µF interdigitated capacitor is recommended for the bypass between REFH and REFL. This type of capacitor is available at a low cost from multiple suppliers. Alternatively, C1 can be replaced by a standard 2.2µF capacitor between REFH and REFL. The capacitors should be as close to the pins as possible (not on the back side of the circuit board). LTC2192 1.25V VREF 2.2µF 5 1.25V BANDGAP REFERENCE 0.625V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE C2 0.1µF 219210 F08c Figure 8c and 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note that in Figure 8c, every pin of the interdigitated capacitor (C1) is connected since the pins are not internally connected in some vendors’ capacitors. In Figure 8d the REFH and REFL pins are connected by short jumpers in an internal layer. To minimize the inductance of these jumpers they can be placed in a small hole in the GND plane on the second board layer. C3 0.1µF C1 2.2µF C2 0.1µF REFH REFL LTC2192 REFH REFL 219210 F08b CAPACITORS ARE 0402 PACKAGE SIZE Figure 8b. Alternative REFH/REFL Bypass Circuit Figure 8c. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8a TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.625V < VSENSE < 1.300V – + C1 + – + – REFH REFL 0.8x DIFF AMP 219210 F08d – C3 0.1µF REFH REFL Figure 8d. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8b VREF + C1: 2.2µF LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLE1AX7S0G225M MURATA LLA219C70G225M AVX W2L14Z225M OR EQUIVALENT INTERNAL ADC LOW REFERENCE 219210 F08a 2.2µF 1.25V EXTERNAL REFERENCE SENSE 1µF LTC2192 219210 F09 Figure 8a. Reference Circuit Figure 9. Using an External 1.25V Reference 219210p 19 LTC2192 LTC2191/LTC2190 APPLICATIONS INFORMATION Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12, 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave LTC2192 VDD DIFFERENTIAL COMPARATOR encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. If the encode signal is turned off or drops below approximately 500kHz, the A/D enters nap mode. 0.1µF 50Ω 100Ω 0.1µF 50Ω ENC– 0.1µF T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE 219210 F12 ENC+ T1 LTC2192 Figure 12. Sinusoidal Encode Drive 0.1µF ENC+ PECL OR LVDS CLOCK LTC2192 0.1µF ENC– 219210 F13 VDD 15k ENC+ ENC– 30k Figure 13. PECL or LVDS Encode Drive Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25µs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. 219210 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode LTC2192 1.8V TO 3.3V 0V ENC+ ENC– 30k CMOS LOGIC BUFFER 219210 F11 Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode 219210p 20 LTC2192 LTC2191/LTC2190 APPLICATIONS INFORMATION DIGITAL OUTPUTS The digital outputs of the LTC2192/LTC2191/LTC2190 are serialized LVDS signals. Each channel outputs one bit at a time (1-lane mode), two bits at a time (2-lane mode) or four bits at a time (4-lane mode). Please refer to the Timing Diagrams for details. In 4-lane mode the clock duty cycle stabilizer must be enabled. The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (See Table 1). The minimum sample rate for all serialization modes is 5Msps. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits are for the LTC2192. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2191) or 25MHz (LTC2190) MAXIMUM SAMPLING SERIALIZATION FREQUENCY , DCO FR SERIAL MODE fS (MHz) FREQUENCY FREQUENCY DATA RATE 4-Lane 2-Lane 1-Lane 65 65 62.5 2 • fS 4 • fS 8 • fS fS fS fS 4 • fS 8 • fS 16 • fS Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Internal termination can only be selected in serial programming mode. DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1. Table 2. Output Codes vs Input Voltage AIN+-AIN– (2V RANGE) >1.000000V +0.999970V +0.999939V +0.000030V +0.000000V –0.000030V –0.000061V –0.999939V –1.000000V