LTC2265IUJ-12TRPBF

LTC2265-12/ LTC2264-12/LTC2263-12 12-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs FEATURES n n n n n n n n n n n n n DESCRIPTION The LTC®2265-12/LTC2264-12/LTC2263-12 are 2-channel, simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 71dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS . The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC – inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. 2-Channel Simultaneous Sampling ADC 71dB SNR 90dB SFDR Low Power: 167mW/112mW/94mW Total 83mW/56mW/47mW per Channel Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package APPLICATIONS n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 1.8V VDD CH.1 ANALOG INPUT CH.2 ANALOG INPUT ENCODE INPUT 1.8V OVDD OUT1A OUT1B DATA SERIALIZER OUT2A OUT2B DATA CLOCK OUT FRAME GND OGND 226512 TA01 LTC2265-12, 65Msps, 2-Tone FFT, fIN = 70MHz and 75MHz 0 –10 –20 AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 + S/H – + S/H – 12-BIT ADC CORE 12-BIT ADC CORE SERIALIZED LVDS OUTPUTS PLL –90 –100 –110 –120 0 20 10 FREQUENCY (MHz) 30 226512 TA02 22654312f 1 LTC2265-12/ LTC2264-12/LTC2263-12 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) PIN CONFIGURATION TOP VIEW PAR/SER OUT1A+ OUT2B – OUT1A– 30 OUT1B+ 29 OUT1B– 28 DCO+ 27 DCO– 41 GND 26 OVDD 25 OGND 24 FR+ 23 FR– 22 OUT2A+ 21 OUT2A– 11 12 13 14 15 16 17 18 19 20 ENC+ ENC– CS SCK SDI OUT2B + VDD VDD GND SENSE VREF GND GND SDO VDD AIN1 AIN1 + – Supply Voltages VDD, OVDD................................................ –0.3V to 2V Analog Input Voltage (AIN +, AIN –, PAR/SER, SENSE) (Note 3) .......................... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2265C, 2264C, 2263C ........................ 0°C to 70°C LTC2265I, 2264I, 2263I .......................–40°C to 85°C Storage Temperature Range...................–65°C to 150°C 40 39 38 37 36 35 34 33 32 31 1 2 VCM1 3 REFH 4 REFH 5 REFL 6 REFL 7 VCM2 8 AIN2+ 9 AIN2 – 10 UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN TJMAX = 150°C, θJA = 32°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2265CUJ-12#PBF LTC2265IUJ-12#PBF LTC2264CUJ-12#PBF LTC2264IUJ-12#PBF LTC2263CUJ-12#PBF LTC2263IUJ-12#PBF TAPE AND REEL LTC2265CUJ-12#TRPBF LTC2265IUJ-12#TRPBF LTC2264CUJ-12#TRPBF LTC2264IUJ-12#TRPBF LTC2263CUJ-12#TRPBF LTC2263IUJ-12#TRPBF PART MARKING* LTC2265UJ-12 LTC2265UJ-12 LTC2264UJ-12 LTC2264UJ-12 LTC2263UJ-12 LTC2263UJ-12 PACKAGE DESCRIPTION 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ VDD 22654312f 2 LTC2265-12/ LTC2264-12/LTC2263-12 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-12 PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise External Reference Internal Reference External Reference External Reference Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS l LTC2264-12 MIN 12 –1 –0.4 –12 –2.4 TYP ±0.3 ±0.1 ±3 –0.8 –0.8 ±20 ±30 ±10 ±0.2 ±3 0.32 MAX 1 0.4 12 0.6 12 –1 LTC2263-12 MIN TYP ±0.3 ±0.1 ±3 –0.8 –0.8 ±20 ±30 ±10 ±0.2 ±3 0.32 MAX 1 0.5 12 0.6 UNITS Bits LSB LSB mV %FS %FS μV/°C ppm/°C ppm/°C %FS mV LSBRMS MIN 12 –1 –0.5 –12 –2.4 TYP ±0.3 ±0.1 ±3 –0.8 –0.8 ±20 ±30 ±10 ±0.2 ±3 0.32 MAX 1 0.5 12 0.6 Differential Analog Input (Note 6) l l l l –0.5 –12 –2.4 ANALOG INPUT SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) External Reference Mode Per Pin, 65Msps Per Pin, 40Msps Per Pin, 25Msps 0 < AIN +, AIN – < VDD 0 < PAR/SER < VDD 0.625 < SENSE < 1.3V l l l l l VCM – 100mV l MIN TYP 1 to 2 VCM 1.250 81 50 31 MAX VCM + 100mV 1.300 UNITS VP-P V V μA μA μA Analog Input Range (AIN + – AIN –) Analog Input Common Mode (AIN + + AIN –)/2 External Voltage Reference Applied to SENSE Analog Input Common Mode Current 0.625 IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B Analog Input Leakage Current (No Encode) PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth –1 –3 –6 0 0.15 80 1 3 6 μA μA μA ns psRMS dB MHz Figure 6 Test Circuit 800 22654312f 3 LTC2265-12/ LTC2264-12/LTC2263-12 DYNAMIC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTC2265-12 CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input l LTC2264-12 MIN 69.7 TYP 70.9 70.8 70.8 70.5 90 90 89 84 90 90 90 90 70.8 70.7 70.6 70.2 –105 MAX LTC2263-12 MIN 69.4 TYP 70.5 70.5 70.5 70.2 90 90 89 84 90 90 90 90 70.5 70.4 70.3 69.9 –105 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc MIN 69.9 TYP 71 71 70.9 70.6 90 90 89 84 90 90 90 90 70.9 70.9 70.7 70.3 –105 MAX SFDR Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 30MHz Input 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 30MHz Input 70MHz Input 140MHz Input l 77 79 79 l 84 85 84 S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input 10MHz Input l 69.6 69.6 69.2 Crosstalk INTERNAL REFERENCE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation –400μA < IOUT < 1mA 1.7V < VDD < 1.9V –600μA < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) MIN 0.5 • VDD – 25mV TYP 0.5 • VDD ±25 4 1.225 1.250 ±25 7 0.6 1.275 MAX 0.5 • VDD + 25mV UNITS V ppm/°C Ω V ppm/°C Ω mV/V 22654312f 4 LTC2265-12/ LTC2264-12/LTC2263-12 DIGITAL INPUTS AND OUTPUTS SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN VIH VIL IIN CIN ROL IOH COUT VOD VOS RTERM Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN TYP MAX UNITS (Note 8) Internally Set Externally Set (Note 8) ENC+, ENC– to GND (See Figure 10) l l l 0.2 1.2 1.1 0.2 10 3.5 1.6 3.6 V V V V kΩ pF V 0.6 V V kΩ pF V 0.6 V μA pF Ω 10 3 μA pF 454 250 1.375 1.375 mV mV V V Ω 10 3 3.6 30 3.5 Single-Ended Encode Mode (ENC– Tied to GND) VDD = 1.8V VDD = 1.8V ENC+ to GND (See Figure 11) l l l 1.2 0 DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VDD = 1.8V VDD = 1.8V VIN = 0V to 3.6V l l l 1.3 –10 SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V l 200 –10 DIGITAL DATA OUTPUTS 247 125 1.125 1.125 350 175 1.250 1.250 100 22654312f 5 LTC2265-12/ LTC2264-12/LTC2263-12 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2265-12 SYMBOL PARAMETER VDD OVDD IVDD IOVDD CONDITIONS l l l POWER REQUIREMENTS LTC2264-12 MIN 1.7 1.7 TYP 1.8 1.8 52 10 19 15 28 112 128 121 144 1 60 20 MAX 1.9 1.9 63 1.9 1.9 98 1.7 1.7 LTC2263-12 MIN TYP 1.8 1.8 42 10 18 14 27 94 108 101 124 1 60 20 MAX 1.9 1.9 50 UNITS V V mA mA mA mA mA mW mW mW mW mW mW mW MIN 1.7 1.7 TYP 1.8 1.8 82 11 20 15 28 167 184 175 198 1 60 20 MAX Analog Supply Voltage (Note 10) Output Supply Voltage (Note 10) Analog Supply Current Sine Wave Input Digital Supply Current 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 18 31 18 31 17 31 PDISS Power Dissipation l l 209 232 146 169 121 146 PSLEEP PNAP PDIFFCLK Sleep Mode Power Nap Mode Power Power Increase with Differential Encode Mode Enabled (No Increase for Sleep Mode) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-12 SYMBOL fS tENCL tENCH tAP PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8) Sample-and-Hold Acquisition Delay Time CONDITIONS (Notes 10, 11) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l l l l TIMING CHARACTERISTICS LTC2264-12 MIN 5 11.88 2 11.88 2 12.5 12.5 12.5 12.5 0 TYP MAX 45 100 100 100 100 65 5 19 2 19 2 LTC2263-12 MIN TYP 20 20 20 20 0 MAX 25 100 100 100 100 UNITS MHz ns ns ns ns ns MIN 5 7.3 2 7.3 2 TYP 7.69 7.69 7.69 7.69 0 MAX 100 100 100 100 22654312f 6 LTC2265-12/ LTC2264-12/LTC2263-12 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER tSER Serial Data Bit Period CONDITIONS Two Lanes, 16-Bit Serialization Two Lanes, 14-Bit Serialization Two Lanes, 12-Bit Serialization One Lane, 16-Bit Serialization One Lane, 14-Bit Serialization One Lane, 12-Bit Serialization (Note 8) (Note 8) (Note 8) Data, DCO, FR, 20% to 80% Data, DCO, FR, FR, 20% to 80% tSER = 1ns l l l TIMING CHARACTERISTICS MIN TYP 1 / (8 • fS) 1 / (7 • fS) 1 / (6 • fS) 1 / (16 • fS) 1 / (14 • fS) 1 / (12 • fS) MAX UNITS s Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tFRAME tDATA tPD tR tF FR to DCO Delay DATA to DCO Delay Propagation Delay Output Rise Time Output Fall Time DCO Cycle-to-Cycle Jitter Pipeline Latency 0.35 • tSER 0.35 • tSER 0.7n + 2 • tSER 0.5 • tSER 0.5 • tSER 1.1n + 2 • tSER 0.17 0.17 60 6 0.65 • tSER 0.65 • tSER 1.5n + 2 • tSER s s s ns ns psP-P Cycles ns ns ns ns ns ns SPI Port Timing (Note 8) tSCK tS tH tDS tDH tDO SCK Period CS to SCK Set-Up Time SCK to CS Set-Up Time SDI Set-Up Time SDI Hold Time SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k Write Mode Readback Mode, CSDO = 20pF RPULLUP = 2k , l l l l l l l 40 250 5 5 5 5 125 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz (LTC2264), or 25MHz (LTC2263), 2-lane output mode, differential ENC+/ ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2265), 40MHz (LTC2264), or 25MHz (LTC2263), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire chip, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps, so tSER must be greater than or equal to 1ns. 22654312f 7 LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A – N+1 N tENCH tENCL tSER tFRAME tDATA tSER tPD D3 D1 DX* 0 D11 D9 D7 D5 D3 tSER D1 DX* 0 D11 D9 D7 OUT#A+ OUT#B– OUT#B+ D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6 226512 TD01 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 226512 TD02 N tENCH tENCL N+1 N+2 tSER tFRAME tDATA tSER tPD D5 D3 D1 DX* D11 D9 D7 D5 D3 tSER D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 22654312f 8 LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ FR+ FR– OUT#A– OUT#A+ OUT#B– OUT#B+ D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6 226512 TD03 tAP N tENCH tENCL N+1 tSER tFRAME tDATA tSER tPD D7 D5 D3 D1 D11 D9 D7 tSER D5 D3 D1 D11 D9 D7 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ DX* DY* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 tPD tFRAME tDATA tSER tSER N tENCH tENCL N+1 tSER D2 D1 D0 DX* DY* 0 0 D11 D10 D9 D8 226512 TD04 SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED SAMPLE N-5 SAMPLE N-4 *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 22654312f 9 LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 tPD tFRAME tDATA tSER tSER N tENCH tENCL N+1 tSER D2 D1 D0 DX* DY* D11 D10 D9 D8 226512 TD05 SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED SAMPLE N-5 SAMPLE N-4 *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUTA– OUTA+ D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 tPD tFRAME tDATA tSER tSER N+1 N tENCH tENCL tSER D2 D1 D0 D11 D10 D9 226512 TD06 SAMPLE N-6 OUTB+, OUTB– ARE DISABLED SAMPLE N-5 SAMPLE N-4 SPI Port Timing (Readback Mode) tS CS SCK tDO SDI SDO HIGH IMPEDANCE R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE 226512 TD07 22654312f 10 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2265-12: Integral Nonlinearity (INL) 1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 OUTPUT CODE 4096 226512 G01 LTC2265-12: Differential Nonlinearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 2048 3072 OUTPUT CODE 4096 226512 G02 LTC2265-12: 8k Point FFT, fIN = 5MHz –1dBFS, 65Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 1024 –90 –100 –110 –120 0 10 20 FREQUENCY (MHz) 30 226512 G03 LTC2265-12: 8k Point FFT, fIN = 30MHz, –1dBFS, 65Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2265-12: 8k Point FFT, fIN = 70MHz, –1dBFS, 65Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 0 20 10 FREQUENCY (MHz) 30 226512 G05 LTC2265-12: 8k Point FFT, fIN = 140MHz, –1dBFS, 65Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 FREQUENCY (MHz) 30 226512 G04 –90 –100 –110 –120 –90 –100 –110 –120 0 20 10 FREQUENCY (MHz) 30 226512 G06 LTC2265-12: 8k Point 2-Tone FFT, fIN = 68MHz, 69MHz, –1dBFS, 65Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 14000 12000 10000 8000 6000 4000 18000 16000 LTC2265-12: Shorted Input Histogram 72 71 70 SNR (dBFS) 69 68 67 2000 0 2049 66 LTC2265-12: SNR vs Input Frequency, –1dBFS, 2V Range, 65Msps –90 –100 –110 –120 0 20 10 FREQUENCY (MHz) 30 226512 G07 2050 2051 2052 OUTPUT CODE 2053 226512 G08 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 226512 G09 22654312f 11 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2265-12: SFDR vs Input Frequency, –1dBFS, 2V Range, 65Msps 95 90 SFDR (dBc AND dBFS) 85 80 75 70 65 110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 dBc dBFS SNR (dBc AND dBFS) LTC2265-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 65Msps 80 70 60 50 LTC2265-12: SNR vs Input Level, fIN = 70MHz, 2V Range, 65Msps dBFS SFDR (dBFS) dBc 40 30 20 10 0 –60 –50 –40 –30 –20 INPUT LEVEL(dBFS) –10 0 226512 G10 226512 G12 226512 G50 LTC2265-12: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 90 85 80 IOVDD (mA) IVDD (mA) 75 70 65 60 0 20 30 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS 72 2-LANE, 3.5mA 71 1-LANE, 3.5mA 2-LANE, 1.75mA SNR (dBFS) 60 226512 G51 LTC2265-12: SNR vs SENSE, fIN = 5MHz, –1dBFS 70 69 68 67 66 10 1-LANE, 1.75mA 0 10 20 30 40 50 SAMPLE RATE (Msps) 60 226512 G53 0 10 20 30 40 50 SAMPLE RATE (Msps) 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 226512 G15 LTC2264-12: Integral Nonlinearity (INL) 1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 OUTPUT CODE 4096 226512 G21 LTC2264-12: Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 3072 OUTPUT CODE 4096 226512 G22 LTC2264-12: 8k Point FFT, fIN = 5MHz, –1dBFS, 40Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 FREQUENCY (MHz) 20 226512 G23 22654312f 12 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2264-12: 8k Point FFT, fIN = 29MHz, –1dBFS, 40Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 20 226512 G25 LTC2264-12: 8k Point FFT, fIN = 69MHz, –1dBFS, 40Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2264-12: 8k Point FFT, fIN = 139MHz, –1dBFS, 40Msps –90 –100 –110 –120 0 10 FREQUENCY (MHz) 20 226512 G24 –90 –100 –110 –120 0 10 FREQUENCY (MHz) –90 –100 –110 –120 0 10 FREQUENCY (MHz) 20 226512 G26 LTC2264-12: 8k Point 2-Tone FFT, fIN = 68MHz, 69MHz, –1dBFS, 40Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 18000 16000 LTC2264-12: Shorted Input Histogram 72 71 14000 12000 10000 8000 6000 4000 67 2000 0 2049 66 SNR (dBFS) 70 69 68 LTC2264-12: SNR vs Input Frequency, –1dBFS, 2V Range, 40Msps –90 –100 –110 –120 0 10 FREQUENCY (MHz) 20 226512 G27 2050 2051 2052 OUTPUT CODE 2053 226512 G28 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 226512 G29 LTC2264-12: SFDR vs Input Frequency, –1dBFS, 2V Range, 40Msps 95 90 85 80 75 70 65 SFDR (dBc AND dBFS) 110 100 90 80 LTC2264-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 40Msps 60 dBFS 55 IVDD (mA) 0 LTC2264-12: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS SFDR (dBFS) 70 60 50 40 30 20 10 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) dBc 50 45 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 40 0 10 20 30 SAMPLE RATE (Msps) 40 226512 G54 226512 G24a 226512 G32 22654312f 13 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2264-12: SNR vs SENSE, fIN = 5MHz, –1dBFS 72 71 70 SNR (dBFS) 69 68 67 66 INL ERROR (LSB) 1.0 0.8 0.6 DNL ERROR (LSB) 0 2048 3072 OUTPUT CODE 4096 226512 G41 LTC2263-12: Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 1024 LTC2263-12: Differential Nonlinearity (DNL) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0 1024 2048 3072 OUTPUT CODE 4096 226512 G42 226512 G35 LTC2263-12: 8k Point FFT, fIN = 5MHz, –1dBFS, 25Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2263-12: 8k Point FFT, fIN = 30MHz, –1dBFS, 25Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 0 226512 G43 LTC2263-12: 8k Point FFT, fIN = 70MHz, –1dBFS, 25Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 FREQUENCY (MHz) 10 –90 –100 –110 –120 5 FREQUENCY (MHz) 10 226512 G44 –90 –100 –110 –120 0 5 FREQUENCY (MHz) 10 226512 G45 LTC2263-12: 8k Point FFT, fIN = 140MHz, –1dBFS, 25Msps 0 –10 –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2263-12: 8k Point 2-Tone FFT, fIN = 68MHz, 69MHz, –1dBFS, 25Msps 18000 16000 14000 12000 COUNT 10000 8000 6000 4000 2000 0 5 FREQUENCY (MHz) 10 226512 G47 LTC2263-12: Shorted Input Histogram –90 –100 –110 –120 0 5 FREQUENCY (MHz) 10 226512 G46 –90 –100 –110 –120 0 2049 2050 2051 2052 OUTPUT CODE 2053 226512 G48 22654312f 14 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2263-12: SNR vs Input Frequency, –1dBFS, 2V Range, 25Msps 72 71 70 SNR (dBFS) 69 68 67 66 95 90 85 80 75 70 65 SFDR (dBc AND dBFS) LTC2263-12: SFDR vs Input Frequency, –1dBFS, 2V Range, 25Msps 110 100 90 80 70 60 50 40 30 20 10 LTC2263-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 25Msps dBFS SFDR (dBFS) dBc 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 226512 G49 226512 G37 226512 G52 LTC2263-12: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS 50 72 71 45 70 SNR (dBFS) IVDD (mA) 40 69 68 35 67 30 66 LTC2263-12: SNR vs SENSE, fIN = 5MHz, –1dBFS 350 300 PEAK-TO-PEAK JITTER (ps) 250 200 150 100 50 0 0.6 0.7 0.8 0.9 1.0 1.1 SENSE PIN (V) 1.2 1.3 DCO Cycle-Cycle Jitter vs Serial Data Rate 0 5 10 15 20 SAMPLE RATE (Msps) 25 226512 G55 0 200 400 600 800 SERIAL DATA RATE (Mbps) 1000 226512 G55a 226512 G52a 22654312f 15 LTC2265-12/ LTC2264-12/LTC2263-12 PIN FUNCTIONS AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD /2. VCM should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1μF ceramic capacitor. REFH (Pins 4, 5): ADC High Reference. Bypass to pins 6, 7 with a 2.2μF ceramic capacitor, and to ground with a 0.1μF ceramic capacitor. REFL (Pins 6, 7): ADC Low Reference. Bypass to pins 4, 5 with a 2.2μF ceramic capacitor, and to ground with a 0.1μF ceramic capacitor. VCM2 (Pin 8): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channel 2. Bypass to ground with a 0.1μF ceramic capacitor. AIN2+ (Pin 9): Channel 2 Positive Differential Analog Input. AIN2– (Pin 10): Channel 2 Negative Differential Analog Input. VDD (Pins 11, 12, 39, 40): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1μF ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC+ (Pin 13): Encode Input. Conversion starts on the rising edge. ENC– (Pin 14): Encode Complement Input. Conversion starts on the falling edge. CS (Pin 15): In serial programming mode (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (Pin 16): In serial programming mode (PAR/SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 17): In serial programming mode (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (Pins 18, 33, 37, Exposed Pad Pin 41): ADC Power Ground. The exposed pad must be soldered to the PCB ground. OGND (Pin 25): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 26): Output Driver Supply, 1.7V to 1.9V. Bypass to ground with a 0.1μF ceramic capacitor. SDO (Pin 34): In serial programming mode (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pullup resistor of 1.8V to 3.3V. If readback from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In parallel programming mode (PAR/SER = VDD), SDO is an input that enables internal 100Ω termination resistors on the digital outputs. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. 22654312f 16 LTC2265-12/ LTC2264-12/LTC2263-12 PAR/SER (Pin 35): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that controls the A/D operating modes. Connect to VDD to enable parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. VREF (Pin 36): Reference Voltage Output. Bypass to ground with a 1μF ceramic capacitor, nominally 1.25V. SENSE (Pin 38): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. LVDS OUTPUTS The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT2B–/OUT2B+ , OUT2A–,OUT2A+ (Pins 19/20, 21/22): Serial Data Outputs for Channel 2. In 1-lane output mode, only OUT2A–/OUT2A+ are used. FR–/FR+ (Pin 23/Pin 24): Frame Start Output. DCO–/DCO+ (Pin 27/Pin 28): Data Clock Output. OUT1B–/OUT1B+ , OUT1A–/OUT1A+ (Pins 29/30, 31/32): Serial Data Outputs for Channel 1. In 1-lane output mode, only OUT1A–/OUT1A+ are used. 22654312f 17 LTC2265-12/ LTC2264-12/LTC2263-12 FUNCTIONAL BLOCK DIAGRAM 1.8V VDD ENC+ ENC– 1.8V OVDD CHANNEL 1 ANALOG INPUT SAMPLEAND-HOLD 12-BIT ADC CORE PLL OUT1A OUT1B DATA SERIALIZER OUT2A OUT2B CHANNEL 2 ANALOG INPUT SAMPLEAND-HOLD 12-BIT ADC CORE VREF 1μF 1.25V REFERENCE RANGE SELECT DATA CLOCK OUT FRAME SENSE REF BUF REFH REFL OGND VDD /2 DIFF REF AMP MODE CONTROL REGISTERS 226512 F01 GND REFH 0.1μF REFL VCM1 0.1μF VCM2 0.1μF PAR/SER CS SCK SDI SDO 2.2μF 0.1μF 0.1μF Figure 1. Functional Block Diagram 22654312f 18 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2265-12/LTC2264-12/LTC2263-12 are low power, 2-channel, 12-bit, 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. To minimize the number of data lines, the digital outputs are serial LVDS. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or VCM2 output pins, which are nominally VDD /2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be a 180° phase difference between the inputs. The two channels are simultaneously sampled by a shared encode circuit (Figure 2). INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching and limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. Figure 2. Equivalent Input Circuit. Only One of the Two Analog Channels Is Shown. 50Ω Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM , setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. LTC2265-12 VDD 10Ω CPARASITIC 1.8pF RON 25Ω CPARASITIC 1.8pF VDD CSAMPLE 3.5pF RON 25Ω CSAMPLE 3.5pF AIN+ VDD 10Ω AIN– 1.2V 10k ENC+ ENC– 10k 1.2V 226512 F02 VCM 0.1μF 0.1μF ANALOG INPUT T1 1:1 25Ω 25Ω 25Ω 0.1μF AIN+ LTC2265-12 12pF 25Ω AIN– 226512 F03 T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 22654312f 19 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. 50Ω VCM 0.1μF 0.1μF ANALOG INPUT T2 T1 25Ω 25Ω 0.1μF 4.7pF 0.1μF AIN– 226512 F04 At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. 50Ω VCM 0.1μF 0.1μF ANALOG INPUT 25Ω T1 0.1μF 25Ω 2.7nH AIN– 226512 F06 AIN+ LTC2265-12 2.7nH 0.1μF AIN+ LTC2265-12 T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front-End Circuit for Input Frequencies from 70MHz to 170MHz 50Ω Figure 6. Recommended Front-End Circuit for Input Frequencies Above 300MHz VCM 0.1μF HIGH SPEED DIFFERENTIAL 0.1μF AMPLIFIER LTC2265-12 1.8pF ANALOG INPUT 200Ω 200Ω 25Ω VCM 0.1μF AIN+ LTC2265-12 0.1μF ANALOG INPUT T2 T1 25Ω 25Ω 0.1μF AIN+ + – + 12pF 0.1μF AIN – – 0.1μF 25Ω AIN– 226512 F05 226512 F07 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 7. Front-End Circuit Using a High Speed Differential Amplifier Figure 5. Recommended Front-End Circuit for Input Frequencies from 170MHz to 300MHz 22654312f 20 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Reference The LTC2265-12/LTC2264-12/LTC2263-12 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE . The reference is shared by both ADC channels, so it is not possible to independently adjust the input range of individual channels. The VREF , REFH and REFL pins should be bypassed, as shown in Figure 8. The 0.1μF capacitor between REFH and REFL should be as close to the pins as possible (not on the backside of the circuit board). LTC2265-12 1.25V VREF 1μF 0.625V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH LTC2265-12 2.2μF 0.1μF 0.8x DIFF AMP 1.8V TO 3.3V 0V REFL INTERNAL ADC LOW REFERENCE 226512 F08 Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). VREF 1μF LTC2265-12 1.25V EXTERNAL REFERENCE SENSE 1μF 226512 F09 Figure 9. Using an External 1.25V Reference LTC2265-12 VDD DIFFERENTIAL COMPARATOR VDD 1.25V BANDGAP REFERENCE ENC+ ENC– 30k 5Ω 15k TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.625V < VSENSE < 1.300V 0.1μF 226512 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode ENC+ ENC– 30k CMOS LOGIC BUFFER 226512 F11 0.1μF Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode Figure 8. Reference Circuit 22654312f 21 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC – should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC – is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. DIGITAL OUTPUTS The digital outputs of the LTC2265-12/LTC2264-12/ LTC2263-12 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode) or one bit at a PECL OR LVDS CLOCK 0.1μF 0.1μF 50Ω ENC– 226512 F12 time (1-lane mode). The data can be serialized with 16-, 14-, or 12-bit serialization (see the Timing Diagrams section for details). The output data should be latched on the rising and falling edges of the data clockout (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps. 0.1μF ENC+ 50Ω 100Ω T1 LTC2265-12 0.1μF T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive 0.1μF ENC+ LTC2265-12 ENC– 226512 F13 Figure 13. PECL or LVDS Encode Drive 22654312f 22 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-12. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-12) or 25MHz (LTC2263-12). SERIALIZATION MODE 2-Lane 2-Lane 2-Lane 1-Lane 1-Lane 1-Lane 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization MAXIMUM SAMPLING FREQUENCY fS (MHz) , 65 65 65 62.5 65 65 DCO FREQUENCY 4 • fS 3.5 • fS 3 • fS 8 • fS 7 • fS 6 • fS FR FREQUENCY fS 0.5 • fS fS fS fS fS SERIAL DATA RATE 8 • fS 7 • fS 6 • fS 16 • fS 14 • fS 12 • fS By default the outputs are standard LVDS levels: a 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In parallel programming mode the SCK pin can select either 3.5mA or 1.75mA. Optional LVDS Driver Internal Termination In most cases, using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In parallel programming mode the SDO pin enables internal termination. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes. DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1. In addition to the 12 data bits (D11 - D0), two additional bits (DX and DY) are sent out in the 14-bit and 16-bit serialization modes. These extra bits are to ensure complete software compatibility with the 14-bit versions of these A/Ds. During normal operation when the analog inputs are not overranged, DX and DY are always logic 0. When the analog inputs are overranged positive, DX and DY become logic 1. When the analog inputs are overranged negative, DX and DY become logic 0. DX and DY can also be controlled by the digital output test pattern. See the Timing Diagrams section for more information. Table 2. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V –0.000488V –0.000976V –0.999512V –1.000000V ≤–1.000000V D11-D0 (OFFSET BINARY) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D11-D0 (2’s COMPLEMENT) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000 DX, DY 11 00 00 00 00 00 00 00 00 00 22654312f 23 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted amplitude. The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1. Digital Output Test Pattern To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D11-D0, DX, DY) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2’s complement and randomizer. Output Disable The digital outputs may be disabled by serially programming mode control register A2. The current drive for all digital outputs, including DCO and FR, are disabled to save power or enable in-circuit testing. When disabled, the common mode of each output pair becomes high impedance, but the differential impedance may remain low. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire chip is powered down, resulting in 1mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF , REFH and REFL. For the suggested values in Figure 8, the A/D will stabilize after 2ms. SDI In nap mode any combination of A/D channels can be powered down while the internal reference circuits and the PLL stay active, allowing faster wake-up than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands a very accurate DC settling, then an additional 50μs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by the mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2265-12/LTC2264-12/ LTC2263-12 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO. Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD) PIN CS DESCRIPTION 2-Lane/1-Lane Selection Bit 0 = 2-Lane, 16-Bit Serialization Output Mode 1 = 1-Lane, 14-Bit Serialization Output Mode SCK LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode SDO Internal Termination Selection Bit 0 = Internal Termination Disabled 1 = Internal Termination Enabled 22654312f 24 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6: Table 4. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 RESET Bit 7 RESET D6 X D5 X Software Reset Bit D4 X D3 X D2 X D1 X D0 X A0) will be read back on the SDO pin (see the Timing Diagrams section). During a readback command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and readback is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero. 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This Bit Is Automatically Set Back to Zero After the Reset Is Complete Bits 6-0 Unused, Don’t Care Bits. REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h) D7 DCSOFF Bit 7 D6 RAND D5 TWOSCOMP D4 SLEEP D3 NAP_2 D2 X D1 X D0 NAP_1 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended. RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format SLEEP: NAP_2: NAP_1 Sleep/Nap Mode Control Bits 000 = Normal Operation 0X1 = Channel 1 in Nap Mode 01X = Channel 2 in Nap Mode 1XX = Sleep Mode. Both Channels are disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. Unused, Don’t Care Bit 22654312f Bit 6 Bit 5 Bits 4, 3, 0 Bits 1, 2 25 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 ILVDS2 Bits 7-5 D6 ILVDS1 D5 ILVDS0 D4 TERMON D3 OUTOFF D2 OUTMODE2 D1 OUTMODE1 D0 OUTMODE0 ILVDS2: ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes. OUTOFF Output Disable Bit 0 = Digital Outputs are enabled. 1 = Digital Outputs are disabled. OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization Bit 4 Bit 3 Bits 2-0 REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 OUTTEST Bit 7 D6 X D5 TP11 D4 TP10 D3 TP9 D2 TP8 D1 TP7 D0 TP6 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Unused, Don’t Care Bit. TP11:TP6 Test Pattern Data Bits (MSB) TP11:TP6 Set the Test Pattern for Data Bit 11 (MSB) Through Data Bit 6. Bit 6 Bits 5-0 REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 TP5 Bits 7-2 Bits 1-0 D6 TP4 D5 TP3 D4 TP2 D3 TP1 D2 TP0 D1 TPX D0 TPY TP5:TP0 Test Pattern Data Bits (LSB) TP5:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB). TPX:TPY Set the Test Pattern for Extra Bits DX and DY. These Bits are for Compatibility with the 14-Bit Version of the A/D. 22654312f 26 LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION GROUNDING AND BYPASSING The LTC2265-12/LTC2264-12/LTC2263-12 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD , OVDD , VCM , VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The larger 2.2μF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2265-12/LTC2264-12/ LTC2263-12 is transferred from the die through the bottom-side Exposed Pad and package leads onto the printed circuit board. For good electrical and thermal performance, the Exposed Pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. 22654312f 27 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL APPLICATIONS Silkscreen Top Top Side Inner Layer 2 GND Inner Layer 3 22654312f 28 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom 22654312f 29 LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL APPLICATIONS LTC2265 Schematic C4 1μF SENSE VDD C5 1μF PAR/SER SDO 40 39 38 37 36 35 34 33 32 31 SENSE VDD VDD GND PAR/SER SDO VREF GND OUT1A+ OUT1A– AIN1 DIGITAL OUTPUTS OUT1B+ OUT1B– DCO+ DCO– LTC2265 OVDD OGND FR+ FR– OUT2A+ OUT2B– OUT2B+ OUT2A– 30 29 28 27 26 25 24 23 22 21 C16 0.1μF OVDD AIN1 C29 0.1μF 1 2 3 4 5 AIN1+ AIN1 – VCM1 REFH REFH REFL REFL VCM2 AIN2+ AIN2 – C2 0.1μF C3 0.1μF C1 2.2μF C30 0.1μF 6 7 8 C59 0.1μF AIN2 AIN2 9 10 ENC+ ENC– GND SCK VDD VDD SDI CS 11 12 13 14 15 16 17 18 19 20 VDD C7 0.1μF DIGITAL OUTPUTS C47 0.1μF ENCODE CLOCK C46 0.1μF SPI BUS ENCODE CLOCK 226512 TA03 22654312f 30 LTC2265-12/ LTC2264-12/LTC2263-12 PACKAGE DESCRIPTION UJ Package 40-Lead (6mm × 6mm) Plastic QFN (Reference LTC DWG # 05-08-1728) 0.70 0.05 5.10 4.42 0.05 4.50 0.05 (4 SIDES) 6.50 0.05 0.05 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 1 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 2 0.10 PIN 1 TOP MARK (SEE NOTE 6) 4.50 REF (4-SIDES) 4.42 0.10 4.42 0.10 (UJ40) QFN REV Ø 0406 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 BOTTOM VIEW—EXPOSED PAD 0.05 0.50 BSC 22654312f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2265-12/ LTC2264-12/LTC2263-12 RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps LTC2172-14 1.8V Quad ADCs, Ultralow Power LTC2170-12/LTC2171-12/ 12-Bit, 25Msps/40Msps/65Msps LTC2172-12 1.8V Quad ADCs, Ultralow Power LTC2173-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2175-14 1.8V Quad ADCs, Ultralow Power LTC2173-12/LTC2174-12/ 12-Bit, 80Msps/105Msps/125Msps LTC2175-12 1.8V Quad ADCs, Ultralow Power LTC2256-14/LTC2257-14/ 14-Bit, 25Msps/40Msps/65Msps LTC2258-14 1.8V ADCs, Ultralow Power LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2261-14 1.8V ADCs, Ultralow Power LTC2262-14 COMMENTS 178mW/234mW/360mW, 73.4dB SNR, 88dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 178mW/234mW/360mW, 70.5dB SNR, 88dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 373mW/445mW/551mW, 73.2 dB SNR, 88dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 412mW/481mW/567mW, 70.5dB SNR, 88dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 35mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 94mW/113mW/169mW, 74dB SNR, 88dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 216mW/250mW/293mW, 73.4dB SNR, 88dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 216mW/250mW/293mW, 70.5dB SNR, 88dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Operation, Integrated Transformer High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm × 4mm QFN-20 LTC2263-14/LTC2264-14/ 14-Bit, 25Msps/40Msps/65Msps LTC2265-14 1.8V Dual ADCs, Ultralow Power LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2268-14 1.8V Dual ADCs, Ultralow Power LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps LTC2268-12 1.8V Dual ADCs, Ultralow Power RF Mixers/Demodulators LTC5517 LTC5527 LTC5557 LTC5575 Amplifiers/Filters LTC6412 LTC6420-20 LTC6421-20 LTC6605-7/LTC6605-10/ LTC6605-14 Signal Chain Receivers LTM9002 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers 40MHz to 900MHz Direct Conversion Quadrature Demodulator 400MHz to 3.7GHz High Linearity Downconverting Mixer 400MHz to 3.8GHz High Linearity Downconverting Mixer 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator Dual Matched 7MHz/10MHz/14MHz Filters Dual Matched 2nd Order Lowpass Filters with Differential Drivers, with ADC Drivers Pin-Programmable Gain, 6mm × 3mm DFN-22 14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers Subsystem 22654312f 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0110 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010