Electrical Specifications Subject to Change
LTC2268-14/ LTC2267-14/LTC2266-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs FEATURES
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DESCRIPTION
The LTC®2268-14/LTC2267-14/LTC2266-14 are 2-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2 LSBRMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
2-Channel Simultaneous Sampling ADC 73.4dB SNR 88dB SFDR Low Power: 299mW/243mW/203mW Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Pin Compatible 14-Bit and 12-Bit Versions 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
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Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V VDD CH.1 ANALOG INPUT CH.2 ANALOG INPUT ENCODE INPUT 14-BIT ADC CORE DATA SERIALIZER 1.8V OVDD OUT1A AMPLITUDE (dBFS) OUT1B OUT2A OUT2B DATA CLOCK OUT FRAME GND OGND
226814 TA01
LTC2268-14, 125Msps, 2-Tone FFT, f IN = 70MHz and 75MHz
0 –10 –20 –30 –40 –50 –60 –70 –80 SERIALIZED LVDS OUTPUTS
S/H
S/H
14-BIT ADC CORE
PLL
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60
226814 TA01b
22687614p
1
LTC2268-14/ LTC2267-14/LTC2266-14 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW PAR/SER OUT1A+
–
Supply Voltages VDD, OVDD................................................ –0.3V to 2V Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE) (Note 3) .............–0.3V to (VDD+0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................ –0.3V to 3.9V Digital Output Voltage .................. –0.3V to (OVDD+0.3V) Operating Temperature Range LTC2268C, 2267C, 2266C ........................ 0°C to 70°C LTC2268I, 2267I, 2266I ....................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C
40 39 38 37 36 35 34 33 32 31 AIN1+ 1 AIN1– 2 VCM1 3 REFH 4 REFH 5 REFL 6 REFL 7 VCM2 8 AIN2+ 9 AIN2
–
OUT1A– 30 OUT1B+ 29 OUT1B– 28 DCO+ 27 DCO– 26 OVDD 25 OGND 24 FR+ 23 FR– 22 OUT2A+ 21 OUT2A– OUT2B +
SENSE
VREF
GND
41
10 11 12 13 14 15 16 17 18 19 20 ENC+ ENC– CS SCK VDD VDD SDI GND OUT2B
UJ PACKAGE 40-LEAD (6mm 6mm) PLASTIC QFN TJMAX = 150°C, θJA = 32°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2268CUJ-14#PBF LTC2268IUJ-14#PBF LTC2267CUJ-14#PBF LTC2267IUJ-14#PBF LTC2266CUJ-14#PBF LTC2266IUJ-14#PBF TAPE AND REEL LTC2268CUJ-14#TRPBF LTC2268IUJ-14#TRPBF LTC2267CUJ-14#TRPBF LTC2267IUJ-14#TRPBF LTC2266CUJ-14#TRPBF LTC2266IUJ-14#TRPBF PART MARKING* LTC2268UJ-14 LTC2268UJ-14 LTC2267UJ-14 LTC2267UJ-14 LTC2266UJ-14 LTC2266UJ-14 PACKAGE DESCRIPTION 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
GND
SDO
VDD
VDD
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LTC2268-14/ LTC2267-14/LTC2266-14 CONVERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise External Reference Internal Reference External Reference External Reference Differential Analog Input (Note 6) Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2268-14 MIN 14 ±1 ±0.3 ±2 ±1.5 ±0.4 ±20 ±30 ±10 ±0.3 ±2 1.2 3.75 0.9 15 1.5 TYP MAX MIN 14 –3.75 –0.9 –15 –1.5 ±1 ±0.3 ±2 ±1.5 ±0.4 ±20 ±30 ±10 ±0.3 ±2 1.2 3.75 0.9 15 1.5 LTC2267-14 TYP MAX MIN 14 –3.5 –0.9 –15 –1.5 ±1 ±0.3 ±2 ±1.5 ±0.4 ±20 ±30 ±10 ±0.3 ±2 1.2 3.5 0.9 15 1.5 LTC2266-14 TYP MAX UNITS Bits LSB LSB mV %FS %FS μV/°C ppm/°C ppm/°C %FS mV LSBRMS
l –3.75 l l l
–0.9 –15 –1.5
ANALOG INPUT
SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) External Reference Mode Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps 0 < AIN+, AIN– < VDD 0 < PAR/SER < VDD 0.625 < SENSE < 1.3V
l l l l
MIN VCM – 100mV 0.625
TYP 1 to 2 VCM 1.25 155 130 100
MAX VCM +100mV 1.3
UNITS VP–P V V μA μA μA
Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ – AIN–)/2 External Voltage Reference Applied to SENSE Analog Input Common Mode Current
IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B
Analog Input Leakage Current (No Encode) PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth
l l l
–1 –3 –6 0 0.15 80
1 3 6
μA μA μA ns psRMS dB MHz
Figure 6 Test Circuit
800
22687614p
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LTC2268-14/ LTC2267-14/LTC2266-14 DIGITAL ACCURACY
SYMBOL PARAMETER SNR Signal-to-Noise Ratio
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2268-14 CONDITIONS 5MHz Input 70MHz Input 140MHz Input 5MHz Input 70MHz Input 140MHz Input 5MHz Input 70MHz Input 140MHz Input 5MHz Input 70MHz Input 140MHz Input 10MHz Input
l
LTC2267-14 MIN 71.3 TYP 73.4 73.2 72.7 88 85 82 90 90 90 73 72.6 72 –105 MAX
LTC2266-14 MIN 70.9 TYP 73.1 72.9 72.4 88 85 82 90 90 90 72.9 72.6 72 –105 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc
MIN 71.3
TYP 73.4 73.2 72.7 88 85 82 90 90 90 73 72.6 72 –105
MAX
SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher
l
76
76
79
l
85
83
85
S/(N+D)
Signal-to-Noise Plus Distortion Ratio Crosstalk
l
70.2
70.2
70.4
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation –400μA < IOUT < 1mA 1.7V < VDD < 1.9V –600μA < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
MIN 0.5 • VDD – 25mV TYP 0.5 • VDD ±25 4 1.225 1.25 ±25 7 0.6 1.275 MAX 0.VDD + 25mV UNITS V ppm/°C Ω V ppm/°C Ω mV/V
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC–) DIFFERENTIAL ENCODE MODE (ENC– NOT TIED TO GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance VDD =1.8V VDD =1.8V ENC+ to GND (Note 8) CONDITIONS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
MIN TYP MAX UNITS
l l l
0.2 1.2 1.1 0.2 10 3.5 1.6 3.6
V V V V kΩ pF V 0.6 V V kΩ pF
22687614p
Internally Set Externally Set (Note 8) ENC+, ENC– to GND (See Figure 10)
SINGLE-ENDED ENCODE MODE (ENC– TIED TO GND)
l l l
1.2 0 30 3.5 3.6
(See Figure 11)
4
LTC2268-14/ LTC2267-14/LTC2266-14 DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN ROL IOH COUT VOD VOS RTERM High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode Termination Enabled, OVDD =1.8V
l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
CONDITIONS VDD =1.8V VDD =1.8V VIN = 0V to 3.6V
l l l
MIN 1.3
TYP
MAX
UNITS V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) 0.6 –10 3 VDD =1.8V, SDO = 0V SDO = 0V to 3.6V
l
V μA pF Ω
10
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) 200 –10 3 247 125 1.125 1.125 350 175 1.25 1.25 100 454 250 1.375 1.375 10 μA pF mV mV V V Ω
DIGITAL DATA OUTPUTS
POWER REQUIREMENTS
SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS PSLEEP PNAP CONDITIONS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2268-14 MIN
l l l l l l l
LTC2267-14 MIN 1.7 1.7 TYP 1.8 1.8 119 16 29 243 266 1 70 20 MAX 1.9 1.9 TBD TBD TBD TBD TBD MIN 1.7 1.7 1.9 1.9 TBD TBD TBD TBD TBD
LTC2266-14 TYP 1.8 1.8 98 15 29 203 229 1 70 20 MAX 1.9 1.9 TBD TBD TBD TBD TBD UNITS V V mA mA mA mW mW mW mW mW
TYP 1.8 1.8 150 16 30 299 324 1 70 20
MAX
Analog Supply Voltage (Note 10) Output Supply Voltage (Note 10) Analog Supply Current Sine Wave Input Digital Supply Current Power Dissipation Sleep Mode Power Nap Mode Power 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode
1.7 1.7
PDIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Sleep Mode)
TIMING CHARACTERISTICS
SYMBOL PARAMETER fS tENCL tENCH tAP Sampling Frequency ENC Low Time (Note 8) Analog Supply Current Sample-and-Hold Acquisition Delay Time CONDITIONS (Notes 10, 11)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2268-14 MIN
l l l l l
LTC2267-14 MIN 5 4.52 2 4.52 2 4.76 4.76 4.76 4.76 0 TYP MAX 105 100 100 100 100 MIN 5 125
LTC2266-14 TYP 6.25 6.25 6.25 6.25 0 MAX 80 100 100 100 100 UNITS MHz ns ns ns ns ns
TYP 4 4 4 4 0
MAX 100 100 100 100
5 3.8 2 3.8 2
Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
5.93 2 5.93 2
22687614p
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LTC2268-14/ LTC2267-14/LTC2266-14 ELECTRICAL CHARACTERISTICS
SYMBOL tSER PARAMETER Serial Data Bit Period CONDITIONS 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization (Note 8) (Note 8) (Note 8) Data, DCO, FR, 20% to 80% Data, DCO, FR, 20% to 80% tSER = 1ns
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
MIN TYP 1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) 0.35 • tSER 0.35 • tSER 0.7n + 2 • tSER 0.5 • tSER 0.5 • tSER 1.1n + 2 • tSER 0.17 0.17 60 6 Write Mode Readback Mode, CSDO = 20pF RPULLUP = 2k ,
l l l l l l l
MAX
UNITS s
DIGITAL DATA OUTPUTS (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tFRAME tDATA tPD tR tF
FR to DCO Delay DATA to DCO Delay Propagation Delay Output Rise Time Output Fall Time DCO Cycle-Cycle Jitter Pipeline Latency
0.65 • tSER 0.65 • tSER 1.5n + 2 • tSER
s s s ns ns psP-P Cycles ns ns ns ns ns ns
SPI PORT TIMING (Note 8) tSCK tS tH tDS tDH tDO SCK Period CS to SCK Setup Time SCK to CS Setup Time SDI Setup Time SDI Hold Time SCK falling to SDO Valid Readback Mode, CSDO = 20pF RPULLUP = 2k , 40 250 5 5 5 5 125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2268), 105MHz (LTC2267), or 80MHz (LTC2266), 2-lane output mode, differential ENC+/ ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2268), 105MHz (LTC2267), or 80MHz (LTC2266), 2-lane output mode, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, unless otherwise noted. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
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LTC2268-14/ LTC2267-14/LTC2266-14 TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization*
tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 D5 D3 D1 0 D13 D11 D9 D7 D5 tFRAME tDATA tSER tSER N tENCH tENCL N+1
tPD
tSER D3 D1 0 D13 D11 D9
SAMPLE N-6 *SEE THE DIGITAL OUTPUTS SECTION
SAMPLE N-5
SAMPLE N-4
226814 TD01
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ OUT#B– OUT#B+ D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D7 D5 D3 D1 D13 D11 D9 D7 D5 tFRAME tDATA tSER tSER N tENCH tENCL N+1 N+2
tPD
tSER D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
SAMPLE N-3
226814 TD02
NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
22687614p
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LTC2268-14/ LTC2267-14/LTC2266-14 TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
tAP N tENCH ENC– ENC+ DCO– DCO+ FR+ FR– OUT#A– OUT#A+ OUT#B– OUT#B+ D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 D9 D7 D5 D3 D13 D11 D9 tFRAME tDATA tSER tSER tENCL N+1
ANALOG INPUT
tPD
tSER D7 D5 D3 D13 D11 D9
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
226814 TD03
1-Lane Output Mode, 16-Bit Serialization
tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D1 D0 0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 tPD tFRAME tDATA tSER tSER N tENCH tENCL
N+1
tSER D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10
SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED
SAMPLE N-5
SAMPLE N-4
226814 TD04
22687614p
8
LTC2268-14/ LTC2267-14/LTC2266-14 TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 tPD tFRAME tDATA tSER tSER N tENCH tENCL N+1
tSER D4 D3 D2 D1 D0 D13 D12 D11 D10
SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED
SAMPLE N-5
SAMPLE N-4
226814 TD05
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG INPUT ENC– ENC+ DCO– DCO+ FR– FR+ OUT#A– OUT#A+ D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 tPD tFRAME tDATA tSER tSER N+1 N tENCH tENCL
tSER D4 D3 D2 D13 D12 D11
SAMPLE N-6 OUT#B+, OUT#B– ARE DISABLED
SAMPLE N-5
SAMPLE N-4
226814 TD06
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LTC2268-14/ LTC2267-14/LTC2266-14 TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tS CS SCK tDO SDI SDO HIGH IMPEDANCE R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH
SPI Port Timing (Write Mode)
CS SCK
SDI SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
226814 TD07
22687614p
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LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2268-14: Integral Nonlinearity (INL)
2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384
226814 G01
LTC2268-14: Differential Nonlinearity (DNL)
1.0 0.8 0.6 AMPLITUDE (dBFS) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 16384
226814 G02
LTC2268-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 125Msps
0 –10 –20 –30 –40 –50 –60 –70 –80
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60
226814 G03
LTC2268-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 125Msps
0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80
LTC2268-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 125Msps
0 –10 –20 –30 AMPLITUDE (dBFS) 0 20 30 40 FREQUENCY (MHz) 50 60
226814 G05
LTC2268-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 125Msps
–40 –50 –60 –70 –80
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60
226814 G04
–90 –100 –110 –120 10
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60
226814 G06
LTC2268-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 125Msps
0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 4000 5000 6000
LTC2268-14: Shorted Input Histogram
74 73 72 SNR (dBFS) 71 70 69 68 1000 0 8178 67 8180 8182 8184 OUTPUT CODE 8186
226814 G08
LTC2268-14: SNR vs Input Frequency, –1dB, 2V Range, 125Msps
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60
226814 G07
COUNT
3000 2000
66
0
50
100 150 200 250 300 INPUT FREQUENCY (MHz)
350
226814 G09
22687614p
11
LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2268-14: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps
95 90 SFDR (dBc AND dBFS) 85 80 75 70 65 110 100 90 SNR (dBc AND dBFS) 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 10 0 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 dBc 60 dBc 50 40 30 20 dBFS 70
LTC2268-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps
80
LTC2268-14: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps
dBFS
SFDR (dBFS)
226814 G10
226814 G12
226814 G50a
LTC2268-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB
160 150 30
IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB
74 2-LANE, 3.5mA 1-LANE, 3.5mA 73 72 SNR (dBFS) 125
226814 G51
LTC2268-14: SNR vs SENSE, fIN = 5MHz, –1dB
140 130 120 110 100 IOVDD (mA) IVDD (mA)
20
71 70 69 68 67
2-LANE, 1.75mA 10 1-LANE, 1.75mA
0
25
50 75 100 SAMPLE RATE (Msps)
125
226814 G53
0
0
25
50 75 100 SAMPLE RATE (Msps)
66
0.6
0.7
0.8
0.9 1 1.1 SENSE PIN (V)
1.2
1.3
226814 G15
LTC2267-14: Integral Nonlinearity (INL)
2.0 1.5 1.0 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384
226814 G21
LTC2267-14: Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE 16384
226814 G22
LTC2267-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 105Msps
0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50
226814 G23
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LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2267-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 105Msps
0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 20 30 40 FREQUENCY (MHz) 50
226814 G25
LTC2267-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 105Msps
0 –10 –20 –30 –40 –50 –60 –70 –80
LTC2267-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 105Msps
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50
226814 G24
–90 –100 –110 –120 10
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50
226814 G26
LTC2267-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 105Msps
0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 4000 5000 6000
LTC2267-14: Shorted Input Histogram
74 73 72 SNR (dBFS) 71 70 69 68 1000 0 8195 67 8197 8199 8201 OUTPUT CODE 8203
226814 G28
LTC2267-14: SNR vs Input Frequency, –1dB, 2V Range, 105Msps
–90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50
226814 G27
COUNT
3000 2000
66
0
50
100 150 200 250 300 INPUT FREQUENCY (MHz)
350
226814 G29
LTC2267-14: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps
95 90 85 80 75 70 65 SFDR (dBc AND dBFS) 110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350
LTC2267-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps
130 dBFS 120
LTC2267-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB
SFDR (dBFS)
dBc
IVDD (mA)
110
100
90
0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS)
80 0
0
25 50 75 SAMPLE RATE (Msps)
100
226814 G54
226814 G30
226814 G32
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LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2267-14: SNR vs SENSE, fIN = 5MHz, –1dB
74 73 72 INL ERROR (LSB) SNR (dBFS) 71 70 69 68 67 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 12288 OUTPUT CODE 16384
226814 G41
LTC2266-14: Integral Nonlinearity (INL)
1.0 0.8 0.6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0
LTC2266-14: Differential Nonlinearity (DNL)
0
4096
8192 12288 OUTPUT CODE
16384
226814 G42
226814 G35
LTC2266-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 80Msps
0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80
LTC2266-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 80Msps
0 –10 –20 –30 AMPLITUDE (dBFS) 0 20 30 FREQUENCY (MHz) 40
226814 G44
LTC2266-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 80Msps
–40 –50 –60 –70 –80
–90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40
226814 G43
–90 –100 –110 –120 10
–90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40
226814 G45
LTC2266-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 80Msps
0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 –10 –20 –30 –40 –50 –60 –70 –80
LTC2266-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 80Msps
6000 5000 4000 COUNT 0 3000 2000 1000
LTC2266-14: Shorted Input Histogram
–90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40
226814 G46
–90 –100 –110 –120 10 20 30 FREQUENCY (MHz) 40
226814 G47
0 8184
8186
8188 8190 OUTPUT CODE
8192
226814 G48
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LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2266-14: SNR vs Input Frequency, –1dB, 2V Range, 80Msps
74 73 72 SFDR (dBFS) SNR (dBFS) 71 70 69 68 67 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 70 65 85 80 75 95 90 SFDR (dBc AND dBFS)
LTC2266-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps
110 100 90 80 70 60 50 40 30 20 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350
LTC2266-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps
dBFS
dBc
0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS)
0
226814 G49
226814 G50
226814 G52
LTC2266-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB
110 74 73 100 SNR (dBFS) IVDD (mA) 72 71 70 69 68 67 70 0 20 40 60 SAMPLE RATE (Msps) 80
226814 G55a
LTC2266-14: SNR vs SENSE, fIN = 5MHz, –1dB
350 300 PEAK-TO-PEAK JITTER (ps) 250 200 150 100 50 0 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3
DCO Cycle-Cycle Jitter vs Serial Data Rate
90
80
66
0
200 400 600 800 SERIAL DATA RATE (Mbps)
1000
226814 G55
226814 G52a
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LTC2268-14/ LTC2267-14/LTC2266-14 PIN FUNCTIONS
AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1μF ceramic capacitor. REFH (Pins 4,5): ADC High Reference. Bypass to pins 6, 7 with a 2.2μF ceramic capacitor and to ground with a 0.1μF ceramic capacitor. REFL (Pins 6,7): ADC Low Reference. Bypass to pins 4, 5 with a 2.2μF ceramic capacitor and to ground with a 0.1μF ceramic capacitor. VCM2 (Pin 8): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channel 2. Bypass to ground with a 0.1μF ceramic capacitor. AIN2+ (Pin 9): Channel 2 Positive Differential Analog Input. AIN2– (Pin 10): Channel 2 Negative Differential Analog Input. VDD (Pins 11, 12, 39, 40): 1.8V Analog Power Supply. Bypass to ground with 0.1μF ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC+ (Pin 13): Encode Input. Conversion starts on the rising edge. ENC– (Pin 14): Encode Complement Input. Conversion starts on the falling edge. CS (Pin 15): In serial programming mode, (PAR/SER=0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (Pin 16): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER= VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 17): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (Pins 18, 33, 37): ADC Power Ground. OGND (Pin 25): Output Driver Ground. OVDD (Pin 26): Output Driver Supply. Bypass to ground with a 0.1μF ceramic capacitor. SDO (Pin 34): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO is an input that enables internal 100Ω termination resistors on the digital outputs. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. PAR/SER (Pin 35): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal.
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LTC2268-14/ LTC2267-14/LTC2266-14 PIN FUNCTIONS
VREF (Pin 36): Reference Voltage Output. Bypass to ground with a 1μF ceramic capacitor, nominally 1.25V. SENSE (Pin 38): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. EXPOSED PAD (Pin 41): Ground. The Exposed Pad must be soldered to the PCB ground. LVDS Outputs All pins below are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT2B–/OUT2B+, OUT2A–/OUT2A+ (Pins 19/20, 21/22): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. FR–/FR+ (Pins 23/24): Frame Start Outputs. DCO–/DCO+ (Pins 27/28): Data Clock Outputs. OUT1B–/OUT1B+, OUT1A–/OUT1A+ (Pins 29/30, 31/32): Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used.
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LTC2268-14/ LTC2267-14/LTC2266-14 BLOCK DIAGRAM
1.8V ENC+ ENC– VDD OVDD 1.8V
PLL OUT1A CHANNEL 1 ANALOG INPUT SAMPLEAND-HOLD 14-BIT ADC CORE OUT1B
DATA SERIALIZER CHANNEL 2 ANALOG INPUT SAMPLEAND-HOLD 14-BIT ADC CORE
OUT2A OUT2B
VREF 1μF
1.25V REFERENCE RANGE SELECT
DATA CLOCKOUT FRAME
OGND
SENSE
REF BUF
REFH
REFL
VDD /2 DIFF REF AMP MODE CONTROL REGISTERS
226814 F01
GND
REFH
0.1μF
REFL
VCM1 0.1μF
VCM2 0.1μF PAR/SER CS SCK SDI SDO
2.2μF
0.1μF
0.1μF
Figure 1. Functional Block Diagram
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
CONVERTER OPERATION The LTC2268-14/LTC2267-14/LTC2266-14 are low power, 2-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single ended for lower power consumption. To minimize the number of data lines the digital outputs are serial LVDS. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port.
LTC2268-14 VDD 10Ω CPARASITIC 1.8pF RON 25Ω CPARASITIC 1.8pF VDD CSAMPLE 3.5pF RON 25Ω
ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or VCM2 output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. The two channels are simultaneously sampled by a shared encode circuit (Figure 2). INPUT DRIVE CIRCUITS Input filtering
CSAMPLE 3.5pF
AIN+
VDD 10Ω
AIN–
If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency.
50Ω VCM 0.1μF
1.2V 10k ENC+ ENC– 10k 1.2V
226814 F02
0.1μF ANALOG INPUT
T1 1:1 25Ω 25Ω
25Ω 0.1μF
AIN+ LTC2268-14 12pF
25Ω
AIN–
226814 F03
T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 2. Equivalent Input Circuit. Only One of the Two Analog Channels is Shown
Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion.
50Ω VCM 0.1μF 0.1μF ANALOG INPUT T2 T1 25Ω 25Ω 0.1μF 4.7pF 0.1μF AIN–
226814 F04
Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D.
50Ω VCM 0.1μF 0.1μF ANALOG INPUT 25Ω T1 0.1μF 25Ω 2.7nH AIN–
226814 F06
AIN+ LTC2268-14
2.7nH 0.1μF
AIN+ LTC2268-14
T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4.Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz
T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 6. Recommended Front End Circuit for Input Frequencies Above 300MHz
50Ω VCM 0.1μF 0.1μF ANALOG INPUT T2 T1 25Ω 25Ω 0.1μF 1.8pF 0.1μF AIN–
226814 F05
AIN+ LTC2268-14 HIGH SPEED DIFFERENTIAL 0.1μF AMPLIFIER ANALOG INPUT 200Ω 200Ω 25Ω
VCM 0.1μF AIN+ LTC2268-14
+ –
+
12pF
–
0.1μF
T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
25Ω
AIN–
226814 F07
Figure 5. Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz
Figure 7. Front End Circuit Using a High Speed Differential Amplifier
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
Reference The LTC2268-14/LTC2267-14/LTC2266-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE.
LTC2268-14 1.25V VREF 1μF 0.625V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH ENC+ ENC– 30k 15k VDD 5Ω 1.25V BANDGAP REFERENCE
The reference is shared by both ADC channels, so it is not possible to independently adjust the input range of individual channels. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8. The 0.1μF capacitor between REFH and REFL should be as close to the pins as possible (not on the backside of the circuit board). Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals — do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11).
LTC2268-14
TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.65V < VSENSE < 1.300V 0.1μF
VDD DIFFERENTIAL COMPARATOR
2.2μF
0.1μF
0.8x DIFF AMP
0.1μF REFL INTERNAL ADC LOW REFERENCE
226814 F08 226814 F10
Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode
Figure 8. Reference Circuit
LTC2268-14 1.8V TO 3.3V 0V LTC2268-14 1.25V EXTERNAL REFERENCE SENSE
226814 F11
VREF 1μF
ENC+ ENC– 30k CMOS LOGIC BUFFER
1μF
226814 F09
Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode
Figure 9. Using an External 1.25V Reference
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times.
0.1μF T1 50Ω 100Ω 0.1μF 50Ω ENC–
226814 F12
Clock PLL and Duty Cycle Stabilizer The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25μs to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. DIGITAL OUTPUTS The digital outputs of the LTC2268-14/LTC2267-14/ LTC2266-14 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16-, 14-, or 12-bit serialization (see Timing Diagrams for details). Note that with 12-bit serialization the two LSBs are not available — this mode is included for compatibility with the 12-bit versions of these parts. The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps.
ENC+
LTC2268-14
0.1μF
T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
0.1μF
ENC+
PECL OR LVDS CLOCK
LTC2268-14 0.1μF ENC–
226814 F13
Figure 13. PECL or LVDS Encode Drive
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2268-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2267-14) or 80MHz (LTC2266-14).
SERIALIZATION MODE 2-Lane 2-Lane 2-Lane 1-Lane 1-Lane 1-Lane 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization 16-Bit Serialization 14-Bit Serialization 12-Bit Serialization MAXIMUM SAMPLING FREQUENCY fS (MHz) , 125 125 125 62.5 71.4 83.3 DCO FREQUENCY 4 • fS 3.5 • fS 3 • fS 8 • fS 7 • fS 6 • fS FR FREQUENCY fS 0.5 • fS fS fS fS fS SERIAL DATA RATE 8 • fS 7 • fS 6 • fS 16 • fS 14 • fS 12 • fS
By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode the SCK pin can select either 3.5mA or 1.75mA. Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the Parallel Programming Mode, the SDO pin enables internal termination.
DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1.
Table 2. Output Codes vs Input Voltage
AIN+ – AIN– (2V RANGE) >1.000000V +0.999878V +0.999756V +0.000122V +0.000000V –0.000122V –0.000244V –0.999878V –1.000000V ≤–1.000000V D13-D0 (OFFSET BINARY) 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 D13-D0 (2’s COMPLEMENT) 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000
Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude.
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1. Digital Output Test Pattern To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D13-D0) of both channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2’s complement and randomizer. Output Disable The digital outputs may be disabled by serially programming mode control register A2. The current drive for all digital outputs including DCO and FR are disabled to save power or enable in-circuit testing. When disabled the common mode of each output pair becomes high impedance, but the differential impedance may remain low. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire chip is powered down, resulting in 1mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL. For the suggested values in Figure 8, the A/D will stabilize after 2ms. In nap mode any combination of A/D channels can be powered down while the internal reference circuits and the PLL stay active, allowing faster wake-up than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50μs should be allowed so the on-chip references can settle from the slight temperature
SCK
shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2268-14/LTC2267-14/ LTC2266-14 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN CS DESCRIPTION 2-Lane/1-Lane Selection Bit 0 = 2-Lane, 16-Bit Serialization Output Mode 1 = 1-Lane, 14-Bit Serialization Output Mode LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode SDI Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode SDO Internal 100Ω Termination Selection Bit 0 = Internal Termination Disabled 1 = Internal Termination Enabled
Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents.
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LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6: A0) will be read back on the SDO pin (see the Timing Diagrams section). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 RESET Bit 7 RESET D6 X D5 X Software Reset Bit D4 X D3 X D2 X D1 X D0 X
0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This Bit Is Automatically Set Back to Zero After the Reset Is Complete Bits 6-0 Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 DCSOFF Bit 7 D6 RAND D5 TWOSCOMP D4 SLEEP D3 NAP_2 D2 X D1 X D0 NAP_1
DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended. RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format SLEEP:NAP_2:NAP_1 Sleep/Nap Mode Control Bits 000 = Normal Operation 0X1 = Channel 1 in Nap Mode 01X = Channel 2 in Nap Mode 1XX = Sleep Mode. Both Channels Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. Unused, Don’t Care Bits.
Bit 6
Bit 5
Bits 4,3,0
Bits 2,1
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25
LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 ILVDS2 Bits 7-5 D6 ILVDS1 D5 ILVDS0 D4 TERMON D3 OUTOFF D2 OUTMODE2 D1 OUTMODE1 D0 OUTMODE0
ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0 OUTOFF Output Disable Bit 0 = Digital Outputs are enabled. 1 = Digital Outputs are disabled. OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization
Bit 4
Bit 3
Bits 2-0
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 OUTTEST Bit 7 D6 X D5 TP13 D4 TP12 D3 TP11 D2 TP10 D1 TP9 D0 TP8
OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Unused, Don’t Care Bit. TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.
Bit 6 Bits 5-0
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 TP7 Bits 7-0 D6 TP6 D5 TP5 D4 TP4 D3 TP3 D2 TP2 D1 TP1 D0 TP0
TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
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26
LTC2268-14/ LTC2267-14/LTC2266-14 APPLICATIONS INFORMATION
GROUNDING AND BYPASSING The LTC2268-14/LTC2267-14/LTC2266-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The larger 2.2μF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2268-14/LTC2267-14/ LTC2266-14 is transferred from the die through the bottom-side Exposed Pad and package leads onto the printed circuit board. For good electrical and thermal performance, the Exposed Pad must be soldered to a large grounded pad on the PC board.
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27
LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL APPLICATIONS
Silkscreen Top Top Side
Inner Layer 2 GND
Inner Layer 3
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28
LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL APPLICATIONS
Inner Layer 4 Inner Layer 5 Power
Bottom Side
Silkscreen Bottom
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29
LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL APPLICATIONS
LTC2268 Schematic
PAR/SER C4 1μF SENSE C5 1μF SDO
40 39 38 37 36 35 34 33 32 31 VDD VDD SENSE GND VREF OUT1A+ PAR/SER OUT1A– SDO GND AIN1 R8 100 AIN1 C29 0.1μF 1 2 3 4 5 C2 0.1μF C3 0.1μF C59 0.1μF AIN2 AIN2 VDD C7 0.1μF R92 100 C1 2.2μF C30 0.1μF 6 7 8 9 10 AIN1+ AIN1– VCM1 REFH REFH REFL REFL VCM2 AIN2+ OUT2B– OUT2B+ AIN2– ENC+ ENC– GND SCK VDD VDD SDI CS LTC2268 DIGITAL OUTPUTS OUT1B+ OUT1B– DCO+ DCO– OVDD OGND FR+ FR– OUT2A+ OUT2A– 30 29 28 27 26 25 24 23 22 21 C16 0.1μF OVDD
11 12 13 14 15 16 17 18 19 20
DIGITAL OUTPUTS
C47 0.1μF ENCODE CLOCK
C46 0.1μF
SPI BUS
ENCODE CLOCK
226814 TA03
22687614p
30
LTC2268-14/ LTC2267-14/LTC2266-14 PACKAGE DESCRIPTION
UJ Package 40-Lead (6mm × 6mm) Plastic QFN
(Reference LTC DWG # 05-08-1728)
0.70
0.05
5.10 4.42 0.05 4.50 0.05 (4 SIDES)
6.50 0.05
0.05
4.42
0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10 (4 SIDES)
0.75
0.05 R = 0.10 TYP
R = 0.115 TYP
39 40 0.40 1 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 2 0.10
PIN 1 TOP MARK (SEE NOTE 6)
4.50 REF (4-SIDES)
4.42
0.10
4.42
0.10
(UJ40) QFN REV Ø 0406
0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 BOTTOM VIEW—EXPOSED PAD
0.05
0.50 BSC
22687614p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2268-14/ LTC2267-14/LTC2266-14 RELATED PARTS
PART NUMBER ADCs LTC2170-14/LTC2171-14/ LTC2172-14 LTC2170-12/LTC2171-12/ LTC2172-12 LTC2173-12/LTC2174-12/ LTC2175-12 LTC2202/LTC2203 LTC2204/LTC2205 LTC2205-14/LTC2206-14/ LTC2207-14 LTC2206/LTC2207 LTC2208 LTC2208-14 LTC2209 LTC2215/LTC2216/ LTC2217 LTC2240-12/LTC2241-12/ LTC2242-12 LTC2256-14/LTC2257-14/ LTC2258-14 LTC2259-14/LTC2260-14/ LTC2261-14 LTC2262-14 LTC2263-14/LTC2264-14/ LTC2265-14 LTC2263-12/LTC2264-12/ LTC2265-12 LTC2266-12/LTC2267-12/ LTC2268-12 LTC2284/LTC2285 LTC2295/LTC2296/ LTC2297 LTC2298/LTC2299 DESCRIPTION 14-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 12-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 12-Bit, 80Msps/105Msps/125Msps 1.8V Quad ADCs, Ultralow Power 16-Bit, 10Msps/25Msps 3.3V ADCs 16-Bit, 40Msps/65Msps 3.3V ADCs 14-Bit, 65Msps/80Msps/105Msps 3.3V ADCs 16-Bit, 80Msps/105Msps 3.3V ADCs 16-Bit, 130Msps 3.3V ADC 14-Bit, 130Msps 3.3V ADC 16-Bit, 160Msps 3.3V ADC 16-Bit, 65Msps/80Msps/105Msps 3.3V Low Noise ADCs 12-Bit, 170Msps/210Msps/250Msps 2.5V ADCs 14-Bit, 25Msps/40Msps/65Msps 1.8V ADCs, Ultralow Power 14-Bit, 80Msps/105Msps/125Msps 1.8V ADCs, Ultralow Power 14-Bit, 150Msps 1.8V ADC, Ultralow Power 14-Bit, 25Msps/40Msps/65Msps 1.8V Dual ADCs, Ultralow Power 12-Bit, 25Msps/40Msps/65Msps 1.8V Dual ADCs, Ultralow Power 12-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 14-Bit, 105Msps/125Msps 3V Dual ADCs 14-Bit, 10Msps/25Msps/40Msps 3V Dual ADCs 14-Bit, 65Msps/80Msps 3V Dual ADCs COMMENTS 178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 178mW/234mW/360mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 412mW/481mW/567mW, 70.5 dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 140mW/220mW, 81.6dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 480mW/590mW, 79dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 597mW/762mW/947mW, 78.3dB/77.3dB/77.3dB SNR, 98dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 725mW/900mW, 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 1250mW, 77.7dB SNR, 100dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 1320mW, 77.1dB SNR, 98dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 1450mW, 77.1dB SNR, 100dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 700mW/970mW/1190mW, 81.5dB/81.3dB/81.2dB SNR, 100dB SFDR, LVDS Outputs, 9mm × 9mm QFN-64 445mW/585mW/740mW, 65.5dB SNR, 80dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 35mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-36 99mW/126mW/191mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 99mW/126mW/191mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-36 540mW/790mW, 72.4dB SNR, 88dB SFDR, CMOS Outputs, 9mm × 9mm QFN-64 120mW/150mW/235mW, 74.4dB SNR, 90dB SFDR, CMOS Outputs, 9mm × 9mm QFN-64 400mW/444mW, 74.3dB/73.0dB SNR, 90dB SFDR, CMOS Outputs, 9mm × 9mm QFN-64 High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Operation, Integrated Transformer High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm × 3mm DFN-22
22687614p LT 0709 • PRINTED IN USA
RF Mixers/Demodulators LTC5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator LTC5527 400MHz to 3.7GHz High Linearity Downconverting Mixer LTC5557 400MHz to 3.8GHz High Linearity Downconverting Mixer LTC5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator Amplifiers/Filters LTC6416 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF LTC6421-20 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers LTC6605-7/ LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Filters LTC6605-14 with ADC Drivers
32 Linear Technology Corporation
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