LTC2289

LTC2289 Dual 10-Bit, 80Msps Low Noise 3V ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Integrated Dual 10-Bit ADCs Sample Rate: 80Msps Single 3V Supply (2.7V to 3.4V) Low Power: 422mW 61.6dB SNR at 70MHz Input 85dB SFDR at 70MHz Input 110dB Channel Isolation at 100MHz Multiplexed or Separate Data Bus Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit) 80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit) 65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit) 40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit) 25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit) 64-Pin (9mm × 9mm) QFN Package The LTC®2289 is a 10-bit 80Msps, low noise 3V dual A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2289 is perfect for demanding imaging and communications applications with AC performance that includes 61.6dB SNR and 85dB SFDR for signals well beyond the Nyquist frequency. DC specs include ±0.1LSB INL (typ), ±0.1LSB DNL (typ) and ±0.6LSB INL, ±0.5LSB DNL over temperature. The transition noise is a low 0.08LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation TYPICAL APPLICATIO + ANALOG INPUT A INPUT S/H 10-BIT PIPELINED ADC CORE OVDD OUTPUT DRIVERS D9A • • • – D0A OGND SNR (dBFS) CLK A CLOCK/DUTY CYCLE CONTROL MUX CLOCK/DUTY CYCLE CONTROL OVDD CLK B + ANALOG INPUT B INPUT S/H – 10-BIT PIPELINED ADC CORE OUTPUT DRIVERS D9B • • • D0B OGND 2289 TA01 U SNR vs Input Frequency, –1dB, 2V Range, 80Msps 65 64 63 62 61 60 59 58 57 56 55 0 100 50 150 INPUT FREQUENCY (MHz) 200 2289 TA02 U U 2289fa 1 LTC2289 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2289C ............................................... 0°C to 70°C LTC2289I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AINA+ 1 AINA– 2 REFHA 3 REFHA 4 REFLA 5 REFLA 6 VDD 7 CLKA 8 CLKB 9 VDD 10 REFLB 11 REFLB 12 REFHB 13 REFHB 14 AINB– 15 AINB+ 16 64 GND 63 VDD 62 SENSEA 61 VCMA 60 MODE 59 SHDNA 58 OEA 57 OFA 56 DA9 55 DA8 54 DA7 53 DA6 52 DA5 51 DA4 50 OGND 49 OVDD 65 48 DA3 47 DA2 46 DA1 45 DA0 44 NC 43 NC 42 NC 41 NC 40 OFB 39 DB9 38 DB8 37 DB7 36 DB6 35 DB5 34 DB4 33 DB3 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2289CUP LTC2289IUP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● GND 17 VDD 18 SENSEB 19 VCMB 20 MUX 21 SHDNB 22 OEB 23 NC 24 NC 25 NC 26 NC 27 DB0 28 DB1 29 DB2 30 OGND 31 OVDD 32 QFN PART* MARKING LTC2289UP TYP MAX UNITS Bits 10 –0.6 –0.5 –12 –2.5 ±0.1 ±0.1 ±2 ±0.5 ±10 ±30 ±5 ±0.3 ±2 0.08 0.6 0.5 12 2.5 Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference External Reference SENSE = 1V ● ● ● ● mV %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS 2289fa 2 U LSB LSB W U U WW W U LTC2289 A ALOG I PUT SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 2.7V < VDD < 3.4V (Note 7) +AIN –)/2 Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ Analog Input Leakage Current SENSEA, SENSEB Input Leakage MODE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input 40MHz Input 70MHz Input 140MHz Input ● SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic SFDR Spurious Free Dynamic Range 4th Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio IMD Intermodulation Distortion Crosstalk U WU U MIN ● ● ● ● ● ● TYP ±0.5 to ±1 1.5 1.5 MAX 1.9 2 1 3 3 UNITS V V V µA µA µA ns psRMS dB MHz Differential Input (Note 7) Single Ended Input (Note 7) 0V < AIN+, AIN– < VDD 0V < SENSEA, SENSEB < 1V 0V < MODE < VDD 1 0.5 –1 –3 –3 0 0.2 80 Figure 8 Test Circuit 575 MIN 60 TYP 61.6 61.6 61.6 61.6 85 MAX UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 5MHz Input 40MHz Input 70MHz Input 140MHz Input 5MHz Input 40MHz Input 70MHz Input 140MHz Input 5MHz Input 40MHz Input 70MHz Input 140MHz Input fIN = 40MHz, 41MHz fIN = 100MHz ● ● ● 69 85 85 80 85 74 85 85 85 61.6 60 61.6 61.6 61.5 85 –110 2289fa 3 LTC2289 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 2.7V < VDD < 3.4V –1mA < IOUT < 1mA CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V LOGIC INPUTS (CLK, OE, SHDN, MUX) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● ● ● 4 U U U U U (Note 4) MIN 1.475 TYP 1.500 ±25 3 4 MAX 1.525 UNITS V ppm/°C mV/V Ω TYP MAX UNITS V 2 0.8 –10 3 10 V µA pF VIN = 0V to VDD (Note 7) OE = High (Note 7) VOUT = 0V VOUT = 3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA ● ● 3 50 50 2.7 2.995 2.99 0.005 0.09 2.49 0.09 1.79 0.09 0.4 pF mA mA V V V V V V V V 2289fa LTC2289 POWER REQUIRE E TS SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power (Each Channel) Nap Mode Power (Each Channel) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) CONDITIONS (Note 9) (Note 9) Both ADCs at fS(MAX) Both ADCs at fS(MAX) SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fs tL tH tAP tD tMD PARAMETER Sampling Frequency CLK Low Time CLK High Time Sample-and-Hold Aperture Delay CLK to DATA Delay MUX to DATA Delay Data Access Time After OE↓ BUS Relinquish Time Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential drive, unless otherwise noted. CL = 5pF (Note 7) CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7) ● ● ● ● TI I G CHARACTERISTICS UW MIN 2.7 0.5 TYP 3 3 141 422 2 15 MAX 3.4 3.6 165 495 UNITS V V mA mW mW mW UW CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● ● ● ● MIN 1 5.9 5 5.9 5 1.4 1.4 TYP 6.25 6.25 6.25 6.25 0 2.7 2.7 4.3 3.3 5 MAX 80 500 500 500 500 5.4 5.4 10 8.5 UNITS MHz ns ns ns ns ns ns ns ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 and 11 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with differential drive. The supply current and power dissipation are the sum total for both channels with both channels active. Note 9: Recommended operating conditions. 2289fa 5 LTC2289 TYPICAL PERFOR A CE CHARACTERISTICS Crosstalk vs Input Frequency –100 –105 1.0 0.8 0.6 –110 –115 –120 –125 –130 0 20 40 60 80 INPUT FREQUENCY (MHz) 100 2289 G01 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 256 512 CODE 768 1024 2289 G02 DNL ERROR (LSB) CROSSTALK (dB) INL ERROR (LSB) 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 80Msps 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 –50 –60 –70 –80 –90 –100 –110 –120 AMPLITUDE (dB) –40 5 10 15 20 25 30 FREQUENCY (MHz) 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 80Msps 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 –60 –70 –80 –90 –100 –110 –120 COUNT 6 UW 35 Typical INL, 2V Range, 80Msps 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 Typical DNL, 2V Range, 80Msps 0.4 0 256 512 CODE 768 1024 2289 G03 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 80Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 –120 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 80Msps –40 40 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 2289 G04 2289 G05 2289 G06 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range 0 –10 –20 –30 –40 –50 120000 100000 80000 60000 40000 20000 0 140000 Grounded Input Histogram, 80Msps 131072 0 510 511 CODE 0 512 2289 G09 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 2289 G07 2289 G08 2289fa LTC2289 TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Frequency, –1dB, 2V Range, 80Msps 65 64 63 SNR AND SFDR (dBFS) 62 61 60 59 58 57 56 55 0 100 50 150 INPUT FREQUENCY (MHz) 200 2289 G10 SFDR (dBFS) SNR (dBFS) SNR and SFDR vs Clock Duty Cycle, 80Msps 90 SFDR: DCS ON 85 SNR AND SFDR (dBFS) 80 SFDR: DCS OFF 75 70 65 SNR: DCS ON 60 55 30 35 40 60 CLOCK DUTY CYCLE (%) 45 50 55 65 70 SNR: DCS OFF SNR (dBc AND dBFS) 70 60 50 40 30 20 10 80 SFDR (dBc AND dBFS) IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 165 155 IOVDD (mA) IVDD (mA) 145 2V RANGE 135 1V RANGE 125 115 105 95 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2289 G16 UW 2289 G13 SFDR vs Input Frequency, –1dB, 2V Range, 80Msps 100 95 90 90 85 80 75 70 65 0 50 150 INPUT FREQUENCY (MHz) 100 200 2289 G11 SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 SFDR 80 70 SNR 60 50 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps) 2289 G12 SNR vs Input Level, fIN = 70MHz, 2V Range, 80Msps 90 80 dBFS SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps dBFS 70 60 50 40 30 20 10 –40 –10 –20 INPUT LEVEL (dBFS) –30 0 2289 G14 dBc dBc 0 –50 0 –50 –40 –20 –30 INPUT LEVEL (dBFS) –10 0 2289 G15 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 14 12 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (Msps) 2289 G17 2289fa 7 LTC2289 PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge. CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge. REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. AINB– (Pin 15): Channel B Negative Differential Analog Input. AINB+ (Pin 16): Channel B Positive Differential Analog Input. GND (Pins 17, 64): ADC Power Ground. SENSEB (Pin 19): Channel B Reference Programming Pin. Connecting SENSEB to VCMB selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of ±VSENSEB. ±1V is the largest valid input range. VCMB (Pin 20): Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMA. MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA9, OFA; Channel B comes out on DB0-DB9, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB9, OFB; Channel B comes out on DA0-DA9, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs at high impedance. OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function. NC (Pins 24 to 27, 41 to 44): Do Not Connect These Pins. DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital Outputs. DB9 is the MSB. OGND (Pins 31, 50): Output Driver Ground. OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred. DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital Outputs. DA9 is the MSB. OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred. OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA pin function. 2289fa 8 U U U LTC2289 PI FU CTIO S SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance. MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. VCMA (Pin 61): Channel A 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMB. SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to VCMA selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEA selects an input range of ±VSENSEA. ±1V is the largest valid input range. GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground. FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE AIN– VCM 2.2µF 1.5V REFERENCE RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFH 0.1µF 2.2µF 1µ F Figure 1. Functional Block Diagram (Only One Channel is Shown) 2289fa W U U U U U THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION REFL INTERNAL CLOCK SIGNALS OVDD OF CLOCK/DUTY CYCLE CONTROL D9 CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFL CLK MODE SHDN OE 2289 F01 OGND 1µF 9 LTC2289 TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP ANALOG INPUT N N+1 tH CLK tD D0-D9, OF N–5 N–4 N–3 N–2 N–1 N 2289 TD01 ANALOG INPUT A ANALOG INPUT B CLKA = CLKB = MUX D0A-D9A, OFA D0B-D9B, OFB 10 W UW N+2 N+3 N+4 N+5 tL Multiplexed Digital Output Bus Timing tAPA A A+1 tAPB B B+1 tH tL B+2 B+3 B+4 A+2 A+3 A+4 A–5 tD B–5 B–5 A–4 B–4 t MD A–3 B–3 A–2 B–2 A–1 A–5 B–4 A–4 B–3 A–3 B–2 A–2 B–1 2289 TD02 2289fa LTC2289 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log ( √(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, Aperture Delay Time The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) Crosstalk Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal). CONVERTER OPERATION As shown in Figure 1, the LTC2289 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive U 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. 2289fa W UU 11 LTC2289 APPLICATIO S I FOR ATIO applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2289 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the LTC2289 VDD 15Ω CPARASITIC 1pF CSAMPLE 4pF CPARASITIC 1pF VDD CLK CSAMPLE 4pF AIN+ VDD 15Ω AIN– Figure 2. Equivalent Input Circuit 2289fa 12 U third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2289 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from 2289 F02 W U U LTC2289 APPLICATIO S I FOR ATIO high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2289 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may U degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2289 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 25Ω 0.1µF 12pF AIN– 2289 F03 W UU AIN+ LTC2289 Figure 3. Single-Ended to Differential Conversion Using a Transformer Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. 2289fa 13 LTC2289 APPLICATIO S I FOR ATIO VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT 2.2µF AIN+ 0.1µF LTC2289 ANALOG INPUT T1 0.1µF 25Ω 12Ω 25Ω 12Ω 0.1µF 8pF AIN– 2289 F06 + CM + 12pF – – 25Ω AIN– 2289 F04 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. VCM 1k 1k 25Ω 2.2µF AIN+ LTC2289 0.1µF ANALOG INPUT 12pF 25Ω 0.1µF AIN– 2289 F05 Figure 5. Single-Ended Drive The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. 14 U VCM 2.2µF AIN+ LTC2289 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE W UU Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2289 F07 AIN+ 25Ω 0.1µF LTC2289 Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz VCM 2.2µF 0.1µF ANALOG INPUT T1 0.1µF 25Ω 6.8nH – 2289 F08 6.8nH 25Ω 0.1µF AIN+ LTC2289 AIN T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz 2289fa LTC2289 APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2289 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (± 0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. LTC2289 1.5V VCM 2.2µF 4Ω 1.5V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 0.5V 1.5V VCM 2.2µF LTC2289 SENSE 1µF TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µF 2.2µF 1µF 0.1µF DIFF AMP REFL INTERNAL ADC LOW REFERENCE 2289 F09 Figure 9. Equivalent Reference Circuit U The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges. Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB. 12k 0.75V 12k 2289 F10 W UU Figure 10. 1.5V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 0.7dB. See the Typical Performance Characteristics section. Driving the Clock Input The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 11). 2289fa 15 LTC2289 APPLICATIO S I FOR ATIO 4.7µF FERRITE BEAD 0.1µF SINUSOIDAL CLOCK INPUT 0.1µF 1k CLK 50Ω 1k NC7SVU04 CLEAN SUPPLY LTC2289 100Ω Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2289 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. Figures 12 and 13 show alternative for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. 16 U 4.7µF FERRITE BEAD 0.1µF CLEAN SUPPLY CLK LTC2289 2289 F11 2289 F12 W UU IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter ETC1-1T 5pF-30pF DIFFERENTIAL CLOCK INPUT CLK LTC2289 2289 F13 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer The transformer shown in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2289 is 80Msps. For the ADC to operate properly, the CLK signal should 2289fa LTC2289 APPLICATIO S I FOR ATIO have a 50% (±5%) duty cycle. Each half cycle must have at least 5.9ns for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels. The lower limit of the LTC2289 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2289 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) >+1.000000V +0.998047V +0.996094V +0.001953V 0.000000V –0.001953V –0.003906V –0.998047V –1.000000V 70MHz 1 A0 2 A1 3 A2 4 A3 8 VCC 7 WP 6 SCL 5 SDA R38 SDA 2289 AI01 U C14 0.1µF W 4 • •3 R7 24.9Ω RN1D 33Ω RN2A 33Ω RN2B 33Ω RN2C 33Ω RN2D 33Ω U E1 EXT REF A EXT REF 5 6 C44 0.1µF U 20 VCC JP1 MODE VDD 1 2 4 R1 1k 3 2/3VDD VDD JP2 SENSEA VDD 1 VDD 2 2289fa LTC2289 APPLICATIO S I FOR ATIO U Silkscreen Top Top Side 2289fa W U U 21 LTC2289 APPLICATIO S I FOR ATIO Inner Layer 2 GND 22 U Inner Layer 3 Power Bottom Side 2289fa W U U LTC2289 PACKAGE DESCRIPTIO 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP PIN 1 TOP MARK (SEE NOTE 5) 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ± 0.05 7.15 ± 0.05 8.10 ± 0.05 9.50 ± 0.05 (4 SIDES) PACKAGE OUTLINE 63 64 0.40 ± 0.10 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.200 REF 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD (UP64) QFN 1003 2289fa 23 LTC2289 RELATED PARTS PART NUMBER LTC2220 LTC2221 LTC2222 LTC2223 LTC2224 LTC2225 LTC2226 LTC2227 LTC2228 LTC2230 LTC2231 LTC2232 LTC2233 LTC2245 LTC2246 LTC2247 LTC2248 LTC2249 LTC2286 LTC2287 LTC2288 LTC2290 LTC2291 LTC2292 LTC2293 LTC2294 LTC2295 LTC2296 LTC2297 LTC2298 LTC2299 DESCRIPTION 12-Bit, 170Msps ADC 12-Bit, 135Msps ADC 12-Bit, 105Msps ADC 12-Bit, 80Msps ADC 12-Bit, 135Msps ADC 12-Bit, 10Msps ADC 12-Bit, 25Msps ADC 12-Bit, 40Msps ADC 12-Bit, 65Msps ADC 10-Bit, 170Msps ADC 10-Bit, 135Msps ADC 10-Bit, 105Msps ADC 10-Bit, 80Msps ADC 14-Bit, 10Msps ADC 14-Bit, 25Msps ADC 14-Bit, 40Msps ADC 14-Bit, 65Msps ADC 14-Bit, 80Msps ADC 10-Bit, Dual, 25Msps ADC 10-Bit, Dual, 40Msps ADC 10-Bit, Dual, 65Msps ADC 12-Bit, Dual, 10Msps ADC 12-Bit, Dual, 25Msps ADC 12-Bit, Dual, 40Msps ADC 12-Bit, Dual, 65Msps ADC 12-Bit, Dual, 80Msps ADC 14-Bit, Dual, 10Msps ADC 14-Bit, Dual, 25Msps ADC 14-Bit, Dual, 40Msps ADC 14-Bit, Dual, 65Msps ADC 14-Bit, Dual, 80Msps ADC COMMENTS 890mW, 67.5dB SNR, 9mm × 9mm QFN Package 630mW, 67.5dB SNR, 9mm × 9mm QFN Package 475mW, 67.9dB SNR, 7mm × 7mm QFN Package 366mW, 68dB SNR, 7mm × 7mm QFN Package 630mW, 67.5dB SNR, 7mm × 7mm QFN Package 60mW, 71.4dB SNR, 5mm × 5mm QFN Package 75mW, 71.4dB SNR, 5mm × 5mm QFN Package 120mW, 71.4dB SNR, 5mm × 5mm QFN Package 205mW, 71.3dB SNR, 5mm × 5mm QFN Package 890mW, 67.5dB SNR, 9mm × 9mm QFN Package 630mW, 67.5dB SNR, 9mm × 9mm QFN Package 475mW, 61.3dB SNR, 7mm × 7mm QFN Package 366mW, 61.3dB SNR, 7mm × 7mm QFN Package 60mW, 74.4dB SNR, 5mm × 5mm QFN Package 75mW, 74.5dB SNR, 5mm × 5mm QFN Package 120mW, 74.4dB SNR, 5mm × 5mm QFN Package 205mW, 74.3dB SNR, 5mm × 5mm QFN Package 222mW, 73dB SNR, 5mm × 5mm QFN Package 150mW, 61.8dB SNR, 9mm × 9mm QFN Package 235mW, 61.8dB SNR, 9mm × 9mm QFN Package 400mW, 61.8dB SNR, 9mm × 9mm QFN Package 120mW, 71.3dB SNR, 9mm × 9mm QFN Package 150mW, 74.5dB SNR, 9mm × 9mm QFN Package 235mW, 74.4dB SNR, 9mm × 9mm QFN Package 400mW, 74.3dB SNR, 9mm × 9mm QFN Package 422mW, 70.6dB SNR, 9mm × 9mm QFN Package 120mW, 74.4dB SNR, 9mm × 9mm QFN Package 150mW, 74.5dB SNR, 9mm × 9mm QFN Package 235mW, 74.4dB SNR, 9mm × 9mm QFN Package 400mW, 74.3dB SNR, 9mm × 9mm QFN Package 444mW, 73dB SNR, 9mm × 9mm QFN Package 2289fa 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● RD/LT 0106 REV A • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005