LTC2293UP

LTC2293/LTC2292/LTC2291 Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Integrated Dual 12-Bit ADCs Sample Rate: 65Msps/40Msps/25Msps Single 3V Supply (2.7V to 3.4V) Low Power: 400mW/235mW/150mW 71dB SNR up to 70MHz Input 85dB SFDR up to 70MHz Input 110dB Channel Isolation at 100MHz Multiplexed or Separate Data Bus Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) 10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) 64-Pin (9mm × 9mm) QFN Package Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation The LTC®2293/LTC2292/LTC2291 are 12-bit 65Msps/ 40Msps/25Msps, low power dual 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2293/LTC2292/LTC2291 are perfect for demanding imaging and communications applications with AC performance that includes 71dB SNR and 85dB SFDR for signals well beyond the Nyquist frequency. DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. An optional multiplexer allows both channels to share a digital output bus. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ TYPICAL APPLICATIO + ANALOG INPUT A INPUT S/H OVDD 12-BIT PIPELINED ADC CORE OUTPUT DRIVERS D11A • • • – D0A OGND MUX CLK B CLOCK/DUTY CYCLE CONTROL SNR (dBFS) CLK A CLOCK/DUTY CYCLE CONTROL OVDD + ANALOG INPUT B INPUT S/H – 12-BIT PIPELINED ADC CORE OUTPUT DRIVERS D11B • • • D0B OGND 229321 TA01 U LTC2293: SNR vs Input Frequency, –1dB, 2V Range, 65Msps 72 71 70 69 68 0 100 150 50 INPUT FREQUENCY (MHz) 200 229321 TA02 U U 229321f 1 LTC2293/LTC2292/LTC2291 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW 64 GND 63 VDD 62 SENSEA 61 VCMA 60 MODE 59 SHDNA 58 OEA 57 OFA 56 DA11 55 DA10 54 DA9 53 DA8 52 DA7 51 DA6 50 OGND 49 OVDD OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2293C, LTC2292C, LTC2291C ........... 0°C to 70°C LTC2293I, LTC2292I, LTC2291I ..........–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C AINA+ 1 AINA– 2 REFHA 3 REFHA 4 REFLA 5 REFLA 6 VDD 7 CLKA 8 CLKB 9 VDD 10 REFLB 11 REFLB 12 REFHB 13 REFHB 14 AINB– 15 AINB+ 16 65 48 DA5 47 DA4 46 DA3 45 DA2 44 DA1 43 DA0 42 NC 41 NC 40 OFB 39 DB11 38 DB10 37 DB9 36 DB8 35 DB7 34 DB6 33 DB5 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2293CUP LTC2293IUP LTC2292CUP LTC2292IUP LTC2291CUP LTC2291IUP Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise CONDITIONS ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN 12 –1.4 –0.8 –12 –2.5 LTC2293 TYP MAX MIN 12 –1.4 –0.7 –12 –2.5 LTC2292 TYP MAX MIN 12 –1.3 –0.7 –12 –2.5 LTC2291 TYP MAX UNITS Bits LSB LSB mV %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS 229321f Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference External Reference SENSE = 1V ● ● ● ● ±0.3 ±0.15 ±2 ±0.5 ±10 ±30 ±15 ±0.3 ±2 0.25 1.4 0.8 12 2.5 GND 17 VDD 18 SENSEB 19 VCMB 20 MUX 21 SHDNB 22 OEB 23 NC 24 NC 25 DB0 26 DB1 27 DB2 28 DB3 29 DB4 30 OGND 31 OVDD 32 QFN PART* MARKING LTC2293UP LTC2292UP LTC2291UP ±0.3 ±0.15 ±2 ±0.5 ±10 ±30 ±15 ±0.3 ±2 0.25 1.4 0.7 12 2.5 ±0.3 ±0.15 ±2 ±0.5 ±10 ±30 ±15 ±0.3 ±2 0.25 1.3 0.7 12 2.5 2 U W U U WW W U LTC2293/LTC2292/LTC2291 A ALOG I PUT SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 2.7V < VDD < 3.4V (Note 7) Differential Input (Note 7) 0V < AIN+, AIN– < VDD 0V < SENSEA, SENSEB < 1V 0V < MODE < VDD ● ● ● ● ● Analog Input Range (AIN+ – AIN–) Analog Input Common Mode Analog Input Leakage Current SENSEA, SENSEB Input Leakage MODE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth DY A IC ACCURACY SYMBOL SNR PARAMETER Signal-to-Noise Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input 12.5MHz Input 20MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 12.5MHz Input 20MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 12.5MHz Input 20MHz Input 30MHz Input 70MHz Input 140MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 12.5MHz Input 20MHz Input 30MHz Input 70MHz Input 140MHz Input IMD Intermodulation Distortion Crosstalk fIN = Nyquist, Nyquist + 1MHz fIN = Nyquist ● ● ● ● ● ● ● ● ● ● ● ● U WU U MIN 1 –1 –3 –3 TYP 1V to 2V 1.5 MAX 1.9 1 3 3 UNITS V V µA µA µA ns psRMS dB MHz 0 0.2 80 Figure 8 Test Circuit 575 MIN LTC2293 TYP MAX 71.3 MIN LTC2292 TYP MAX 71.4 MIN 70.1 LTC2291 TYP MAX 71.4 71.2 UNITS dB dB dB dB 69.6 69.6 71.3 71.3 71 90 74 74 90 85 80 90 79 78 90 90 90 71.3 69.4 69.4 71.2 71.1 69.9 90 –110 71.3 71.1 70.7 90 75 90 85 80 90 80 90 90 90 71.4 69.8 71.2 70.9 69.9 90 –110 70.8 69.8 90 –110 90 90 71.4 71.2 85 80 90 90 70.9 70.6 90 90 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 229321f 3 LTC2293/LTC2292/LTC2291 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V LOGIC INPUTS (CLK, OE, SHDN, MUX) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● ● ● 4 U U U U U (Note 4) MIN 1.475 TYP 1.500 ±30 3 4 MAX 1.525 UNITS V ppm/°C mV/V Ω 2.7V < VDD < 3.3V –1mA < IOUT < 1mA TYP MAX UNITS V 2 0.8 –10 3 10 V µA pF VIN = 0V to VDD (Note 7) OE = High (Note 7) VOUT = 0V VOUT = 3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA ● ● 3 50 50 2.7 2.995 2.99 0.005 0.09 2.49 0.09 1.79 0.09 0.4 pF mA mA V V V V V V V V 229321f LTC2293/LTC2292/LTC2291 POWER REQUIRE E TS SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power (Each Channel) Nap Mode Power (Each Channel) CONDITIONS (Note 9) (Note 9) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) MIN ● ● ● ● Both ADCs at fS(MAX) Both ADCs at fS(MAX) SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL fs tL PARAMETER CLK Low Time CONDITIONS ● ● ● ● ● TI I G CHARACTERISTICS Sampling Frequency (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) tH CLK High Time tAP tD tMD Sample-and-Hold Aperture Delay CLK to DATA Delay Data Access Time After OE↓ CL = 5pF (Note 7) CL = 5pF (Note 7) ● ● ● ● MUX to DATA Delay CL = 5pF (Note 7) BUS Relinquish Time (Note 7) Pipeline Latency Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2293), 40MHz (LTC2292), or 25MHz (LTC2291), input range = 2VP-P with differential drive, unless otherwise noted. UW LTC2293 TYP MAX 3 3 133 400 2 15 3.4 3.6 150 450 MIN 2.7 0.5 LTC2292 TYP MAX 3 3 78 235 2 15 3.4 3.6 95 285 MIN 2.7 0.5 LTC2291 TYP MAX 3 3 50 150 2 15 3.4 3.6 60 180 UNITS V V mA mW mW mW 2.7 0.5 UW MIN 1 7.3 5 7.3 5 LTC2293 TYP MAX 65 7.7 7.7 7.7 7.7 0 500 500 500 500 MIN 1 11.8 5 11.8 5 LTC2292 TYP MAX 40 12.5 12.5 12.5 12.5 0 500 500 500 500 MIN 1 18.9 5 18.9 5 LTC2291 TYP MAX 25 20 20 20 20 0 500 500 500 500 UNITS MHz ns ns ns ns ns 1.4 1.4 2.7 2.7 4.3 3.3 6 5.4 5.4 10 8.5 1.4 1.4 2.7 2.7 4.3 3.3 6 5.4 5.4 10 8.5 1.4 1.4 2.7 2.7 4.3 3.3 6 5.4 5.4 10 8.5 ns ns ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2293), 40MHz (LTC2292), or 25MHz (LTC2291), input range = 1VP-P with differential drive. The supply current and power dissipation are the sum total for both channels with both channels active. Note 9: Recommended operating conditions. 229321f 5 LTC2293/LTC2292/LTC2291 TYPICAL PERFOR A CE CHARACTERISTICS LTC2293/LTC2292/LTC2291: Crosstalk vs Input Frequency –100 –105 –110 –115 –120 –125 –130 0 20 40 60 80 INPUT FREQUENCY (MHz) 100 229321 G01 DNL ERROR (LSB) INL ERROR (LSB) CROSSTALK (dB) LTC2293: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 65Msps 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 229321 G04 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 229321 G05 AMPLITUDE (dB) LTC2293: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 65Msps 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 229321 G07 AMPLITUDE (dB) –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 229321 G08 COUNT 6 UW LTC2293: Typical INL, 2V Range, 65Msps 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 CODE 3072 4096 229321 G02 LTC2293: Typical DNL, 2V Range, 65Msps 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 CODE 3072 4096 229321 G03 LTC2293: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 65Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 LTC2293: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 65Msps 0 5 10 15 20 25 FREQUENCY (MHz) 30 229321 G06 LTC2293: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range 65Msps 70000 60000 50000 40000 30000 20000 10000 LTC2293: Grounded Input Histogram, 65Msps 61496 –40 –50 2123 0 2042 2043 CODE 1910 2044 229321 G09 229321f LTC2293/LTC2292/LTC2291 TYPICAL PERFOR A CE CHARACTERISTICS LTC2293: SNR vs Input Frequency, –1dB, 2V Range, 65Msps 72 100 95 90 SNR AND SFDR (dBFS) 71 SFDR (dBFS) SNR (dBFS) 70 69 68 0 100 150 50 INPUT FREQUENCY (MHz) LTC2293: SNR and SFDR vs Clock Duty Cycle, 65Msps 100 95 SNR AND SFDR (dBFS) 80 SFDR: DCS ON SNR (dBc AND dBFS) 90 85 80 75 SFDR (dBc AND dBFS) SFDR: DCS OFF SNR: DCS ON 70 65 30 SNR: DCS OFF 35 40 60 CLOCK DUTY CYCLE (%) 45 50 55 65 70 LTC2293: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 155 145 135 1V RANGE 125 115 105 95 2V RANGE IOVDD (mA) IVDD (mA) 0 10 20 30 40 50 60 SAMPLE RATE (Msps) UW 229321 G10 LTC2293: SFDR vs Input Frequency, –1dB, 2V Range, 65Msps 110 LTC2293: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 SFDR 85 80 75 70 65 90 80 SNR 70 60 0 50 150 INPUT FREQUENCY (MHz) 100 200 229321 G11 200 0 20 60 80 40 SAMPLE RATE (Msps) 100 229321 G12 LTC2293: SNR vs Input Level, fIN = 30MHz, 2V Range, 65Msps 120 dBFS 70 60 50 40 30 20 10 0 –60 –50 – 40 –30 –20 INPUT LEVEL (dBFS) –10 0 dBc LTC2293: SFDR vs Input Level, fIN = 30MHz, 2V Range, 65Msps 110 100 90 80 70 60 50 40 30 20 –60 –50 – 40 –30 –20 INPUT LEVEL (dBFS) –10 0 90dBc SFDR REFERENCE LINE dBc dBFS 229321 G13 229321 G14 229321 G15 LTC2293: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 12 10 8 6 4 2 0 70 80 0 10 229321 G16 20 30 40 50 60 SAMPLE RATE (Msps) 70 80 229321 G17 229321f 7 LTC2293/LTC2292/LTC2291 TYPICAL PERFOR A CE CHARACTERISTICS LTC2292: Typical INL, 2V Range, 40Msps 1.00 0.75 0.50 DNL ERROR (LSB) INL ERROR (LSB) 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 CODE 3072 4096 229321 G18 AMPLITUDE (dB) LTC2292: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 40Msps 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 229321 G21 LTC2292: 8192 Point 2-Tone FFT, fIN = 21.6MHz and 23.6MHz, –1dB, 2V Range, 40Msps 0 –10 –20 –30 60000 50000 70000 AMPLITUDE (dB) COUNT –50 –60 –70 –80 –90 –100 –110 –120 40000 30000 20000 10000 1424 0 2558 SNR (dBFS) –40 0 5 10 15 FREQUENCY (MHz) 8 UW 229321 G24 LTC2292: Typical DNL, 2V Range, 40Msps 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 CODE 3072 4096 229321 G19 LTC2292: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 40Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 229321 G20 LTC2292: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 40Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 229321 G22 LTC2292: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 40Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 FREQUENCY (MHz) 20 229321 G23 LTC2292: Grounded Input Histogram, 40Msps 72 61538 LTC2292: SNR vs Input Frequency, –1dB, 2V Range, 40Msps 71 70 69 68 2051 CODE 2052 229321 G25 20 2050 0 100 150 50 INPUT FREQUENCY (MHz) 200 229321 G26 229321f LTC2293/LTC2292/LTC2291 TYPICAL PERFOR A CE CHARACTERISTICS LTC2292: SFDR vs Input Frequency, –1dB, 2V Range, 40Msps 100 95 100 90 110 SFDR SNR AND SFDR (dBFS) SNR (dBc AND dBFS) SFDR (dBFS) 85 80 75 70 65 0 50 150 INPUT FREQUENCY (MHz) 100 200 229321 G27 LTC2292: SFDR vs Input Level, fIN = 5MHz, 2V Range, 40Msps 120 110 100 SNR (dBc AND dBFS) 100 dBFS 90 6 90 IVDD (mA) 80 70 60 50 40 30 20 –60 dBc 90dBc SFDR REFERENCE LINE 2V RANGE 80 IOVDD (mA) –50 – 40 –30 –20 INPUT LEVEL (dBFS) 229321 G30 LTC2291: Typical INL, 2V Range, 25Msps 1.00 0.75 0.50 1.00 0.75 0.50 DNL ERROR (LSB) INL ERROR (LSB) AMPLITUDE (dB) 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 CODE 3072 4096 229321 G33 UW –10 LTC2292: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 80 70 60 50 40 30 20 10 LTC2292: SNR vs Input Level, fIN = 5MHz, 2V Range, 40Msps dBFS 90 dBc 80 SNR 70 60 0 20 40 60 SAMPLE RATE (Msps) 80 229321 G28 0 –60 –50 – 40 –30 –20 INPUT LEVEL (dBFS) –10 0 229321 G29 LTC2292: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 8 LTC2292: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 4 1V RANGE 70 2 60 0 0 10 30 40 20 SAMPLE RATE (Msps) 50 229321 G31 0 0 10 30 40 20 SAMPLE RATE (Msps) 50 229321 G32 LTC2291: Typical DNL, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –1.00 0 1024 2048 CODE 3072 4096 229321 G34 LTC2291: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 25Msps 0.25 0 –0.25 –0.50 –0.75 –120 0 2 4 6 8 FREQUENCY (MHz) 10 12 229321 G35 229321f 9 LTC2293/LTC2292/LTC2291 TYPICAL PERFOR A CE CHARACTERISTICS LTC2291: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 AMPLITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 FREQUENCY (MHz) 10 12 229321 G36 AMPLITUDE (dB) AMPLITUDE (dB) LTC2291: 8192 Point 2-Tone FFT, fIN = 10.9MHz and 13.8MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 60000 70000 AMPLITUDE (dB) –40 COUNT –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 10 FREQUENCY (MHz) 12 229321 G39 40000 30000 20000 10000 2155 0 2048 2049 CODE 1607 SNR (dBFS) LTC2291: SFDR vs Input Frequency, –1dB, 2V Range, 25Msps 100 95 100 90 110 SNR AND SFDR (dBFS) SNR (dBc AND dBFS) SFDR (dBFS) 85 80 75 70 65 0 50 150 INPUT FREQUENCY (MHz) 100 200 229321 G42 10 UW LTC2291: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 FREQUENCY (MHz) 10 12 229321 G37 LTC2291: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 2 4 6 8 FREQUENCY (MHz) 10 12 229321 G38 LTC2291: Grounded Input Histogram, 25Msps 72 61758 LTC2291: SNR vs Input Frequency, –1dB, 2V Range, 25Msps 71 50000 70 69 68 2050 229321 G40 0 100 150 50 INPUT FREQUENCY (MHz) 200 229321 G41 LTC2291: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 80 70 60 50 40 30 20 10 LTC2291: SNR vs Input Level, fIN = 5MHz, 2V Range, 25Msps dBFS SFDR 90 dBc 80 SNR 70 60 0 10 30 40 20 SAMPLE RATE (Msps) 50 229321 G43 0 –60 –50 – 40 –30 –20 INPUT LEVEL (dBFS) –10 0 229321 G44 229321f LTC2293/LTC2292/LTC2291 TYPICAL PERFOR A CE CHARACTERISTICS LTC2291: SFDR vs Input Level, fIN = 5MHz, 2V Range, 25Msps 120 110 100 dBFS SFDR (dBc AND dBFS) 90 dBc 2V RANGE 50 1V RANGE 40 70 60 50 40 30 20 –60 –50 – 40 –30 –20 INPUT LEVEL (dBFS) –10 0 90dBc SFDR REFERENCE LINE IOVDD (mA) 2 0 IVDD (mA) 80 PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge. CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge. REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. AINB– (Pin 15): Channel B Negative Differential Analog Input. AINB+ (Pin 16): Channel B Positive Differential Analog Input. GND (Pins 17, 64): ADC Power Ground. SENSEB (Pin 19): Channel B Reference Programming Pin. Connecting SENSEB to VCMB selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of ±VSENSEB. ±1V is the largest valid input range. VCMB (Pin 20): Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMA. 229321f UW 229321 G45 LTC2291: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 70 LTC2291: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 6 60 4 30 0 5 25 20 15 10 SAMPLE RATE (Msps) 30 35 229321 G46 0 5 25 20 15 10 SAMPLE RATE (Msps) 30 35 229321 G47 U U U 11 LTC2293/LTC2292/LTC2291 PI FU CTIO S MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA13, OFA; Channel B comes out on DB0-DB13, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs at high impedance. OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function. NC (Pins 24, 25, 41, 42): Do Not Connect These Pins. DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital Outputs. DB11 is the MSB. OGND (Pins 31, 50): Output Driver Ground. OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred. DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital Outputs. DA11 is the MSB. OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred. OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA pin function. SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance. MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. VCMA (Pin 61): Channel A 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMB. SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to VCMA selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEA selects an input range of ±VSENSEA. ±1V is the largest valid input range. GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground. 12 U U U 229321f LTC2293/LTC2292/LTC2291 FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE AIN– VCM 2.2µF 1.5V REFERENCE RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFH 0.1µF 2.2µF 1µF 1µF Figure 1. Functional Block Diagram (Only One Channel is Shown) W THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION REFL INTERNAL CLOCK SIGNALS OVDD OF CLOCK/DUTY CYCLE CONTROL D11 CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFL CLK MODE SHDN OE 229321 F01 U U OGND 229321f 13 LTC2293/LTC2292/LTC2291 TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP ANALOG INPUT N N+1 tH CLK tD D0-D11, OF N–6 N–5 N–4 N–3 N–2 N–1 229321 TD01 ANALOG INPUT A ANALOG INPUT B CLKA = CLKB = MUX D0A-D11A, OFA D0B-D11B, OFB 14 W UW N+2 N+3 N+4 N+5 tL Multiplexed Digital Output Bus Timing tAPA A A+1 tAPB B B+1 tH tL B+2 B+3 B+4 A+2 A+3 A+4 A–6 tD B–6 B–6 A–5 B–5 t MD A–4 B–4 A–3 B–3 A–2 A–6 B–5 A–5 B–4 A–4 B–3 A–3 B–2 229321 TD02 229321f LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, Aperture Delay Time The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π) • fIN • tJITTER Crosstalk Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal). CONVERTER OPERATION As shown in Figure 1, the LTC2293/LTC2292/LTC2291 are dual CMOS pipelined multistep converters. The converters have six pipelined ADC stages; a sampled analog input will result in a digitized value six cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost U 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. 229321f W UU 15 LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2293/LTC2292/ LTC2291 have two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the LTC2293/LTC2292/LTC2291 VDD 15Ω CPARASITIC 1pF AIN+ VDD 15Ω AIN– CLK Figure 2. Equivalent Input Circuit 229321f 16 U third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2293/ LTC2292/LTC2291 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling CSAMPLE 4pF CSAMPLE 4pF CPARASITIC 1pF VDD 229321 F02 W U U LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2293/LTC2292/LTC2291 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling U glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2293/LTC2292/LTC2291 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 25Ω 0.1µF 12pF AIN– 229321 F03 W UU AIN+ LTC2293 LTC2292 LTC2291 Figure 3. Single-Ended to Differential Conversion Using a Transformer Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. 229321f 17 LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT 2.2µF AIN+ 0.1µF LTC2293 LTC2292 LTC2291 ANALOG INPUT 25Ω T1 0.1µF 25Ω 12Ω 12Ω 0.1µF 8pF AIN– 229321 F06 + CM + 12pF – – 25Ω AIN– 229321 F04 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. VCM 1k 0.1µF ANALOG INPUT 1k 25Ω 2.2µF AIN+ LTC2293 LTC2292 LTC2291 12pF 25Ω 0.1µF AIN– 229321 F05 Figure 5. Single-Ended Drive The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. 18 U VCM 2.2µF AIN+ LTC2293 LTC2292 LTC2291 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE W UU Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz VCM 2.2µF 0.1µF ANALOG INPUT 25Ω T1 0.1µF 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 229321 F07 AIN+ 0.1µF LTC2293 LTC2292 LTC2291 Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz VCM 2.2µF 0.1µF ANALOG INPUT 25Ω T1 0.1µF 25Ω 6.8nH – 229321 F08 6.8nH 0.1µF AIN+ LTC2293 LTC2292 LTC2291 AIN T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz 229321f LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2293/LTC2292/LTC2291 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. LTC2293/LTC2292/LTC2291 1.5V VCM 2.2µF 1V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 0.5V 4Ω 1.5V BANDGAP REFERENCE 1.5V VCM 2.2µF SENSE 1µF LTC2293 LTC2292 LTC2291 TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µF 2.2µF 0.1µF DIFF AMP 1µF REFL INTERNAL ADC LOW REFERENCE 229321 F09 Figure 9. Equivalent Reference Circuit U The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges. Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB. 12k 0.75V 12k 229321 F10 W UU Figure 10. 1.5V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB. See the Typical Performance Characteristics section. Driving the Clock Input The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 11). 229321f 19 LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO 4.7µF FERRITE BEAD 0.1µF SINUSOIDAL CLOCK INPUT 0.1µF 1k CLK 50Ω 1k NC7SVU04 CLEAN SUPPLY LTC2293 LTC2292 LTC2291 229321 F11 Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2293/LTC2292/LTC2291 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2293/LTC2292/ LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and 25Msps (LTC2291). For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 7.3ns (LTC2293), 11.8ns (LTC2292), and 18.9ns (LTC2291) for the ADC internal circuitry to have enough settling time for proper operation. 20 U An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels. The lower limit of the LTC2293/LTC2292/LTC2291 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2293/LTC2292/ LTC2291 is 1Msps. DIGITAL OUTPUTS Digital Output Buffers Figure 12 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2293/LTC2292/LTC2291 should drive a minimal capacitive load to avoid possible interaction 229321f W UU LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO LTC2293/LTC2292/LTC2291 VDD VDD DATA FROM LATCH OE PREDRIVER LOGIC Figure 12. Digital Output Buffer between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format Using the MODE pin, the LTC2293/LTC2292/LTC2291 parallel digital output can be selected for offset binary or 2’s complement format. Note that MODE controls both Channel A and Channel B. Connecting MODE to GND or 1/3VDD selects straight binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 1 shows the logic states for the MODE pin. Table 1. MODE Pin Function MODE Pin 0 1/3VDD 2/3VDD VDD Output Format Straight Binary Straight Binary 2’s Complement 2’s Complement Clock Duty Cycle Stabilizer Off On On Off U OVDD 0.5V TO VDD 0.1µF OVDD 43Ω TYPICAL DATA OUTPUT OGND 229321 F12 W U U Overflow Bit When OF outputs a logic high the converter is either overranged or underranged. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. Channels A and B have independent output enable pins (OEA, OEB). 229321f 21 LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state. Channels A and B have independent SHDN pins (SHDNA, SHDNB). Channel A is controlled by SHDNA and OEA, and Channel B is controlled by SHDNB and OEB. The nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode. Digital Output Multiplexer The digital outputs of the LTC2293/LTC2292/LTC2291 can be multiplexed onto a single data bus. The MUX pin is a digital input that swaps the two data busses. If MUX is High, Channel A comes out on DA0-DA11, OFA; Channel B comes out on DB0-DB11, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-DB11, OFB; Channel B comes out on DA0-DA11, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together (see the Timing Diagram for the multiplexed mode). The multiplexed data is available on either data bus—the unused data bus can be disabled with its OE pin. 22 U Grounding and Bypassing The LTC2293/LTC2292/LTC2291 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1µF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2µF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2293/LTC2292/LTC2291 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2293/LTC2292/ LTC2291 is transferred from the die through the bottomside exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. 229321f W U U VCC JP1 MODE VDD 1 2 4 6 8 C1 0.1µF RN1D 33Ω RN1C 33Ω RN1B 33Ω RN1A 33Ω VCC RN2D 33Ω RN2C 33Ω RN2B 33Ω RN2A 33Ω RN3D 33Ω RN3C 33Ω RN3B 33Ω RN3A 33Ω RN4D 33Ω RN4C 33Ω RN4B 33Ω C2 2.2µF R1 1k 3 5 7 GND 1/3VDD 2/3VDD R2 1k R3 1k C44 0.1µF 74VCX245BQX VDD JP2 SENSE A 3 VCM 4 E1 EXT REF A EXT REF 5 6 20 VCC 18 2 A0 B0 17 3 A1 B1 16 4 B2 A2 15 5 A3 B3 14 6 B4 A4 13 7 A5 B5 12 8 A6 B6 11 9 A7 B7 1 T/R 19 10 OE GND J2 ANALOG R4 INPUT A OPT VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 C3 T1 0.1µF ETC1-1T 5 1 C6 12pF C4 0.1µF VCC C5 0.1µF R5 24.9Ω 2 R6 24.9Ω 34 32 30 28 26 24 22 20 18 16 14 14 APPLICATIO S I FOR ATIO U 12 12 10 10 8 8 6 6 4 4 2 2 C16 0.1µF R28 24Ω C43 8.2pF 228876 AI01 4 GND VDD SENSEA VCMA MODE SHDNA OEA OFA DA11 DA10 DA9 DA8 DA7 DA6 OGND OVDD • •3 R7 24.9Ω R8 51 C9 1µF C10 2.2µF C13 1µF U1 LTC2293 C11 0.1µF L1 BEAD C12 4.7µF 6.3V VCMA R9 24.9Ω C8 0.1µF 3201S-40G1 39 40 39 37 38 37 35 35 36 33 34 33 31 31 32 29 30 29 27 27 28 25 25 26 23 23 24 21 21 22 19 19 20 17 17 18 15 15 16 13 13 11 11 9 9 7 7 5 VDD VDD C14 0.1µF R10 1k C18 1µF C20 2.2µF C21 0.1µF C23 1µF GND VDD SENSEB VCMB MUX SHDNB OEB NC NC DB0 DB1 DB2 DB3 DB4 OGND OVDD C15 0.1µF VDD 20 VCC 18 2 A0 B0 17 3 A1 B1 16 4 B2 A2 15 5 A3 B3 14 6 B4 A4 13 7 A5 B5 12 8 A6 B6 11 9 B7 A7 1 T/R 19 10 OE GND 74VCX245BQX VCC J3 CLOCK INPUT C19 0.1µF U3 NC7SVU04 C17 0.1µF 5 3 3 1 1 R11 10k R12 10k C24 0.1µF R13 10k R14 49.9Ω VCC C25 0.1µF VCC R27 TBD R15 1k C13 0.1µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AINA+ AINA– REFHA REFHA REFLA REFLA VDD CLKA CLKB VDD REFLB REFLB REFHB REFHB AINB– AINB+ DA5 DA4 DA3 DA2 DA1 DA0 NC NC OFB DB11 DB10 DB9 DB8 DB7 DB6 DB5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R32 22Ω 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 U6 NC7SVU04 VDD C27 0.1µF VCC R25 105k JP3 SENSE C31 12pF VDD VCMB E2 EXT REF B C35 0.1µF EXT REF 5 6 3 4 VCM C37 10µF 6.3V R26 100k 1 2 VDD C28 2.2µF U8 LT1763 VDD R16 33Ω VDD R18 24.9Ω VCMB R20 24.9Ω R22 24.9Ω VCC U4 NC7SV86P5X 1 A0 2 A1 3 A2 4 A3 8 VCC 7 WP 6 SCL 5 SDA U5 24LC025 VDD R31 TBD U10 NC7SV86P5X E4 GND E3 VDD 3V VCC C26 0.1µF C36 E5 4.7µF PWR GND R30 15Ω J4 ANALOG R17 INPUT B OPT 2 C29 T2 0.1µF ETC1-1T 4 1 5 • •3 C33 0.1µF R24 24.9Ω C34 0.1µF R23 51 1 8 IN OUT 2 7 ADJ GND 3 6 GND GND 4 5 BYP SHDN C38 0.01µF VCC C39 1µF U7 NC7SV86P5X R29 51Ω L2 47nH C30 18pF C40 0.1µF C41 0.1µF L3 47nH C32 18pF L4 47nH C42 8.2pF VCMB U LTC2293/LTC2292/LTC2291 C7 0.1µF W VCMA 40 38 36 U VDD 1 VDD 2 23 229321f LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO 24 U Silkscreen Top Top Side 229321f W U U LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO U Inner Layer 2 GND Inner Layer 3 Power 229321f W U U 25 LTC2293/LTC2292/LTC2291 APPLICATIO S I FOR ATIO 26 U Bottom Side 229321f W U U LTC2293/LTC2292/LTC2291 PACKAGE DESCRIPTIO 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ± 0.05 R = 0.115 TYP 9 .00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 5) 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ± 0.05 7.15 ± 0.05 8.10 ± 0.05 9.50 ± 0.05 (4 SIDES) PACKAGE OUTLINE 63 64 0.40 ± 0.10 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) (UP64) QFN 1003 0.200 REF 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 229321f 27 LTC2293/LTC2292/LTC2291 RELATED PARTS PART NUMBER LTC1403A/LTC1403 LTC1407A/LTC1407 LTC1749 LTC1750 LTC2225 LTC2226 LTC2227 LTC2228 LTC2229 LTC2236 LTC2237 LTC2238 LTC2239 LTC2245 LTC2246 LTC2247 LTC2248 LTC2249 LTC2286 LTC2287 LTC2288 LTC2289 LTC2290 LTC2294 LTC2295 LTC2296 LTC2297 LTC2298 LTC2299 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit/12-Bit 2.8Msps Serial ADC 14-Bit/12-Bit 3Msps, Simultaneous Sampling Serial ADC 12-Bit, 80Msps Wideband ADC 14-Bit, 80Msps Wideband ADC 12-Bit, 10Msps ADC 12-Bit, 25Msps ADC 12-Bit, 40Msps ADC 12-Bit, 65Msps ADC 12-Bit, 80Msps ADC 10-Bit, 25Msps ADC 10-Bit, 40Msps ADC 10-Bit, 65Msps ADC 10-Bit, 80Msps ADC 14-Bit, 10Msps ADC 14-Bit, 25Msps ADC 14-Bit, 40Msps ADC 14-Bit, 65Msps ADC 14-Bit, 80Msps ADC Dual 10-Bit, 25Msps ADC Dual 10-Bit, 40Msps ADC Dual 10-Bit, 65Msps ADC Dual 10-Bit, 80Msps ADC Dual 12-Bit, 10Msps ADC Dual 12-Bit, 80Msps ADC Dual 14-Bit, 10Msps ADC Dual 14-Bit, 25Msps ADC Dual 14-Bit, 40Msps ADC Dual 14-Bit, 65Msps ADC Dual 14-Bit, 80Msps ADC DC-3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 3V, 14mW, Differential Input, MSOP Package 3V, 14mW, 2-Ch. Differential Input, MSOP Package Up to 500MHz IF Undersampling, 87dB SFDR Up to 500MHz IF Undersampling, 90dB SFDR 60mW, 71dB SNR, 5mm × 5mm QFN 75mW, 71dB SNR, 5mm × 5mm QFN 125mW, 71dB SNR, 5mm × 5mm QFN 205mW, 71dB SNR, 5mm × 5mm QFN 211mW, 70.6dB SNR, 5mm × 5mm QFN 75mW, 61dB SNR, 5mm × 5mm QFN 125mW, 61dB SNR, 5mm × 5mm QFN 205mW, 61dB SNR, 5mm × 5mm QFN 211mW, 61dB SNR, 5mm × 5mm QFN 60mW, 74.4dB SNR, 5mm × 5mm QFN 75mW, 74dB SNR, 5mm × 5mm QFN 125mW, 74dB SNR, 5mm × 5mm QFN 205mW, 74dB SNR, 5mm × 5mm QFN 222mW, 73dB SNR, 5mm × 5mm QFN 150mW, 61dB SNR, 9mm × 9mm QFN 235mW, 61dB SNR, 9mm × 9mm QFN 400mW, 61dB SNR, 9mm × 9mm QFN 445mW, 61dB SNR, 9mm × 9mm QFN 120mW, 71dB SNR, 9mm × 9mm QFN 445mW, 70.6dB SNR, 9mm × 9mm QFN 120mW, 74.4dB SNR, 9mm × 9mm QFN 150mW, 74dB SNR, 9mm × 9mm QFN 235mW, 74dB SNR, 9mm × 9mm QFN 400mW, 74dB SNR, 9mm × 9mm QFN 445mW, 73dB SNR, 9mm × 9mm QFN DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 20dBm IIP3, Integrated LO Quadrature Generator 21.5dBm IIP3, Integrated LO Quadrature Generator 21dBm IIP3, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single Ended RF and LO Ports 229321f 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/TP 1204 1K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004