LTC2295CUP

LTC2295 Dual 14-Bit, 10Msps Low Power 3V ADC FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ Integrated Dual 14-Bit ADCs Sample Rate: 10Msps Single 3V Supply (2.7V to 3.4V) Low Power: 120mW 74.4dB SNR 90dB SFDR 110dB Channel Isolation Multiplexed or Separate Data Bus Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) 10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) 64-Pin (9mm × 9mm) QFN Package The LTC®2295 is a 14-bit 10Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2295 is perfect for demanding imaging and communications applications with AC performance that includes 74.4dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation TYPICAL APPLICATIO + ANALOG INPUT A INPUT S/H 14-BIT PIPELINED ADC CORE OVDD OUTPUT DRIVERS D13A • • • – D0A OGND INL ERROR (LSB) CLK A CLOCK/DUTY CYCLE CONTROL MUX CLOCK/DUTY CYCLE CONTROL OVDD CLK B + ANALOG INPUT B INPUT S/H – 14-BIT PIPELINED ADC CORE OUTPUT DRIVERS D13B • • • D0B OGND 2295 TA01 U Typical INL, 2V Range 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 CODE 12288 16384 2295 G02 U U 2295fa 1 LTC2295 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW 64 GND 63 VDD 62 SENSEA 61 VCMA 60 MODE 59 SHDNA 58 OEA 57 OFA 56 DA13 55 DA12 54 DA11 53 DA10 52 DA9 51 DA8 50 OGND 49 OVDD OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2295C ............................................... 0°C to 70°C LTC2295I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AINA+ 1 AINA– 2 REFHA 3 REFHA 4 REFLA 5 REFLA 6 VDD 7 CLKA 8 CLKB 9 VDD 10 REFLB 11 REFLB 12 REFHB 13 REFHB 14 AINB– 15 AINB+ 16 65 48 DA7 47 DA6 46 DA5 45 DA4 44 DA3 43 DA2 42 DA1 41 DA0 40 OFB 39 DB13 38 DB12 37 DB11 36 DB10 35 DB9 34 DB8 33 DB7 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2295CUP LTC2295IUP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS ● GND 17 VDD 18 SENSEB 19 VCMB 20 MUX 21 SHDNB 22 OEB 23 DB0 24 DB1 25 DB2 26 DB3 27 DB4 28 DB5 29 DB6 30 OGND 31 OVDD 32 QFN PART* MARKING LTC2295UP MIN ● ● ● ● TYP ±1.2 ±0.5 ±2 ±0.5 ±10 ±30 ±5 ±0.3 ±2 1 MAX 5 1 12 2.5 UNITS Bits LSB LSB mV %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference External Reference SENSE = 1V 14 –5 –1 –12 –2.5 2295fa 2 U W U U WW W U LTC2295 A ALOG I PUT SYMBOL VIN VIN,CM IIN ISENSE IMODE tAP tJITTER CMRR PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS 2.7V < VDD < 3.4V (Note 7) +AIN –)/2 Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ Analog Input Leakage Current SENSEA, SENSEB Input Leakage MODE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth DY A IC ACCURACY SYMBOL SNR SFDR SFDR S/(N+D) IMD PARAMETER Signal-to-Noise Ratio The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS 5MHz Input 70MHz Input Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher Signal-to-Noise Plus Distortion Ratio Intermodulation Distortion Crosstalk 5MHz Input 70MHz Input 5MHz Input 70MHz Input 5MHz Input 70MHz Input fIN = 4.3MHz, 4.6MHz fIN = 5MHz ● ● ● ● U WU U MIN ● ● ● ● ● ● TYP ±0.5 to ±1 1.5 1.5 MAX 1.9 2 1 3 3 UNITS V V V µA µA µA ns psRMS dB MHz Differential Input (Note 7) Single Ended Input (Note 7) 0V < AIN+, AIN– < VDD 0V < SENSEA, SENSEB < 1V 0V < MODE < VDD 1 0.5 –1 –3 –3 0 0.2 80 Figure 8 Test Circuit 575 MIN 71.6 75 80 71 TYP 74.4 73.2 90 85 90 90 74.4 73.1 90 –110 MAX UNITS dB dB dB dB dB dB dB dB dB dB 2295fa 3 LTC2295 I TER AL REFERE CE CHARACTERISTICS PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN LOGIC OUTPUTS OVDD = 3V COZ ISOURCE ISINK VOH VOL OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA High Level Output Voltage Low Level Output Voltage IO = –200µA IO = 1.6mA Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance CONDITIONS VDD = 3V VDD = 3V LOGIC INPUTS (CLK, OE, SHDN, MUX) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN ● ● ● 4 U U U U U (Note 4) MIN 1.475 TYP 1.500 ±25 3 4 MAX 1.525 UNITS V ppm/°C mV/V Ω 2.7V < VDD < 3.3V –1mA < IOUT < 1mA TYP MAX UNITS V 2 0.8 –10 3 10 V µA pF VIN = 0V to VDD (Note 7) OE = High (Note 7) VOUT = 0V VOUT = 3V IO = –10µA IO = –200µA IO = 10µA IO = 1.6mA ● ● 3 50 50 2.7 2.995 2.99 0.005 0.09 2.49 0.09 1.79 0.09 0.4 pF mA mA V V V V V V V V 2295fa LTC2295 POWER REQUIRE E TS SYMBOL VDD OVDD IVDD PDISS PSHDN PNAP PARAMETER Analog Supply Voltage Output Supply Voltage Supply Current Power Dissipation Shutdown Power (Each Channel) Nap Mode Power (Each Channel) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) CONDITIONS (Note 9) (Note 9) Both ADCs at fS(MAX) Both ADCs at fS(MAX) SHDN = H, OE = H, No CLK SHDN = H, OE = L, No CLK ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL ts tL tH tAP tD tMD PARAMETER Sampling Frequency CLK Low Time CLK High Time Sample-and-Hold Aperture Delay CLK to DATA Delay MUX to DATA Delay Data Access Time After OE↓ BUS Relinquish Time Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential drive, unless otherwise noted. CL = 5pF (Note 7) CL = 5pF (Note 7) CL = 5pF (Note 7) (Note 7) ● ● ● ● TI I G CHARACTERISTICS UW MIN 2.7 0.5 TYP 3 3 40 120 2 15 MAX 3.4 3.6 46 138 UNITS V V mA mW mW mW UW CONDITIONS (Note 9) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● ● ● ● MIN 1 40 5 40 5 1.4 1.4 TYP 50 50 50 50 0 2.7 2.7 4.3 3.3 5 MAX 10 500 500 500 500 5.4 5.4 10 8.5 UNITS MHz ns ns ns ns ns ns ns ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with differential drive. The supply current and power dissipation are the sum total for both channels with both channels active. Note 9: Recommended operating conditions. 2295fa 5 LTC2295 TYPICAL PERFOR A CE CHARACTERISTICS Crosstalk vs Input Frequency –100 –105 –110 –115 –120 –125 –130 0 20 40 60 80 INPUT FREQUENCY (MHz) 100 2295 G01 0.5 0 –0.5 –1.0 –1.5 –2.0 0 4096 8192 CODE 12288 16384 2295 G02 DNL ERROR (LSB) INL ERROR (LSB) CROSSTALK (dB) 8192 Point FFT, fIN = 5.1MHz, –1dB, 2V Range 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 –110 –120 0 1 3 2 FREQUENCY (MHz) 4 5 2295 G04 –50 –60 –70 –80 –90 –100 –110 –120 0 1 3 2 FREQUENCY (MHz) 4 5 2295 G05 AMPLITUDE (dB) –40 Grounded Input Histogram 25000 22016 20000 18803 75 74 73 72 SNR (dBFS) COUNT 15000 13373 71 70 69 68 SFDR (dBFS) 10000 6919 5000 43 853 3227 278 0 8179 8180 8181 8182 8183 8184 8185 8186 CODE 2295 G07 6 UW Typical INL, 2V Range 2.0 1.5 1.0 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 Typical DNL, 2V Range 0 4096 8192 CODE 12288 16384 2295 G03 8192 Point FFT, fIN = 70.1MHz, –1dB, 2V Range 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 8192 Point 2-Tone FFT, fIN = 4.3MHz and 4.6MHz, –1dB, 2V Range –40 0 1 3 2 FREQUENCY (MHz) 4 5 2295 G06 SNR vs Input Frequency, –1dB, 2V Range 100 95 90 85 80 75 70 65 0 10 40 30 20 50 60 INPUT FREQUENCY (MHz) 70 SFDR vs Input Frequency, –1dB, 2V Range 67 66 65 0 10 40 60 30 50 20 INPUT FREQUENCY (MHz) 70 2295 G08 2295 G09 2295fa LTC2295 TYPICAL PERFOR A CE CHARACTERISTICS SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 SFDR 80 70 SNR AND SFDR (dBFS) SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 90 80 SNR 70 60 0 2 10 12 4 6 8 SAMPLE RATE (Msps) 14 2295 G10 IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 50 2.0 1.8 2V RANGE 40 1V RANGE 1.6 1.4 IOVDD (mA) IVDD (mA) 30 20 0 2 4 6 8 10 SAMPLE RATE (Msps) 12 14 UW SNR vs Input Level, fIN = 5MHz, 2V Range dBFS SFDR vs Input Level, fIN = 5MHz, 2V Range 120 110 100 90 80 70 60 50 40 30 20 10 0 –80 100dBc SFDR REFERENCE LINE dBc dBFS 60 50 40 30 20 10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 dBc –40 –20 –60 INPUT LEVEL (dBFS) 0 2295 G12 2295 G11 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 8 6 4 10 SAMPLE RATE (Msps) 12 14 2295 G13 2295 G14 2295fa 7 LTC2295 PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge. CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge. REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. AINB– (Pin 15): Channel B Negative Differential Analog Input. AINB (Pin 16): Channel B Positive Differential Analog Input. GND (Pins 17, 64): ADC Power Ground. SENSEB (Pin 19): Channel B Reference Programming Pin. Connecting SENSEB to VCMB selects the internal reference and a ±0.5V input range. VDD selects the internal reference + 8 U U U and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of ±VSENSEB. ±1V is the largest valid input range. VCMB (Pin 20): Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMA. MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA13, OFA; Channel B comes out on DB0-DB13, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs at high impedance. OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function. DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital Outputs. DB13 is the MSB. OGND (Pins 31, 50): Output Driver Ground. OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred. DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital Outputs. DA13 is the MSB. OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred. OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA pin function. 2295fa LTC2295 PI FU CTIO S SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance. MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. VCMA (Pin 61): Channel A 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMB. SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to VCMA selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEA selects an input range of ±VSENSEA. ±1V is the largest valid input range. GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground. FUNCTIONAL BLOCK DIAGRA AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE AIN– VCM 2.2µF 1.5V REFERENCE RANGE SELECT REFH SENSE REF BUF DIFF REF AMP REFH 0.1µF 2.2µF 1µ F Figure 1. Functional Block Diagram (Only One Channel is Shown) 2295fa W U U U U U THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION REFL INTERNAL CLOCK SIGNALS OVDD OF CLOCK/DUTY CYCLE CONTROL D13 CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFL CLK MODE SHDN OE 2295 F01 OGND 1µF 9 LTC2295 TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP ANALOG INPUT N N+1 tH CLK tD D0-D13, OF N–5 N–4 N–3 N–2 N–1 N 2295 TD01 ANALOG INPUT A ANALOG INPUT B CLKA = CLKB = MUX D0A-D13A, OFA D0B-D13B, OFB 10 W UW N+2 N+3 N+4 N+5 tL Multiplexed Digital Output Bus Timing tAPA A A+1 tAPB B B+1 tH tL B+2 B+3 B+4 A+2 A+3 A+4 A–5 tD B–5 B–5 A–4 B–4 t MD A–3 B–3 A–2 B–2 A–1 A–5 B–4 A–4 B–3 A–3 B–2 A–2 B–1 2295 TD02 2295fa LTC2295 APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, Aperture Delay Time The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) Crosstalk Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal). CONVERTER OPERATION As shown in Figure 1, the LTC2295 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive U 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. 2295fa W UU 11 LTC2295 APPLICATIO S I FOR ATIO applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2295 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the LTC2295 VDD 15Ω CPARASITIC 1pF CSAMPLE 4pF CPARASITIC 1pF VDD CLK CSAMPLE 4pF AIN+ VDD 15Ω AIN– Figure 2. Equivalent Input Circuit 2295fa 12 U third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2295 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from 2295 F02 W U U LTC2295 APPLICATIO S I FOR ATIO high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to VCM or a quiet reference voltage between 0.5V and 1.5V. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2295 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on U the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2295 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 25Ω 0.1µF 12pF AIN– 2295 F03 W UU AIN+ LTC2295 Figure 3. Single-Ended to Differential Conversion Using a Transformer 2295fa 13 LTC2295 APPLICATIO S I FOR ATIO Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT 2.2µF AIN+ LTC2295 + CM + 12pF – – 25Ω AIN– 2295 F04 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. VCM 1k 1k 25Ω 2.2µF AIN+ LTC2295 0.1µF ANALOG INPUT 12pF 25Ω 0.1µF AIN– 2295 F05 Figure 5. Single-Ended Drive 1µ F The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. 14 U Reference Operation Figure 6 shows the LTC2295 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (± 0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. LTC2295 1.5V VCM 2.2µF 4Ω 1.5V BANDGAP REFERENCE 1V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE REFH 0.5V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 1µ F 2.2µF 0.1µF DIFF AMP REFL INTERNAL ADC LOW REFERENCE 2295 F06 W UU Figure 6. Equivalent Reference Circuit 2295fa LTC2295 APPLICATIO S I FOR ATIO The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 6. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges. Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 7. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB. 1.5V VCM 2.2µF 12k 0.75V LTC2295 SENSE 12k 1µF 2295 F7 Figure 7. 1.5V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5.8dB. U Driving the Clock Input The CLK inputs can be driven directly with a CMOS or TTL level signal. A differential clock can also be used along with a low jitter CMOS converter before the CLK pin (Figure 8). CLEAN SUPPLY FERRITE BEAD 0.1µF 4.7µF CLK 100Ω LTC2295 2295 F08 W UU IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter The noise performance of the LTC2295 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. 2295fa 15 LTC2295 APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2295 is 10Msps. For the ADC to operate properly, the CLK signal should have a 50% (±10%) duty cycle. Each half cycle must have at least 40ns for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels. The lower limit of the LTC2295 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2295 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. 16 U Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) >+1.000000V +0.999878V +0.999756V +0.000122V 0.000000V –0.000122V –0.000244V –0.999878V –1.000000V