LTC2302CDDXPBF

LTC2302/LTC2306 Low Noise, 500ksps, 1-/2-Channel, 12-Bit ADCs FEATURES n n n n n n n DESCRIPTION The LTC®2302/LTC2306 are low noise, 500ksps, 1-/2-channel, 12-bit ADCs with an SPI/MICROWIRE compatible serial interface. These ADCs include a fully differential sample-and-hold circuit to reduce common mode noise. The internal conversion clock allows the external serial output data clock (SCK) to operate at any frequency up to 40MHz. The LTC2302/LTC2306 operate from a single 5V supply and draw just 2.8mA at a sample rate of 500ksps. The auto-shutdown feature reduces the supply current to 14μA at a sample rate of 1ksps. The LTC2302/LTC2306 are packaged in a tiny 10-pin 3mm × 3mm DFN. The low power consumption and small size make the LTC2302/LTC2306 ideal for battery-operated and portable applications, while the 4-wire SPI compatible serial interface makes these ADCs a good match for isolated or remote data acquisition systems. TYPE Int Reference Ext Reference 1 NUMBER OF INPUT CHANNELS 2 LTC2306 8 n n n n n n n 12-Bit Resolution 500ksps Sampling Rate Low Noise: SINAD = 72.8dB Guaranteed No Missing Codes Single 5V Supply Auto-Shutdown Scales Supply Current with Sample Rate Low Power: 14mW at 500ksps 70μW at 1ksps 35μW Sleep Mode 1-Channel (LTC2302) and 2-Channel (LTC2306) Versions Unipolar or Bipolar Input Ranges (Software Selectable) Internal Conversion Clock SPI/MICROWIRE™ Compatible Serial Interface Separate Output Supply OVDD (2.7V to 5.25V) Software Compatible with the LTC2308 10-Pin (3mm × 3mm) DFN Package APPLICATIONS n n n n n n LTC2308 LTC2302 High Speed Data Acquisition Industrial Process Control Motor Control Accelerometer Measurements Battery-Operated Instruments Isolated and/or Remote Data Acquisition L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 5V 2.7V TO 5.25V 10μF VDD 0.1μF OVDD 0.1μF LTC2302 LTC2306 SDI ANALOG INPUTS CH0 (IN+) 0V TO 4.096V UNIPOLAR CH1 (IN–) ±2.048V BIPOLAR ANALOG INPUT MUX 8192 Point FFT, fIN = 1kHz (LTC2306) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 50 100 fSMPL = 500kHz SINAD = 72.8dB THD = –88.7dB + – 12-BIT 500ksps ADC SERIAL PORT SDO SCK CONVST SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTER PIN NAMES IN PARENTHESIS REFER TO LTC2302 GND VREF 0.1μF 10μF 23026 TA01 MAGNITUDE (dB) 150 200 250 FREQUENCY (kHz) 23026 TA01b 23026f 1 LTC2302/LTC2306 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD, OVDD)......................... –0.3V to 6V Analog Input Voltage (Note 3) CH0(IN+)-CH1(IN–), REF ..............................(GND – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3).............................(GND – 0.3V) to (VDD + 0.3V) Digital Output Voltage ... (GND – 0.3V) to (OVDD + 0.3V) Power Dissipation ...............................................500mW Operating Temperature Range LTC2302C/LTC2306C ............................... 0°C to 70°C LTC2302I/LTC2306I.............................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C PIN CONFIGURATION LTC2302 TOP VIEW SDO 1 CONVST 2 VDD 3 IN+ 4 IN– 5 11 10 OVDD 9 SCK 8 SDI 7 GND 6 VREF SDO 1 CONVST 2 VDD 3 CH0 4 CH1 5 11 LTC2306 TOP VIEW 10 OVDD 9 SCK 8 SDI 7 GND 6 VREF DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2302CDD#PBF LTC2302IDD#PBF LTC2306CDD#PBF LTC2306IDD#PBF TAPE AND REEL LTC2302CDD#TRPBF LTC2302IDD#TRPBF LTC2306CDD#TRPBF LTC2306IDD#TRPBF PART MARKING* LDGV LDGV LDGW LDGW PACKAGE DESCRIPTION 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 23026f 2 LTC2302/LTC2306 CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Unipolar Zero Error Unipolar Zero Error Drift Unipolar Zero Error Match (LTC2306) Bipolar Full-Scale Error Bipolar Full-Scale Error Drift Unipolar Full-Scale Error Unipolar Full-Scale Error Drift Unipolar Full-Scale Error Match (LTC2306) (Note 8) l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5) CONDITIONS l MIN 12 l l l l TYP ±0.3 ±0.25 ±1 0.002 ±1 0.002 ±0.3 MAX ±1 ±1 ±6 ±6 ±3 ±8 ±6 ±3 UNITS Bits LSB LSB LSB LSB/°C LSB LSB/°C LSB LSB LSB/°C LSB LSB/°C LSB (Note 6) (Note 7) (Note 7) (Note 8) l ±1.5 0.05 ±1.2 0.05 ±0.3 ANALOG INPUT SYMBOL VIN+ VIN – The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Absolute Input Range (CH0, CH1, IN+) Absolute Input Range (CH0, CH1, IN–) CONDITIONS (Note 9) Unipolar (Note 9) Bipolar (Note 9) VIN = VIN+ – VIN– (Unipolar) VIN = VIN+ – VIN– (Bipolar) Sample Mode Hold Mode l l l l l l MIN –0.05 –0.05 –0.05 TYP MAX VDD VDD/2 VDD UNITS V V V V V VIN+ – VIN– Input Differential Voltage Range IIN CIN CMRR Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio 0 to VREF ±VREF/2 ±1 55 5 70 μA pF pF dB REFERENCE INPUT SYMBOL IREF CREF PARAMETER VREF Input Range Reference Input Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l MIN 0.1 l l TYP 50 230 55 MAX VDD 80 260 UNITS V μA μA pF fSMPL = 0ksps, VREF = 4.096V fSMPL = 500ksps, VREF = 4.096V Reference Input Capacitance 23026f 3 LTC2302/LTC2306 DYNAMIC ACCURACY SYMBOL SINAD SNR THD SFDR PARAMETER Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Channel-to-Channel Isolation Full Linear Bandwidth –3dB Input Linear Bandwidth Aperature Delay Transient Response Full-Scale Step The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 4, 10) CONDITIONS fIN = 1kHz fIN = 1kHz fIN = 1kHz, First 5 Harmonics fIN = 1kHz fIN = 1kHz (Note 11) l l l l MIN 71 71 79 TYP 72.8 73.2 –88 89 –109 700 25 13 240 MAX UNITS dB dB –78 dB dB dB kHz MHz ns ns DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current OVDD = 4.75V, IOUT = –10μA OVDD = 4.75V, IOUT = –200μA OVDD = 4.75V, IOUT = 160μA OVDD = 4.75V, IOUT = 1.6mA VOUT = 0V to OVDD, CONVST High CONVST High VOUT = 0V VOUT = OVDD CONDITIONS VDD = 5.25V VDD = 4.75V VIN = VDD The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN l l l TYP MAX 0.8 ±10 UNITS V V μA pF V V 2.4 5 l l l 4.74 4 0.05 0.4 ±10 15 –10 10 V V μA pF mA mA POWER REQUIREMENTS SYMBOL VDD OVDD IDD PD PARAMETER Supply Voltage Output Driver Supply Voltage Supply Current Sleep Mode Power Dissipation Sleep Mode The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l MIN 4.75 2.7 TYP 5 2.8 7 14 35 MAX 5.25 5.25 3.5 15 UNITS V V mA μA mW μW CL = 25pF CONVST = 5V, Conversion Done 23026f 4 LTC2302/LTC2306 TIMING CHARACTERISTICS SYMBOL fSMPL(MAX) fSCK tWHCONV tHD tSUDI tWHCLK tWLCLK tWLCONVST tHCONVST tCONV tACQ tdDO thDO ten tdis tr tf tCYC PARAMETER Maximum Sampling Frequency Shift Clock Frequency CONVST High Time Hold Time SDI After SCK↑ Setup Time SDI Stable Before SCK↑ SCK High Time SCK Low Time CONVST Low Time During Data Transfer Hold Time CONVST Low After Last SCK↓ Conversion Time Acquisition Time SDO Data Valid After SCK↓ SDO Hold Time SCK↓ SDO Valid After CONVST↓ Bus Relinquish Time SDO Rise Time SDO Fall Time Total Cycle Time 7th SCK↑ to CONVST↑ (Note 9) CL = 25pF (Note 9) CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF fSCK = fSCK(MAX) fSCK = fSCK(MAX) (Note 9) (Note 9) (Note 9) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l l l l l l l l l l l MIN TYP MAX 500 40 UNITS kHz MHz ns ns ns ns ns ns ns 20 2.5 0 10 10 410 20 1.3 240 10.8 4 11 11 4 4 2 15 15 12.5 1.6 μs ns ns ns ns ns ns ns μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with VDD and OVDD wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below ground or above VDD without latchup. Note 4: VDD = 5V, OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise specified. Note 5: Linearity, offset and full-scale specifications apply for a singleended analog input with respect to GND for the LTC2306 and IN+ with respect to IN– tied to GND for the LTC2302. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Unipolar zero error is the offset voltage measured from +0.5LSB when the output code flickers between 0000 0000 0000 and 0000 0000 0001. Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. Note 9: Guaranteed by design, not subject to test. Note 10: All specifications in dB are referred to a full-scale ±2.048V input with a 4.096V reference voltage. Note 11: Full linear bandwidth is defined as the full-scale input frequency at which the SINAD degrades to 60dB or 10 bits of accuracy. 23026f 5 LTC2302/LTC2306 TYPICAL PERFORMANCE CHARACTERISTICS (LTC2302) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted. Integral Nonlinearity vs Output Code 1.00 0.75 0.50 DNL (LSB) INL (LSB) 0.25 0 1.00 0.75 0.50 0.25 0 MAGNITUDE (dB) Differential Nonlinearity vs Output Code 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 1kHz Sine Wave 8192 Point FFT Plot SNR = 73.2dB SINAD = 72.8dB THD = –89.5dB –0.25 –0.50 –0.75 –1.00 0 1024 2048 OUTPUT CODE 23026 G01 –0.25 –0.50 –0.75 3072 4096 –1.00 0 1024 2048 OUTPUT CODE 23026 G02 3072 4096 0 50 100 150 200 250 23026 G03 FREQUENCY (kHz) SNR vs Input Frequency 80 75 70 SINAD (dB) SNR (dB) 65 60 55 50 1 10 100 FREQUENCY (kHz) 1000 23026 G04 SINAD vs Input Frequency 80 75 70 THD (dB) 65 60 55 50 1 10 100 FREQUENCY (kHz) 1000 23026 G05 THD vs Input Frequency –60 –65 –70 –75 –80 –85 –90 –95 –100 1 10 100 FREQUENCY (kHz) 1000 23026 G06 Supply Current vs Sampling Frequency 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 10 100 SAMPLING FREQUENCY (ksps) 1000 23026 G07 Supply Current vs Temperature 4.0 3.8 3.6 SUPPLY CURRENT (mA) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 SUPPLY CURRENT (mA) 23026 G08 23026f 6 LTC2302/LTC2306 TYPICAL PERFORMANCE CHARACTERISTICS (LTC2302) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted. Analog Input Leakage Current vs Temperature 1000 900 INPUT LEAKAGE CURRENT (nA) 800 700 600 500 400 300 200 100 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 Sleep Current vs Temperature 10 9 8 SLEEP CURRENT (μA) 7 6 5 4 3 2 1 0 –50 23026 G09 23026 G10 Offset Error vs Temperature 2.5 2.0 FULL-SCALE ERROR (LSB) 1.5 OFFSET ERROR (LSB) 1.0 0.5 0 –0.5 –1.0 –1.5 –1.5 –2.0 –2.5 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 UNIPOLAR BIPOLAR 2.0 1.5 1.0 0.5 0 –0.5 –1.0 Full-Scale Error vs Temperature BIPOLAR UNIPOLAR –2.0 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 23026 G11 23026 G12 23026f 7 LTC2302/LTC2306 TYPICAL PERFORMANCE CHARACTERISTICS (LTC2306) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted. Integral Nonlinearity vs Output Code 1.00 0.75 0.50 DNL (LSB) INL (LSB) 0.25 0 1.00 0.75 0.50 0.25 0 MAGNITUDE (dB) Differential Nonlinearity vs Output Code 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 1kHz Sine Wave 8192 Point FFT Plot SNR = 73.2dB SINAD = 72.8dB THD = –88.7dB –0.25 –0.50 –0.75 –1.00 0 1024 2048 OUTPUT CODE 23026 G13 –0.25 –0.50 –0.75 3072 4096 –1.00 0 1024 2048 OUTPUT CODE 23026 G14 3072 4096 0 50 100 150 200 250 23026 G15 FREQUENCY (kHz) SNR vs Input Frequency 80 75 70 SINAD (dB) SNR (dB) 65 60 55 50 1 10 100 FREQUENCY (kHz) 1000 23026 G16 SINAD vs Input Frequency 80 75 70 THD (dB) 65 60 55 50 1 10 100 FREQUENCY (kHz) 1000 23026 G17 THD vs Input Frequency –60 –65 –70 –75 –80 –85 –90 –95 –100 1 10 100 FREQUENCY (kHz) 1000 23026 G18 Supply Current vs Sampling Frequency 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 10 100 SAMPLING FREQUENCY (ksps) 1000 23026 G19 Supply Current vs Temperature 4.0 3.8 3.6 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 23026 G20 23026f 8 LTC2302/LTC2306 TYPICAL PERFORMANCE CHARACTERISTICS (LTC2306) TA = 25°C, VDD = OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless otherwise noted. Analog Input Leakage Current vs Temperature 1000 900 INPUT LEAKAGE CURRENT (nA) 800 700 600 500 400 300 200 100 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 Sleep Current vs Temperature 10 9 8 SLEEP CURRENT (μA) 7 6 5 4 3 2 1 0 –50 23026 G21 23026 G22 Offset Error vs Temperature 2.0 1.5 OFFSET ERROR (LSB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 UNIPOLAR BIPOLAR FULL-SCALE ERROR (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 Full-Scale Error vs Temperature UNIPOLAR BIPOLAR –2.0 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 23026 G23 23026 G24 23026f 9 LTC2302/LTC2306 PIN FUNCTIONS LTC2302 SDO (Pin 1): Three-State Serial Data Out. SDO outputs the data from the previous conversion. SDO is shifted out serially on the falling edge of each SCK pulse. SDO is enabled by a low level on CONVST. CONVST (Pin 2): Conversion Start. A rising edge at CONVST begins a conversion. For best performance, ensure that CONVST returns low within 40ns after the conversion starts or after the conversion ends. VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with a 0.1μF ceramic capacitor and a 10μF tantalum capacitor in parallel. IN+, IN– (Pin 4, Pin 5): Positive (IN+) and Negative (IN–) Differential Analog Inputs. VREF (Pin 6): Reference Input. Connect an external reference at VREF . The range of the external reference is 0.1V to VDD. Bypass to GND with a minimum 10μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor. GND (Pin 7): Ground. All GND pins must be connected to a solid ground plane. SDI (Pin 8): Serial Data Input. The SDI serial bit stream configures the ADC and is latched on the rising edge of the first 6 SCK pulses. SCK (Pin 9): Serial Data Clock. SCK synchronizes the serial data transfer. The serial data input at SDI is latched on the rising edge of SCK. The serial data output at SDO transitions on the falling edge of SCK. OVDD (Pin 10): Output Driver Supply. Bypass OVDD to GND with a 0.1μF ceramic capacitor close to the pin. The range of OVDD is 2.7V to 5.25V. Exposed Pad (Pin 11): Exposed Pad Ground. Must be soldered directly to ground plane. LTC2306 SDO (Pin 1): Three-State Serial Data Out. SDO outputs the data from the previous conversion. SDO is shifted out serially on the falling edge of each SCK pulse. SDO is enabled by a low level on CONVST. CONVST (Pin 2): Conversion Start. A rising edge at CONVST begins a conversion. For best performance, ensure that CONVST returns low within 40ns after the conversion starts or after the conversion ends. VDD (Pin 3): 5V Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with a 0.1μF ceramic capacitor and a 10μF tantalum capacitor in parallel. CH0, CH1 (Pin 4, Pin 5): Channel 0 and Channel 1 Analog Inputs. CH0, CH1 can be configured as single-ended or differential input channels. See the Analog Input Multiplexer section. VREF (Pin 6): Reference Input. Connect an external reference at VREF .The range of the external reference is 0.1V to VDD. Bypass to GND with a minimum 10μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor. GND (Pin 7): Ground. All GND pins must be connected to a solid ground plane. SDI (Pin 8): Serial Data Input. The SDI serial bit stream configures the ADC and is latched on the rising edge of the first 6 SCK pulses. SCK (Pin 9): Serial Data Clock. SCK synchronizes the serial data transfer. The serial data input at SDI is latched on the rising edge of SCK. The serial data output at SDO transitions on the falling edge of SCK. OVDD (Pin 10): Output Driver Supply. Bypass OVDD to OGND with a 0.1μF ceramic capacitor close to the pin. The range of OVDD is 2.7V to 5.5V. Exposed Pad (Pin 11): Exposed Pad Ground. Must be soldered directly to ground plane. 23026f 10 LTC2302/LTC2306 BLOCK DIAGRAM VDD OVDD LTC2302 LTC2306 SDI CH0 (IN+) CH1 (IN–) ANALOG INPUT MUX + – 12-BIT 500ksps ADC SERIAL PORT SDO SCK CONVST PIN NAMES IN PARENTHESIS REFER TO LTC2302 23026 BD VREF GND TEST CIRCUITS Load Circuit for tdis Waveform 1 VDD 3k SDO CL 23026 TC01 23026 TC02 Load Circuit for tdis Waveform 2, ten TEST POINT SDO 3k TEST POINT CL TIMING DIAGRAMS Voltage Waveforms for SDO Delay Times, tdDO and thDO Voltage Waveforms for tdis SCK VIL tdDO thDO VOH SDO VOL 23026 TD01 CONVST VIH SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2) 90% 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 23026 TD02 23026f 11 LTC2302/LTC2306 TIMING DIAGRAMS tWLCLK (SCK Low Time) tWHCLK (SCK High Time) tHD (Hold Time SDI After SCK↑) tSUDI (Setup Time SDI Stable Before SCK↑) tWLCLK SCK tHD SDI tSUDI 23026 TD03 Voltage Waveforms for ten CONVST tWHCLK SDO ten 23026 TD04 Voltage Waveforms for SDO Rise and Fall Times tr, tf SDO VOH VOL tr tf 23004 TD05 APPLICATIONS INFORMATION Overview The LTC2302/LTC2306 are low noise, 500ksps, 1-/2-channel, 12-bit successive approximation register (SAR) A/D converters. The LTC2306 includes a 2-channel analog input multiplexer (MUX) while the LTC2302 includes an input MUX that allows the polarity of the differential input to be selected. Both ADCs include an SPI-compatible serial port for easy data transfers and can operate in either unipolar or bipolar mode. Unipolar mode should be used for single-ended operation with the LTC2306, since singleended input signals are always referenced to GND. The LTC2302/LTC2306 can be put into a power-down sleep mode during idle periods to save power. Conversions are initiated by a rising edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, a 6-bit input word (DIN) at the SDI input configures the MUX and programs various modes of operation. As the DIN bits are shifted in, data from the previous conversion is shifted out on SDO. After the 6 bits of the DIN word have been shifted in, the ADC begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out. The acquire phase requires a minimum time of 240ns for the sample-and-hold capacitors to acquire the analog input signal. During the conversion, the internal 12-bit capacitive charge-redistribution DAC output is sequenced through a successive approximation algorithm by the SAR starting from the most significant bit (MSB) to the least significant bit (LSB). The sampled input is successively compared with binary weighted charges supplied by the capacitive DAC using a differential comparator. At the end of a conversion, the DAC output balances the analog input. The SAR contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out. Programming the LTC2306 and LTC2302 The software compatible LTC2302/LTC2306/LTC2308 family features a 6-bit DIN word to program various modes of operation. Don’t care bits (X) are ignored. The SDI data bits are loaded on the rising edge of SCK, with the S/D bit loaded on the first rising edge (see Figure 6 in the Timing 23026f 12 LTC2302/LTC2306 APPLICATIONS INFORMATION and Control section). The input data word for the LTC2306 is defined as follows: S/D O/S X X UNI X Table 1. Channel Configuration for the LTC2306 S/D 0 0 1 1 O/S 0 1 0 1 CH0 CH1 + – + + – + WITH RESPECT TO GND S/D = SINGLE-ENDED/DIFFERENTIAL BIT O/S = ODD/SIGN BIT UNI = UNIPOLAR/BIPOLAR BIT X = DON’ T CARE For the LTC2302, the input data word is defined as: X O/S X X UNI X NOTE: UNIPOLAR MODE SHOULD BE USED FOR SINGLE-ENDED OPERATION, SINCE INPUT SIGNALS ARE ALWAYS REFERENCED TO GND Table 2. Channel Configuration for the LTC2302 O/S 0 1 IN+ + – IN– – + Analog Input Multiplexer The analog input MUX is programmed by the S/D and O/S bits of the DIN word for the LTC2306 and the O/S bit of the DIN word for the LTC2302. Table 1 and Table 2 list MUX configurations for all combinations of the configuration bits. Figure 1a shows several possible MUX configurations and Figure 1b shows how the MUX can be reconfigured from one conversion to the next. 1 Differential 2 Single-Ended Driving the Analog Inputs The analog inputs of the LTC2302/LTC2306 are easy to drive. Each of the analog inputs of the LTC2306 (CH0 and CH1) can be used as a single-ended input relative to GND or as a differential pair. The analog inputs of the LTC2302 (IN+, IN–) are always configured as a differential pair. Regardless of the MUX configuration, the “+” and “–” inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while 1st Conversion 2nd Conversion + (–) – (+) { CH0 CH1 LTC2306 + + CH0 CH1 LTC2306 (–) GND 1 Differential + –{ CH0 CH1 LTC2306 + + CH0 CH1 LTC2306 + (–) – (+) { IN+ IN– LTC2302 (–) GND 23026 F01b 23026 F01a Figure 1b. Changing the MUX Assignment “On the Fly” Figure 1a. Example MUX Configurations 23026f 13 LTC2302/LTC2306 APPLICATIONS INFORMATION charging the sample-and-hold capacitors during the acquire mode. In conversion mode, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, the ADC inputs can be driven directly. Otherwise, more acquisition time should be allowed for a source with higher impedance. Reference A low noise, stable reference is required to ensure full performance. The LT®1790 and LT6660 are adequate for most applications. The LT6660 is available in 2.5V, 3V, 3.3V and 5V versions, and the LT1790 is available in 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V versions. The exceptionally low input noise allows the input range to be optimized for the application by changing the reference voltage. The VREF input must be decoupled with a 10μF capacitor in parallel with a 0.1μF capacitor, so verify that the device providing the reference voltage is stable with capacitive loads. If the voltage reference is 5V and can supply 5mA, it can be used for both VREF and VDD. VDD must be connected to a clean analog supply, and a quiet 5V reference voltage makes a convenient supply for this purpose. Input Filtering The noise and distortion of the input amplifier and other circuitry must be considered since they will add to the ADC noise and distortion. Therefore, noisy input circuitry LTC2302 LTC2306 RON 100Ω CIN 55pF RFILTER VIN CFILTER should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. The analog inputs of the LTC2302/LTC2306 can be modeled as a 55pF capacitor (CIN) in series with a 100Ω resistor (RON) as shown in Figure 2a. CIN gets switched to the selected input once during each conversion. Large filter RC time constants will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (tACQ) if DC accuracy is important. When using a filter with a large CFILTER value (e.g., 1μF), the inputs do not completely settle and the capacitive input switching currents are averaged into a net DC current (IDC). In this case, the analog input can be modeled by an equivalent resistance (REQ = 1/(fSMPL • CIN)) in series with an ideal voltage source (VREF/2) as shown in Figure 2b. The magnitude of the DC current is then approximately IDC = (VIN – VREF/2)/REQ, which is roughly proportional to VIN. To prevent large DC drops across the resistor RFILTER, a filter with a small resistor and large capacitor should be chosen. When running at the minimum cycle time of 2μs, the input current equals 106μA at VIN = 5V, which amounts to a full-scale error of 0.5LSB when using a filter resistor (RFILTER) of 4.7Ω. Applications requiring lower sample rates can tolerate a larger filter resistor for the same amount of full-scale error. INPUT (CH0, CH1 IDC IN+, IN–) LTC2302 LTC2306 RSOURCE VIN INPUT (CH0, CH1 IN+, IN–) C1 REQ 1/(fSMPL • CIN) + – VREF/2 23026 F02a 23026 F02b Figure 2a. Analog Input Equivalent Circuit Figure 2b. Analog Input Equivalent Circuit for Large Filter Capacitances 23026f 14 LTC2302/LTC2306 APPLICATIONS INFORMATION Figures 3a and 3b show respective examples of input filtering for single-ended and differential inputs. For the single-ended case in Figure 3a, a 50Ω source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1.6MHz. High quality capacitors and resistors should be used in the RC filter since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Dynamic Performance FFT (fast fourier transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. 5V 0.1μF ANALOG INPUT 50Ω CH0, CH1 2000pF LTC2306 MAGNITUDE (dB) Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 4 shows a typical SINAD of 72.8dB with a 500kHz sampling rate and a 1kHz input. A SNR of 73.2dB can be achieved with the LTC2302/LTC2306. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 50 100 SNR = 73.2dB SINAD = 72.8dB THD = –88.7dB 150 200 250 23026 F04 FREQUENCY (kHz) VIN LT1790A-4.096 VOUT 10μF 0.1μF VREF Figure 4. 1kHz Sine Wave 8192 Point FFT Plot (LTC2306) Total Harmonic Distortion (THD) 23026 F03a Figure 3a. Optional RC Input Filtering for Single-Ended Input Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency(fSMPL/2). THD is expressed as: V22 + V32 + V42 ... + VN2 THD = 20 log V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. 1000pF 50Ω 5V 0.1μF DIFFERENTIAL ANALOG INPUTS 50Ω 1000pF CH0, IN+ LTC2302 LTC2306 CH1, IN– 1000pF LT1790A-4.096 VOUT 10μF 0.1μF 23026 F03b VIN VREF Figure 3b. Optional RC Input Filtering for Differential Inputs 23026f 15 LTC2302/LTC2306 APPLICATIONS INFORMATION Internal Conversion Clock The internal conversion clock is factory trimmed to achieve a typical conversion time (tCONV) of 1.3μs and a maximum conversion time of 1.6μs over the full operating temperature range. With a minimum acquisition time of 240ns, a throughput sampling rate of 500ksps is tested and guaranteed. Digital Interface The LTC2302/LTC2306 communicate via a standard 4-wire SPI compatible digital interface. The rising edge of CONVST initiates a conversion. After the conversion is finished, pull CONVST low to enable the serial output (SDO). The ADC then shifts out the digital data in 2’s complement format when operating in bipolar mode or in straight binary format when in unipolar mode, based on the setting of the UNI bit. For best performance, ensure that CONVST returns low within 40ns after the conversion starts (i.e., before the first bit decision) or after the conversion ends. If CONVST is low when the conversion ends, the MSB bit will appear at SDO at the end of the conversion and the ADC will remain powered up. Timing and Control The start of a conversion is triggered by the rising edge of CONVST. Once initiated, a new conversion cannot be restarted until the current conversion is complete. Figures 6 and 7 show the timing diagrams for two different examples of CONVST pulses. Example 1 (Figure 6) shows CONVST staying HIGH after the conversion ends. If CONVST is high after the tCONV period, the LTC2302/LTC2306 enter sleep mode (see Sleep Mode for more details). When CONVST returns low, the ADC wakes up and the most significant bit (MSB) of the output data sequence at SDO becomes valid after the serial data bus is enabled. All other data bits from SDO transition on the falling edge of each SCK pulse. Configuration data (DIN) is loaded into the LTC2302/LTC2306 at SDI, starting with the first SCK rising edge after CONVST returns low. The S/D bit is loaded on the first SCK rising edge. Example 2 (Figure 7) shows CONVST returning low before the conversion ends. In this mode, the ADC and all internal circuitry remain powered up. When the conversion is complete, the MSB of the output data sequence at SDO becomes valid after the data bus is enabled. At this point(tCONV 1.3μs after the rising edge of CONVST), pulsing SCK will shift data out at SDO and load configuration data (DIN) into the LTC2302/LTC2306 at SDI. The first SCK rising edge loads the S/D bit. SDO transitions on the falling edge of each SCK pulse. Figures 8 and 9 are the transfer characteristics for the bipolar and unipolar modes. Data is output at SDO in 2’s complement format for bipolar readings or in straight binary for unipolar readings. Sleep Mode The ADC enters sleep mode when CONVST is held high after the conversion is complete (tCONV). The supply current decreases to 7μA in sleep mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. For example, the LTC2302/LTC2306 draw an average of 14μA with a 1ksps sampling rate. The LTC2302/LTC2306 power down all circuitry when in sleep mode. Board Layout and Bypassing To obtain the best performance, a printed circuit board with a solid ground plane is required. Layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. Care should be taken not to run any digital signal alongside an analog signal. All analog inputs should be shielded by GND. VREF and VDD should be bypassed to the ground plane as close to the pin as possible. Maintaining a low impedance path for the common return of these bypass capacitors is essential to the low noise operation of the ADC. These traces should be as wide as possible. See Figure 5 for a suggested layout. 23026f 16 LTC2302/LTC2306 APPLICATIONS INFORMATION INPUT FILTER CAPACITORS VDD, BYPASS 0.1μF||10μF 0603 , SOLID GROUND PLANE OVDD, BYPASS 0.1μF 0603 , 23026 F05 VREF, BYPASS 0.1μF||10μF 0603 Figure 5. Suggested Layout tWLCONVST CONVST tCONV SLEEP tCYC 1 SCK 2 3 4 5 6 7 8 9 10 11 12 tACQ S/D BIT IS A DON’T CARE (X) FOR THE LTC2302 SDI S/D O/S UNI MSB SDO Hi-Z LSB Hi-Z 23026 F06 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Figure 6. LTC2302/LTC2306 Timing with a Long CONVST Pulse 23026f 17 LTC2302/LTC2306 APPLICATIONS INFORMATION tWHCONV CONVST tCYC 1 2 3 4 5 6 7 8 9 10 11 12 tACQ tHCONVST tCONV SCK S/D BIT IS A DON’T CARE (X) FOR THE LTC2302 SDI S/D O/S UNI MSB SDO Hi-Z B11 LSB B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z 23026 F07 Figure 7. LTC2302/LTC2306 Timing with a Short CONVST Pulse OUTPUT CODE (TWO’S COMPLEMENT) 011...111 011...110 BIPOLAR ZERO OUTPUT CODE 111...111 111...110 000...001 000...000 111...111 111...110 FS = 4.096V 1LSB = FS/2N 1LSB = 1mV –FS/2 –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB 23026 F08 100...001 100...000 011...111 UNIPOLAR ZERO 011...110 FS = 4.096V 1LSB = FS/2N 1LSB = 1mV 0V INPUT VOLTAGE (V) 20026 F09 100...001 100...000 000...001 000...000 FS – 1LSB Figure 8. LTC2302/LTC2306 Bipolar Transfer Characteristics (2’s Complement) Figure 9. LTC2302/LTC2306 Unipolar Transfer Characteristics (Straight Binary) 23026f 18 LTC2302/LTC2306 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 ± 0.10 10 3.00 ±0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 1.65 ± 0.10 (2 SIDES) (DD) DFN 1103 5 0.200 REF 0.75 ±0.05 2.38 ±0.10 (2 SIDES) 1 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 23026f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2302/LTC2306 TYPICAL APPLICATION Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator, Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing 10μF 0.1μF 0.1μF LTC2302 LTC2306 SDI CH0 (IN+) CH1 (IN–) ANALOG INPUT MUX SDO SERIAL PORT SCK CONVST Q PRE D NL17SZ74 Q CLR CONVERT ENABLE VREF GND 0.1μF RF SIGNAL GENERATOR OR OTHER LOW JITTER SOURCE 10μF VCC MASTER CLOCK 23026 TA02 VDD OVDD + – 12-BIT 500ksps ADC VCC CONTROL LOGIC (FPGA, CPLD, DSP ETC.) , 0.1μF 1k 50Ω 1k NC7SVU04P5X MASTER CLOCK CONVERT ENABLE •••••• •••••• •••••• JITTER •••••• CONVST •••••• DATA TRANSFER •••••• RELATED PARTS PART NUMBER LTC1417 LTC1468/LT1469 LTC1609 LTC1790 LTC1850/LTC1851 LTC1852/LTC1853 LTC1860/LTC1861 LTC1860L/LTC1861L LTC1863/LTC1867 LTC1863L/LTC1867L LTC1864/LTC1865 LTC1864L/LTC1865L LTC2308 DESCRIPTION 14-Bit, 400ksps Serial ADC Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Op Amps 16-Bit, 200ksps Serial ADC Micropower Low Dropout Reference 10-Bit/12-Bit, 8-channel, 1.25Msps ADCs 10-Bit/12-Bit, 8-channel, 400ksps ADCs 12-Bit, 1-/2-Channel 250ksps ADCs in MSOP 3V, 12-bit, 1-/2-Channel 150ksps ADCs 12-/16-Bit, 8-Channel 200ksps ADCs 3V, 12-/16-bit, 8-Channel 175ksps ADCs 16-Bit, 1-/2-Channel 250ksps ADCs in MSOP 3V, 16-Bit, 1-/2-Channel 150ksps ADCs in MSOP 12-Bit, 8-Channel 500ksps ADC COMMENTS 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package Low Input Offset: 75μV/125μV 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply 60μA Supply Current, 10ppm/°C, SOT-23 Package Parallel Output, Programmable MUX and Sequencer, 5V Supply Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply 850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages 450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages 450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages 5V, Internal Reference, 4mm × 4mm QFN Packages 23026f LT 0108 • PRINTED IN USA 20 Linear Technology Corporation (408) 432-1900 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008