LTC2356-14

LTC2356-12/LTC2356-14 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 3.5Msps Conversion Rate 74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits Low Power Dissipation: 18mW 3.3V Single Supply Operation 2.5V Internal Bandgap Reference can be Overdriven 3-Wire SPI-Compatible Serial Interface Sleep (13µW) Shutdown Mode Nap (4mW) Shutdown Mode 80dB Common Mode Rejection ±1.25V Bipolar Input Range Tiny 10-Lead MSOP Package The LTC®2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13µW. The combination of speed, low power and tiny package makes the LTC2356-12/ LTC2356-14 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for AIN+ and AIN– extends from ground to the supply voltage. The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ ■ ■ Communications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Multiplexed Data Acquisition RFID BLOCK DIAGRA 10µF 3.3V LTC2356-14 AIN+ AIN– 1 7 VDD + S&H 14-BIT ADC 14-BIT LATCH 8 SDO THD, 2nd, 3rd (dB) 2 – VREF 2.5V REFERENCE THREESTATE SERIAL OUTPUT PORT 14 3 10µF 4 10 TIMING LOGIC 9 6 11 2356 BD CONV GND 5 SCK EXPOSED PAD U THD, 2nd and 3rd vs Input Frequency for Differential Input Signals –50 –56 –62 –68 –74 –80 –86 –92 –98 –104 0.1 1 10 FREQUENCY (MHz) 100 2356 G02 W U THD 2nd 3rd 2356f 1 LTC2356-12/LTC2356-14 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW AIN+ AIN– VREF GND GND 1 2 3 4 5 10 9 8 7 6 CONV SCK SDO VDD GND Supply Voltage (VDD) ................................................. 4V Analog and VREF Input Voltages (Note 3) ....................................–0.3V to (VDD + 0.3V) Digital Input Voltages ................. – 0.3V to (VDD + 0.3V) Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 100mW Operation Temperature Range LTC2356C-12/LTC2356C-14 ................... 0°C to 70°C LTC2356I-12/LTC2356I-14 ................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C 11 LTC2356CMSE-12 LTC2356IMSE-12 LTC2356CMSE-14 LTC2356IMSE-14 MSE PART MARKING LTCWN LTCWN LTCVF LTCVF MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 150°C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult factory for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Gain Error Gain Tempco (Notes 4, 5, 18) (Notes 4, 18) (Note 4, 18) CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V LTC2356-12 MIN TYP MAX ● ● ● ● LTC2356-14 MIN TYP MAX 14 –4 –30 –80 ± 0.5 ±2 ± 10 ± 15 ±1 4 30 80 UNITS Bits LSB LSB LSB ppm/°C ppm/°C 12 –2 –10 –40 ±0.25 ±1 ±5 ±15 ±1 2 10 40 Internal Reference (Note 4) External Reference A ALOG I PUT SYMBOL PARAMETER VIN VCM IIN CIN tACQ tAP tJITTER CMRR The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V CONDITIONS 3.1V ≤ VDD ≤ 3.6V ● MIN TYP –1.25 to 1.25 0 to VDD MAX UNITS V V Analog Differential Input Range (Notes 3, 8, 9) Analog Common Mode + Differential Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio ● 1 13 39 1 0.3 (Note 19) (Note 6) ● fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V –60 –15 2 U µA pF ns ns ps dB dB 2356f W U U WW W U U U LTC2356-12/LTC2356-14 DY A IC ACCURACY SYMBOL SINAD THD SFDR IMD PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C with external reference = 2.55V. VDD = 3.3V. Single-ended AIN+ signal drive with AIN– = 1.5V DC. Differential signal drive with VCM = 1.5V at AIN+ and AIN– CONDITIONS 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 100kHz First 5 Harmonics (Note 19) 1.4MHz First 5 Harmonics (Note 19) 100kHz Input Signal (Note 19) 1.4MHz Input Signal (Note 19) 0.625VP-P 1.4MHz Summed with 0.625VP-P 1.56MHz into AIN+ and Inverted into AIN– VREF = 2.5V (Note 18) VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) S/(N + D) ≥ 68dB ● ● I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time External VREF Input Range CONDITIONS IOUT = 0 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V MIN TYP 2.5 15 VDD = 3.1V to 3.6V, VREF = 2.5V Load Current = 0.5mA CREF = 10µF 2.55 600 0.2 2 VDD MAX UNITS V ppm/°C µV/V Ω ms V DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT = 0V, VDD = 3.3V VOUT = VDD = 3.3V CONDITIONS VDD = 3.6V VDD = 3.1V VIN = 0V to VDD The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V MIN ● ● ● U U U WU U LTC2356-12 MIN TYP MAX 68 71.1 71.1 –86 –82 86 82 –82 0.25 50 5 –76 LTC2356-14 MIN TYP MAX 70 74.1 72.3 –86 –82 86 82 –82 1 50 5 –78 UNITS dB dB dB dB dB dB dB LSBRMS MHz MHz U TYP MAX 0.6 ± 10 UNITS V V µA pF V V V µA pF mA mA 2.4 5 VDD = 3.3V, IOUT = – 200µA VDD = 3.1V, IOUT = 160µA VDD = 3.1V, IOUT = 1.6mA VOUT = 0V to VDD ● ● ● 2.5 2.9 0.05 0.10 1 20 15 0.4 ± 10 2356f 3 LTC2356-12/LTC2356-14 POWER REQUIRE E TS SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 17) CONDITIONS Active Mode Nap Mode Sleep Mode (LTC2356-12) Sleep Mode (LTC2356-14) Active Mode with SCK in Fixed State (Hi or Lo) ● ● PD Power Dissipation The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 PARAMETER CONDITIONS Maximum Sampling Rate per Channel (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Clock Period Conversion Time Minimum High or Low SCLK Pulse Width CONV to SCK Setup Time Nearest SCK Edge Before CONV Minimum High or Low CONV Pulse Width SCK↑ to Sample Mode CONV↑ to Hold Mode 16th SCK↑ to CONV≠ Interval (Affects Acquisition Period) Delay from SCK to Valid Data SCK↑ to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition ● ● TI I G CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and full-gain specifications are measured for a single-ended AIN+ input with AIN– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between AIN+ and AIN–. Performance is specified with AIN– = 1.5V DC while driving AIN+. Note 9: The absolute voltage at AIN+ and AIN– must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 4 UW MIN 3.1 TYP 3.3 5.5 1.1 4 4 18 MAX 3.6 8 1.5 15 12 UNITS V mA mA µA µA mW UW MIN 3.5 TYP MAX UNITS MHz ns ns SCLK cycles ns ns ns ns ns ns ns ns ns ns ms (Note 16) (Note 6) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Note 14) ● 15.872 16 2 3 0 4 4 1.2 45 286 10000 18 8 6 2 2 Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops to 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock. Note 17: VDD = 3.3V, fSAMPLE = 3.5Msps. Note 18: The LTC2356-14 is measured and specified with 14-bit resolution (1LSB = 152µV) and the LTC2356-12 is measured and specified with 12-bit resolution (1LSB = 610µV). Note 19: The sampling capacitor at each input accounts for 4.1pF of the input capacitance. 2356f LTC2356-12/LTC2356-14 TYPICAL PERFOR A CE CHARACTERISTICS SINAD vs Input Frequency 77 74 71 68 SINAD (dB) THD, 2nd, 3rd (dB) 65 62 59 56 53 50 0.1 1 10 FREQUENCY (MHz) 100 2356 G01 SFDR vs Input Frequency 92 86 80 SFDR (dB) 74 68 62 SNR (dB) 56 50 0.1 1 10 FREQUENCY (MHz) 100kHz Sine Wave 8192 Point FFT Plot 0 –10 –20 –30 MAGNITUDE (dB) MAGNITUDE (dB) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 250K 500K 750K 1M 1.25M 1.5M 1.75M FREQUENCY (Hz) 2356 G05 UW TA = 25°C, VDD = 3.3V (LTC2356-14). THD, 2nd and 3rd vs Input Frequency –50 –56 –62 –68 –74 –80 –86 –92 –98 –104 0.1 1 10 FREQUENCY (MHz) 100 2356 G02 THD 2nd 3rd SNR vs Input Frequency 77 74 71 68 65 62 59 56 53 100 2356 G03 50 0.1 1 10 FREQUENCY (MHz) 100 2356 G04 1.4MHz Sine Wave 8192 Point FFT Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 250K 500K 750K 1M 1.25M 1.5M 1.75M FREQUENCY (Hz) 2356 G06 2356f 5 LTC2356-12/LTC2356-14 TYPICAL PERFOR A CE CHARACTERISTICS Differential Linearity vs Output Code 1.0 0.8 DIFFERENTIAL LINEARITY (LSB) 4 3 INTEGRAL LINEARITY (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 12288 8192 OUTPUT CODE 16384 2356 G07 Differential and Integral Linearity vs Conversion Rate 4 3 2 LINEARITY (LSB) 0 –1 –2 MAX DNL MIN DNL MIN INL SINAD (dB) 1 –3 –4 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 CONVERSION RATE (Msps) 2356 G09 2.5VP-P Power Bandwidth 12 6 0 AMPLITUDE (dB) –40 CMRR (dB) 0 –20 –6 –12 –18 –24 –30 –36 1M 10M 100M FREQUENCY (Hz) 1G 2356 G11 6 UW MAX INL TA = 25°C, VDD = 3.3V (LTC2356-14). Integral Linearity vs Output Code 2 1 0 –1 –2 –3 –4 0 4096 8192 OUTPUT CODE 2356 G08 12288 16384 SINAD vs Conversion Rate, Input Frequency = 1.4MHz 75 74 73 72 71 70 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 CONVERSION RATE (Msps) 2356 G10 CMRR vs Frequency –60 –80 –100 –120 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 2356 G12 2356f LTC2356-12/LTC2356-14 TYPICAL PERFOR A CE CHARACTERISTICS PSRR vs Frequency –25 –30 –35 –40 PSRR (dB) –45 –50 –55 –60 –65 –70 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M VREF (V) Internal Reference Voltage vs VDD 2.4902 2.4900 2.4898 VDD SUPPLY CURRENT (mA) VREF (V) 2.4896 2.4894 2.4892 2.4890 2.6 2.8 3.0 3.2 VDD (V) 3.4 3.6 2356 G15 UW TA = 25°C, VDD = 3.3V (LTC2356-12 and LTC2356-14) Internal Reference Voltage vs Load Current 2.4902 2.4900 2.4898 2.4896 2.4894 2.4892 2.4890 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 2356 G14 2356 G13 VDD Supply Current vs Conversion Rate 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 CONVERSION RATE (Mps) 2356 G16 2356f 7 LTC2356-12/LTC2356-14 PI FU CTIO S AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN– with a –1.25V to 1.25V differential swing with respect to AIN– and a 0V to VDD common mode swing. AIN– (Pin 2): Inverting Analog Input. AIN– operates fully differentially with respect to AIN+ with a 1.25V to –1.25V differential swing with respect to AIN+ and a 0V to VDD common mode swing. VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference between 2.55V and VDD. GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These ground pins and the exposed pad must be tied directly to the solid ground plane under the part. Keep in mind that analog signal currents and digital output signal currents flow through these pins. VDD (Pin 7): 3.3V Positive Supply. This single power pin supplies 3.3V to the entire device. Bypass to GND and to a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pins 6 and 7 as possible. SDO (Pin 8): Three-State Serial Data Output. Each set of output data words represents the difference between AIN+ and AIN– analog inputs at the start of the previous conversion. The output format is 2’s complement. SCK (Pin 9): External Clock Input. Advances the conversion process and sequences the output data on the rising edge. Responds to TTL (≤ 3.3V) and 3.3V CMOS levels. One or more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds the analog input signal and starts the conversion on the rising edge. Responds to TTL (≤ 3.3V) and 3.3V CMOS levels. Two CONV pulses with SCK in fixed high or fixed low state start Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state start Sleep mode. BLOCK DIAGRA 1 + S&H 14-BIT ADC 14-BIT LATCH AIN+ AIN– 10µF 4 GND 5 6 8 W U U U 10µF 3.3V LTC2356-14 7 VDD THREESTATE SERIAL OUTPUT PORT 14 8 SDO 2 – VREF 2.5V REFERENCE 3 10 TIMING LOGIC 9 11 2356 BD CONV SCK EXPOSED PAD 2356f LTC2356-12/LTC2356-14 TI I G DIAGRA 17 SCK t4 CONV t6 INTERNAL S/H STATUS SAMPLE t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* Hi-Z 2356 TD01 18 *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED. 17 SCK t4 CONV t6 INTERNAL S/H STATUS 18 SAMPLE t8 SDO SCK CONV NAP SLEEP VREF NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS W LTC2356-12 Timing Diagram t2 t3 1 2 3 4 5 6 7 t1 8 9 10 11 12 13 14 15 16 t7 17 18 1 t5 tACQ HOLD t8 SAMPLE t9 HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT UW LTC2356-14 Timing Diagram t2 t3 1 2 3 4 5 6 7 t1 8 9 10 11 12 13 14 15 16 t7 17 18 1 t5 tACQ HOLD t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z 2356 TD01b SAMPLE t9 HOLD 14-BIT DATA WORD tCONV tTHROUGHPUT Nap Mode and Sleep Mode Waveforms t1 t1 t12 2356 TD02 SCK to SDO Delay SCK t8 t10 SDO VOH VOL 2356 TD03 VIH SCK VIH t9 90% SDO 10% 2356f 9 LTC2356-12/LTC2356-14 APPLICATIO S I FOR ATIO DRIVING THE ANALOG INPUT The differential analog inputs of the LTC2356-12/LTC2356-14 may be driven differentially or as a single-ended input (i.e., the AIN– input is set to VCM). Both differential analog inputs, AIN+ and AIN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC2356-12/ LTC2356-14 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (