LTC2380IMS-16PBF

Electrical Specifications Subject to Change LTC2380-16 16-Bit, 2Msps, Low Power SAR ADC with 96dB SNR FEATURES n n n n n n n n n n n n n n n n DESCRIPTION The LTC®2380-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2380-16 has a ±VREF fully differential input range with VREF ranging from 2.5V to 5.1V. The LTC2380-16 consumes only 19mW and achieves ±0.6LSB INL maximum, no missing codes at 16-bits with 96dB SNR. The LTC2380-16 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisychain mode. The fast 2Msps throughput with no cycle latency makes the LTC2380-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2380-16 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate. The LTC2380-16 features a unique digital gain compression (DGC) function, which eliminates the driver amplifier’s negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling function that maps zero-scale code from 0V to 0.1 • VREF and full-scale code from VREF to 0.9 • VREF. For a typical reference voltage of 5V, the full-scale input range is now 0.5V to 4.5V, which provides adequate headroom for powering the driving amplifier from a single 5.5V supply. 2Msps Throughput Rate ±0.6LSB INL (Max) Guaranteed 16-Bit No Missing Codes Low Power: 19mW at 2Msps, 19μW at 2ksps 96dB SNR (typ) at fIN = 2kHz –117dB THD (typ) at fIN = 2kHz Digital Gain Compression (DGC) Guaranteed Operation to 125°C 2.5V Supply Fully Differential Input Range ±VREF VREF Input Range from 2.5V to 5.1V No Pipeline Delay, No Cycle Latency 1.8V to 5V I/O Voltages SPI-Compatible Serial I/O with Daisy-Chain Mode Internal Conversion Clock 16-pin MSOP and 4mm × 3mm DFN Packages APPLICATIONS n n n n n n Medical Imaging High Speed Data Acquisition Portable or Compact Instrumentation Industrial Process Control Low Power Battery-Operated Instrumentation ATE L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 32k Point FFT fS = 2Msps, fIN = 2kHz 2.5V 10μF VDD IN+ 3300pF IN– 20Ω 3300pF REF 2.5V TO 5.1V 47μF (X5R, 0805 SIZE) GND LTC2380-16 OVDD 1.8V TO 5V 0.1μF AMPLITUDE (dBFS) CHAIN RDL/SDI SDO SCK BUSY CNV REF/DGC 238016 TA01 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 SNR = 96.4dB THD = –119dB SINAD = 96.3dB SFDR = 122dB VREF 0V VREF 0V 20Ω 3300pF SAMPLE CLOCK VREF 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 238016 TA02 238016p 1 LTC2380-16 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD) ...............................................2.8V Supply Voltage (OVDD) ................................................6V Reference Input (REF).................................................6V Analog Input Voltage (Note 3) IN+, IN– ......................... (GND –0.3V) to (REF + 0.3V) REF/DGC Input (Note 3) .... (GND –0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC2380C ................................................ 0°C to 70°C LTC2380I .............................................–40°C to 85°C LTC2380H .......................................... –40°C to 125°C Storage Temperature Range .................. –65°C to 150°C PIN CONFIGURATION TOP VIEW CHAIN VDD GND IN + 1 2 3 4 5 6 7 8 17 GND 16 GND 15 OVDD 14 SDO 13 SCK 12 RDL/SDI 11 BUSY 10 GND 9 CNV TOP VIEW CHAIN VDD GND IN+ IN– GND REF REF/DGC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OVDD SDO SCK RDL/SDI BUSY GND CNV IN– GND REF REF/DGC DE PACKAGE 16-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB MS PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 110°C/W ORDER INFORMATION LEAD FREE FINISH LTC2380CMS-16#PBF LTC2380IMS-16#PBF LTC2380HMS-16#PBF LTC2380CDE-16#PBF LTC2380IDE-16#PBF TAPE AND REEL LTC2380CMS-16#TRPBF LTC2380IMS-16#TRPBF LTC2380HMS-16#TRPBF LTC2380CDE-16#TRPBF LTC2380IDE-16#TRPBF PART MARKING* 238016 238016 238016 23806 23806 PACKAGE DESCRIPTION 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead (4mm × 3mm) Plastic DFN 16-Lead (4mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 238016p 2 LTC2380-16 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIN+ VIN – VIN+ – VIN– VCM IIN CIN CMRR PARAMETER Absolute Input Range (IN+) Absolute Input Range (IN–) Input Differential Voltage Range Common-Mode Input Range Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio Sample Mode Hold Mode fIN = 1MHz CONDITIONS (Note 5) (Note 5) VIN = VIN+ – VIN– l l l l l ELECTRICAL CHARACTERISTICS MIN –0.05 –0.05 –VREF VREF/2– 0.05 TYP MAX VREF + 0.05 VREF + 0.05 +VREF UNITS V V V V μA pF pF dB VREF/2 VREF/2+ 0.05 ±1 45 5 83 CONVERTER CHARACTERISTICS SYMBOL PARAMETER Resolution No Missing Codes Transition Noise INL DNL BZE FSE Integral Linearity Error Differential Linearity Error Bipolar Zero-Scale Error Bipolar Zero-Scale Error Drift Bipolar Full-Scale Error Bipolar Full-Scale Error Drift The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l l MIN 16 16 TYP MAX UNITS Bits Bits 0.15 (Note 6) (Note 7) (Note 7) –0.6 –0.5 –2 –10 ±0.25 0.1 0 1 ±2 ±0.1 10 0.6 0.5 2 LSBRMS LSB LSB LSB mLSB/°C LSB ppm/°C DYNAMIC ACCURACY SYMBOL PARAMETER SINAD SNR The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8) CONDITIONS fIN = 2kHz fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 5V, REF/DGC = GND fIN = 2kHz, VREF = 2.5V fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 5V, REF/DGC = GND fIN = 2kHz, VREF = 2.5V fIN = 2kHz l l MIN 94 94 TYP 96 96.1 95.3 93.4 –117 –114 –103 118 34 500 4 MAX UNITS dB dB dB dB dB dB dB dB MHz ps ps ns Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio THD Total Harmonic Distortion l –109 SFDR Spurious Free Dynamic Range –3dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response Full-Scale Step 175 238016p 3 LTC2380-16 REFERENCE INPUT SYMBOL VREF IREF VIHDGC VILDGC PARAMETER Reference Voltage Reference Input Current High Level Input Voltage REF/DGC Pin Low Level Input Voltage REF/DGC Pin The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS (Note 5) (Note 9) l l l l MIN 2.5 TYP 1.2 MAX 5.1 1.5 0.2VREF UNITS V mA V V 0.8VREF The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current Output Source Current Output Sink Current IO = –500 μA IO = 500 μA VOUT = 0V to OVDD VOUT = 0V VOUT = OVDD l l l DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS MIN l l TYP MAX 0.2 • OVDD UNITS V V μA pF V 0.8 • OVDD –10 5 OVDD – 0.2 0.2 –10 –10 10 10 10 VIN = 0V to OVDD l V μA mA mA POWER REQUIREMENTS SYMBOL VDD OVDD IVDD IOVDD IPD IPD PD PARAMETER Supply Voltage Supply Voltage Supply Current Supply Current Power Down Mode Power Down Mode Power Dissipation Power Down Mode Power Down Mode The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l MIN 2.375 1.71 TYP 2.5 7.5 1.1 0.9 0.9 19 2.25 2.25 MAX 2.625 5.25 8.5 40 110 21 100 275 UNITS V V mA mA μA μA mW μW μW 2Msps Sample Rate 2Msps Sample Rate (CL = 20pF) Conversion Done (IVDD + IOVDD) Conversion Done (IVDD + IOVDD, H-Grade) 2Msps Sample Rate Conversion Done (IVDD + IOVDD) Conversion Done (IVDD + IOVDD, H-Grade) ADC TIMING CHARACTERISTICS SYMBOL fSMPL tCONV tACQ tCYC tCNVH tBUSYLH tCNVL tQUIET tSCK tSCKH PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Time Between Conversions CNV High Time CNV ↑ to BUSY Delay Minimum Low Time for CNV SCK Quiet Time from CNV ↑ SCK Period SCK High Time The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l MIN 290 175 500 20 TYP MAX 2 310 UNITS Msps ns ns ns ns tACQ = tCYC –tCONV – tBUSYLH (Note 10) l l l l l l l l CL = 20pF (Note 11) (Note 11) (Note 10) (Notes 11, 12) 15 20 10 10 4 ns ns ns ns ns 238016p 4 LTC2380-16 ADC TIMING CHARACTERISTICS SYMBOL tSCKL tSSDISCK tHSDISCK tSCKCH tDSDO tHSDO tDSDOBUSYL tEN tDIS PARAMETER SCK Low Time SDI Setup Time From SCK ↑ SDI Hold Time From SCK ↑ SCK Period in Chain Mode SDO Data Valid Delay from SCK ↑ SDO Data Remains Valid Delay from SCK ↑ SDO Data Valid Delay from BUSY ↓ Bus Enable Time After RDL ↓ Bus Relinquish Time After RDL ↑ (Note 11) (Note 11) tSCKCH = tSSDISCK + tDSDO (Note 11) CL = 20pF (Note 11) CL = 20pF (Note 10) CL = 20pF (Note 10) (Note 11) (Note 11) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l l l l l MIN 4 4 1 13.5 TYP MAX UNITS ns ns ns ns 9.5 1 5 16 13 ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may effect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above REF or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without latch-up. Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 2MHz, REF/DGC = VREF. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero-scale error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale ±5V input with a 5V reference voltage. Note 9: fSMPL = 2MHz, IREF varies proportionately with sample rate. Note 10: Guaranteed by design, not subject to test. Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 12: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture. 0.8*OVDD 0.2*OVDD tDELAY 0.8*OVDD 0.2*OVDD tDELAY 0.8*OVDD 0.2*OVDD 50% tWIDTH 50% 238016 F01 Figure 1. Voltage Levels for Timing Specifications 238016p 5 LTC2380-16 fSMPL = 2Msps, unless otherwise noted. Integral Nonlinearity vs Output Code 1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 49152 OUTPUT CODE 65536 238016 G01 TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity vs Output Code 0.5 0.4 0.3 0.2 TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, DC Histogram 140000 120000 100000 COUNTS 80000 60000 40000 20000 0 σ = 0.15 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 16384 32768 49152 OUTPUT CODE 65536 238016 G02 32676 32677 32678 CODE 32679 32680 238016 G03 32k Point FFT fS = 2Msps, fIN = 2kHz 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 238016 G04 SNR, SINAD vs Input Frequency 98 96 94 SNR, SINAD (dBFS) 92 90 88 86 84 82 80 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz) 238016 G05 THD, Harmonics vs Input Frequency –80 –85 HARMONICS, THD (dBFS) SNR = 96.4dB THD = –119dB SINAD = 96.3dB SFDR = 122dB SNR –90 –95 –100 –105 –110 –115 –120 –125 –130 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz) 238016 G06 3RD THD SINAD 2ND SNR, SINAD vs Input level, fIN = 2kHz 97.0 96.5 96.0 96.5 SNR, SINAD (dBFS) SNR SINAD 96.0 SNR, SINAD (dBFS) SNR, SINAD vs Reference Voltage, fIN = 2kHz –100 –105 HARMONICS, THD (dBFS) SNR 95.5 SINAD 95.0 94.5 94.0 93.5 –110 THD, Harmonics vs Reference Voltage, fIN = 2kHz THD –115 –120 –125 –130 –135 2ND 3RD 95.5 95.0 –40 93.0 –30 –20 –10 INPUT LEVEL (dB) 238016 G07 0 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 238016 G16 –140 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 238016 G17 238016p 6 LTC2380-16 TYPICAL PERFORMANCE CHARACTERISTICS fSMPL = 2Msps, unless otherwise noted. SNR, SINAD vs Temperature, fIN = 2kHz 98.0 97.5 97.0 SNR, SINAD (dBFS) SNR 96.5 96.0 95.5 95.0 94.5 94.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G08 TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, THD, Harmonics vs Temperature, fIN = 2kHz –105 –110 HARMONICS, THD (dBFS) –115 –120 –125 –130 2ND 3RD THD INL/DNL ERROR (LSB) 0.25 0.50 INL/DNL vs Temperature MAX INL MAX DNL 0 MIN DNL –0.25 MIN INL –0.50 –55 –35 –15 SINAD –135 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G09 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G10 Full-Scale Error vs Temperature 2.0 1.5 FULL-SCALE ERROR (LSB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –55 –35 –15 +FS 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G11 Offset Error vs Temperature 1.00 POWER SUPPLY CURRENT (mA) 8 7 6 5 4 3 2 1 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G12 Supply Current vs Temperature IVDD –FS OFFSET ERROR (LSB) 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 –55 –35 –15 IOVDD IREF 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G13 0 –55 –35 –15 Shutdown Current vs Temperature 45 40 POWER-DOWN CURRENT (μA) 35 30 CMRR (dB) 25 20 15 10 75 5 0 –55 –35 –15 70 5 25 45 65 85 105 125 TEMPERATURE (°C) 238016 G14 CMRR vs Input Frequency 100 95 90 85 80 1.4 1.2 REFERENCE CURRENT (mA) 1.0 0.8 0.6 0.4 0.2 Reference Current vs Reference Voltage IVDD + IOVDD 0 200 400 600 FREQUENCY (kHz) 800 1000 238016 G15 0 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 238016 G18 238016p 7 LTC2380-16 PIN FUNCTIONS CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2380-16 operates in Normal Mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2380-16 operates in Chain Mode and the RDL/ SDI pin functions as SDI, the daisychain serial data input. Logic levels are determined by 0VDD. VDD (Pin 2): 2.5V Power Supply. The range of VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10μF ceramic capacitor. GND (Pins 3, 6, 10 and 16): Ground. IN+, IN– (Pins 4, 5): Positive and Negative Differential Analog Inputs. REF (Pin 7): Reference Input. The range of REF is 2.5V to 5.1V. This pin is referred to the GND pin and should be decoupled closely to the pin with a 47μF ceramic capacitor (X5R, 0805 size). REF/DGC (Pin 8): When tied to REF digital gain compression , is disabled and the LTC2380-16 defines full-scale according to the ±VREF analog input range. When tied to GND, digital gain compression is enabled and the LTC2380-16 defines full-scale with inputs that swing between 10% and 90% of the ±VREF analog input range. CNV (Pin 9): Convert Input. A rising edge on this input powers up the part and initiates a new conversion. Logic levels are determined by 0VDD. BUSY (Pin 11): BUSY indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. Logic levels are determined by 0VDD. RDL/SDI (Pin 12): When CHAIN is low, the part is in Normal Mode and the pin is treated as a bus enabling input. When CHAIN is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another ADC in the daisychain is input. Logic levels are determined by 0VDD. SCK (Pin 13): Serial Data Clock Input. When SDO is enabled, the conversion result or daisychain data from another ADC is shifted out on the rising edges of this clock MSB first. Logic levels are determined by 0VDD. SDO (Pin 14): Serial Data Output. The conversion result or daisychain data is output on this pin on each rising edge of SCK MSB first. The output data is in 2’s complement format. Logic levels are determined by 0VDD. OVDD (Pin 15): I/O Interface Digital Power. The range of OVDD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V, or 5V). Bypass OVDD to GND with a 0.1μF capacitor. GND (Exposed Pad Pin 17 – DFN Package Only): Ground. Exposed pad must be soldered directly to the ground plane. FUNCTIONAL BLOCK DIAGRAM VDD = 2.5V REF = 5V LTC2380-16 CHAIN SDO RDL/SDI SCK OVDD = 1.8V to 5V IN+ + 16-BIT SAMPLING ADC IN– – SPI PORT CONTROL LOGIC CNV BUSY REF/DGC GND 238016 BD01 238016p 8 LTC2380-16 TIMING DIAGRAM Conversion Timing Using the Serial Interface CHAIN, RDL/SDI = 0 CNV POWER-DOWN AND ACQUIRE BUSY CONVERT SCK D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO 238016 TD02 238016p 9 LTC2380-16 APPLICATIONS INFORMATION OVERVIEW The LTC2380-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a single 2.5V supply, the LTC2380-16 supports a large and flexible ±VREF fully differential input range with VREF ranging from 2.5V to 5.1V, making it ideal for high performance applications which require a wide dynamic range. The LTC2380-16 achieves ±0.6LSB INL max, no missing codes at 16-bits and 96dB SNR. Fast 2Msps throughput with no cycle latency makes the LTC2380-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2380-16 dissipates only 19mW at 2Msps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. The LTC2380-16 features a unique digital gain compression (DGC) function, which eliminates the driver amplifier’s negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling function that maps zero-scale code from 0V to 0.1 • VREF and full-scale code from VREF to 0.9 • VREF. For a typical reference voltage of 5V, the full-scale input range is now 0.5V to 4.5V, which provides adequate headroom for powering the driving amplifier from a single 5.5V supply. CONVERTER OPERATION The LTC2380-16 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A converter (CDAC) is connected to the IN+ and IN– pins to sample the differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the 16-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 … VREF/65536) using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 16-bit digital output code for serial transfer. TRANSFER FUNCTION The LTC2380-16 digitizes the full-scale voltage of 2 × REF into 216 levels, resulting in an LSB size of 152μV with REF = 5V. The ideal transfer function is shown in Figure 2. The output data is in 2’s complement format. OUTPUT CODE (TWO’S COMPLEMENT) 011...111 011...110 BIPOLAR ZERO 000...001 000...000 111...111 111...110 100...001 100...000 –FSR/2 FSR = +FS – –FS 1LSB = FSR/65536 –1 0V 1 FSR/2 – 1LSB LSB LSB INPUT VOLTAGE (V) 238016 F02 Figure 2. LTC2380-16 Transfer Function ANALOG INPUT The analog inputs of the LTC2380-16 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each input sees approximately 45pF (CIN) from the sampling CDAC in series with 40Ω (RON) from the on-resistance of the sampling switch. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the ADC. The inputs draw a current spike while charging the CIN capacitors during acquisition. During conversion, the analog inputs draw only a small leakage current. REF RON 40Ω CIN 45pF IN+ REF IN– RON 40Ω CIN 45pF BIAS VOLTAGE 238016 F03 Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2380-16 238016p 10 LTC2380-16 APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance inputs of the LTC2380-16 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC inputs draw a current spike when entering acquisition. For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2380-16. The amplifier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the current spike the ADC inputs draw. Input Filtering The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise. The simple 1-pole RC lowpass filter (LPF1) shown in Figure 4 is sufficient for many applications. Another filter network consisting of LPF2 should be used between the buffer and ADC input to both minimize the noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients. Long RC time constants at the analog inputs will slow down the settling of the analog inputs. Therefore, LPF2 requires a wider bandwidth than LPF1. A buffer amplifier with a low noise density must be selected to minimize degradation of the SNR. LPF2 SINGLE-ENDEDINPUT SIGNAL LPF1 500Ω 6600pF 20Ω SINGLE-ENDED- 3300pF BW = 48kHz TO-DIFFERENTIAL DRIVER BW = 800kHz 3300pF 20Ω 3300pF IN– 238016 F04 High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Single-Ended-to-Differential Conversion For single-ended input signals, a single-ended to differential conversion circuit must be used to produce a differential signal at the inputs of the LTC2380-16. The LT6350 ADC driver is recommended for performing single-ended-todifferential conversions. The LT6350 is flexible and may be configured to convert single-ended signals of various amplitudes to the ±5V differential input range of the LTC2380-16. The LT6350 is also available in H-grade to complement the extended temperature operation of the LTC2380-16 up to 125°C. Figure 5a shows the LT6350 being used to convert a 0V to 5V single-ended input signal. In this case, the first amplifier is configured as a unity gain buffer and the singleended input signal directly drives the high-impedance input of the amplifier. As shown in the FFT of Figure 5b, the LT6350 drives the LTC2380-16 to near full datasheet performance. The LT6350 can also be used to buffer and convert large true bipolar signals which swing below ground to the ±5V differential input range of the LTC2380-16 in order to maximize the signal swing that can be digitized. Figure 6a shows the LT6350 being used to convert a ±10V true bipolar signal for use by the LTC2380-16. In this case, the first amplifier in the LT6350 is configured as an inverting amplifier stage, which acts to attenuate and level shift the input signal to the 0V to 5V input range of the LTC2380-16. In the inverting amplifier configuration, the single-ended input signal source no longer directly drives a high impedance input of the first amplifier. The input impedance is instead set by resistor RIN. RIN must be chosen carefully based on the source impedance of the signal source. Higher values of RIN tend to degrade both the noise and distortion of the LT6350 and LTC2380-16 as a system. 238016p IN+ LTC2380-16 Figure 4. Input Signal Chain 11 LTC2380-16 APPLICATIONS INFORMATION LT6350 5V 8 0V 1 4 OUT1 0V 5V 5 OUT2 0V 10μF R4 = 402 R3 = 2k 5V RINT RINT VCM R2 = 499 200pF + – LT6350 4 8 OUT1 5V RINT RINT 0V 5V 5 OUT2 0V 2 – + VCM = VREF/2 + – + – 1 238016 F05a 2 R1 = 499 – + VCM = VREF/2 Figure 5a. LT6350 Converting a 0V-5V Single-Ended Signal to a ±5V Differential Input Signal 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 238016 F05b 10V 0V –10V RIN = 2k + – 220pF 238016 F06a SNR = 96.1dB THD = –104.7dB SINAD = 95.5dB SFDR = 108dB Figure 6a. LT6350 Converting a ±10V Single-Ended Signal to a ±5V Differential Input Signal 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 238016 F06b SNR = 96dB THD = –93dB SINAD = 91.2dB SFDR = 94.3dB Figure 5b. 32k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 5a R1, R2, R3 and R4 must be selected in relation to RIN to achieve the desired attenuation and to maintain a balanced input impedance in the first amplifier. Table 1 shows the resulting SNR and THD for several values of RIN, R1, R2, R3 and R4 in this configuration. Figure 6b shows the resulting FFT when using the LT6350 as shown in Figure 6a. Table 1. SNR, THD vs RIN for ±10V Single-Ended Input Signal. RIN (Ω) 2k 10k 100k R1 (Ω) 499 2.49k 24.9k R2 (Ω) 499 2.49k 24.9k R3 (Ω) 2k 10k 100k R4 (Ω) 402 2k 20k SNR (dB) 96 96 93 THD (dB) –93 –96 –97 Figure 6b. 32k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 6a 5V 0V LT6203 3 2 + – + – 5V 1 0V 5V 5 0V 6 5V 7 0V 238016 F07 Figure 7. LT6203 Buffering a Fully Differential Signal Source Digital Gain Compression The LTC2380-16 offers a digital gain compression (DGC) feature which defines the full-scale input swing to be between 10% and 90% of the ±VREF analog input range. To enable digital gain compression, bring the REF/DGC pin low. This feature allows the LT6350 to be powered off of a single +5.5V supply since each input swings between 0.5V and 4.5V as shown in Figure 8. Needing only one 238016p Fully Differential Inputs To achieve the full distortion performance of the LTC2380-16, a low distortion fully differential signal source driven through the LT6203 configured as two unity gain buffers as shown in Figure 7 can be used to get the full data sheet THD specification of –117dB. 12 LTC2380-16 APPLICATIONS INFORMATION 5V 4.5V 0.5V 0V 238016 F08 Figure 8. Input Swing of the LTC2380 with Gain Compression Enabled positive supply to power the LT6350 results in additional power savings for the entire system. Figure 9a shows how to configure the LT6350 to accept a ±10V true bipolar input signal and attenuate and level shift the signal to the reduced input range of the LTC2380-16 when digital gain compression is enabled. Figure 9b shows an FFT plot with the LTC2380-16 being driven by the LT6350 with digital gain compression enabled. ADC REFERENCE The LTC2380-16 requires an external reference to define its input range. A low noise, low temperature drift reference is critical to achieving the full datasheet performance of the ADC. Linear Technology offers a portfolio of high performance references designed to meet the needs of 5.5V 5V 1k many applications. With its small size, low power and high accuracy, the LTC6655-5 is particularly well suited for use with the LTC2380-16. The LTC6655-5 offers 0.025% (max) initial accuracy and 2ppm/°C (max) temperature coefficient for high precision applications. The LTC6655-5 is fully specified over the H-grade temperature range and complements the extended temperature operation of the LTC2380-16 up to 125°C. We recommend bypassing the LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805 size) close to the REF pin. The REF pin of the LTC2380-16 draws charge (QCONV) from the 47μF bypass capacitor during each conversion cycle. The reference replenishes this charge with a DC current, IREF = QCONV/tCYC. The DC current draw of the REF pin, IREF, depends on the sampling rate and output code. If the LTC2380-16 is used to continuously sample a signal at a constant rate, the LTC6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5LSBs. When idling, the REF pin on the LTC2380-16 draws only a small leakage current (< 1μA). In applications where a burst of samples is taken after idling for long periods as shown in Figure 10, IREF quickly goes from approximately VIN LTC6655-5 0 –20 –40 AMPLITUDE (dBFS) SNR = 94.6dB THD = –94.6dB SINAD = 91.6dB SFDR = 95.9dB VOUT_F VOUT_S 47μF 4.5V VCM 10μF 1k LT6350 6.04k 8 4.32k 10μF V +3 2.5V 3300pF 20Ω IN+ REF VDD –60 –80 –100 –120 –140 4 OUT1 0.5V + – RINT RINT 3300pF LTC2380-16 IN– 3300pF REF/DGC 238016 F09a 1 10V 0V –10V RIN = 15k 3.01k 2 VCM – + 20Ω 5 V– 6 0.5V OUT2 4.5V –160 –180 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 238016 F09b Figure 9a. LT6350 Configured to Accept a ±10V Input Signal While Running Off of a Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2380-16 Figure 9b. 32k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 9a CNV IDLE PERIOD IDLE PERIOD 238016 F10 Figure 10. CNV Waveform Showing Burst Sampling 238016p 13 LTC2380-16 APPLICATIONS INFORMATION 0μA to a maximum of 1.5mA at 2Msps. This step in DC current draw triggers a transient response in the reference that must be considered since any deviation in the reference output voltage will affect the accuracy of the output code. In applications where the transient response of the reference is important, the fast settling LTC6655-5 reference is also recommended. DYNAMIC PERFORMANCE Fast Fourier Transform (FFT) techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2380-16 provides guaranteed tested limits for both AC distortion and noise measurements. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 11 shows that the LTC2380-16 achieves a typical SINAD of 96dB at a 2MHz sampling rate with a 2kHz input. 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 238016 F11 Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 11 shows that the LTC2380-16 achieves a typical SNR of 96dB at a 2MHz sampling rate with a 2kHz input. Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: THD = 20log V22 + V32 + V42 +…+ VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. POWER CONSIDERATIONS The LTC2380-16 provides two power supply pins: the 2.5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2380-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Power Supply Sequencing The LTC2380-16 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2380-16 has a power-on-reset (POR) circuit that will reset the LTC2380-16 at initial power-up or whenever the power supply voltage drops below 1V. Once the supply voltage re-enters the nominal supply voltage range, the POR will SNR = 96.4dB THD = –119dB SINAD = 96.3dB SFDR = 122dB Figure 11. 32k Point FFT with fIN = 2kHz of the LTC2380-16 238016p 14 LTC2380-16 APPLICATIONS INFORMATION reinitialize the ADC. No conversions should be initiated until 20μs after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. TIMING AND CONTROL CNV Timing The LTC2380-16 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the LTC2380-16. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2380-16 powers down and begins acquiring the input signal. Internal Conversion Clock The LTC2380-16 has an internal clock that is trimmed to achieve a maximum conversion time of 310ns. With a minimum acquisition time of 175ns, throughput performance of 2Msps is guaranteed without any external adjustments. Auto Power-Down The LTC2380-16 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of CNV. During power down, data from the last conversion can be clocked out. To minimize power dissipation during power down, disable SDO and turn off SCK. The auto power-down feature will reduce the power dissipation of the LTC2380-16 as the sampling frequency is reduced. Since power is consumed only during a conversion, the LTC2380-16 remains powered-down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 12. DIGITAL INTERFACE The LTC2380-16 has a serial digital interface. The flexible OVDD supply allows the LTC2380-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 100MHz, a 2Msps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D15 remains valid till the first rising edge of SCK. The serial interface on the LTC2380-16 is simple and straightforward to use. The following sections describe the operation of the LTC2380-16. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy-chained. 8 POWER SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0 0 400 800 1200 1600 SAMPLING RATE (kHz) 2000 238016 F12 IVDD IOVDD IREF Figure 12. Power Supply Current of the LTC2380-16 Versus Sampling Rate 238016p 15 LTC2380-16 TIMING DIAGRAM Normal Mode, Single Device When CHAIN = 0, the LTC2380-16 operates in Normal mode. In Normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high-impedance. If RDL/SDI is low, SDO is driven. Figure 13 shows a single LTC2380-16 operated in Normal Mode with CHAIN and RDL/SDI tied to ground. With RDL/ SDI grounded, SDO is enabled and the MSB(D15) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2380-16. CONVERT CNV CHAIN LTC2380-16 RDL/SDI SCK CLK SDO DATA IN BUSY IRQ DIGITAL HOST 238016 F13a POWER-DOWN AND ACQUIRE CONVERT POWER-DOWN AND ACQUIRE CONVERT CHAIN = 0 RDL/SDI = 0 tCNVH CNV tCYC tCNVL tACQ = tCYC – tCONV – tBUSYLH BUSY tBUSYLH tCONV tSCK tACQ tSCKH 2 3 14 15 16 tQUIET SCK 1 tHSDO tDSDOBUSYL SDO D15 D14 tDSDO D13 tSCKL D1 D0 238016 F13 Figure 13. Using a Single LTC2380-16 in Normal Mode 238016p 16 LTC2380-16 TIMING DIAGRAM Normal Mode, Multiple Devices Figure 14 shows multiple LTC2380-16 devices operating in Normal Mode(CHAIN = 0) sharing CNV, SCK and SDO. By sharing CNV, SCK and SDO, the number of required signals to operate multiple ADCs in parallel is reduced. Since SDO is shared, the RDL/SDI input of each ADC must be used to allow only one LTC2380-16 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 14, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. RDLB RDLA CONVERT CNV CHAIN LTC2380-16 B RDL/SDI SCK SDO RDL/SDI SCK DATA IN CLK 238016 F15 CHAIN CNV LTC2380-16 A BUSY SDO IRQ DIGITAL HOST POWER-DOWN AND ACQUIRE CONVERT POWER-DOWN AND ACQUIRE CONVERT CHAIN = 0 CNV tCONV BUSY tBUSYLH RDL/SDIA tCNVL RDL/SDIB tSCK SCK 1 2 3 tHSDO SDO tEN Hi-Z D15A D14A D13A tDSDO D1A tDIS D0A Hi-Z D15B D14B D13B D1B D0B Hi-Z 238016 F14 tSCKH 14 15 16 tSCKL 17 18 19 30 31 32 tQUIET Figure 14. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO 238016p 17 LTC2380-16 TIMING DIAGRAM When CHAIN = OVDD, the LTC2380-16 operates in Chain Mode. In Chain Mode, SDO is always enabled and RDL/SDI serves as the serial data input pin (SDI) where daisychain data output from another ADC can be input. This is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. Figure 15 shows an example with two daisy chained devices. The MSB of converter A will appear at SDO of converter B after 16 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. CONVERT OVDD CHAIN RDL/SDI CNV LTC2380-16 A SCK SDO OVDD CHAIN RDL/SDI CNV LTC2380-16 B SCK BUSY SDO IRQ DATA IN DIGITAL HOST CLK 238016 F15a POWER-DOWN AND ACQUIRE CHAIN = OVDD RDL/SDIA = 0 CONVERT POWER-DOWN AND ACQUIRE CONVERT tCYC tCNVL CNV BUSY tBUSYLH tCONV tSCKCH tSCKH 16 tHSDO tDSDO 17 18 tSCKL 30 31 32 tQUIET SCK 1 2 3 tSSDISCK tHSDISCK 14 15 SDOA = RDL/SDIB D15A tDSDOBUSYL D14A D13A D1A D0A SDOB D15B D14B D13B D1B D0B D15A D14A D1A D0A 238016 F15 Figure 15. Chain Mode Timing Diagram 238016p 18 LTC2380-16 BOARD LAYOUT To obtain the best performance from the LTC2380-16 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1783A, the evaluation kit for the LTC2380-16. Partial Top Silkscreen 238016p 19 LTC2380-16 BOARD LAYOUT Partial Layer 1 Component Side Partial Layer 2 Ground Plane 238016p 20 LTC2380-16 BOARD LAYOUT Partial Layer 3 PWR Plane Partial Layer 4 Bottom Layer 238016p 21 LTC2380-16 BOARD LAYOUT 1 2 3 C18 OPT –IN1 C61 10μF 6.3V C39 3300pF R16 0Ω NPO OUT2 5 R36 20Ω LTC2380-16 GND GND GND GND IN– RDL/SDI R7 1k 3 6 10 16 1 C40 3300pF R35 OPT R38 OPT C19 3300pF 1206 NPO R19 0Ω VDD 2 OVDD 15 REF 7 8 REF/DGC IN+ CNV SCK SDO BUSY R45 ØΩ R15 OPT R9 OPT C42 15pF C58 OPT C9 10μF 6.3V C10 0.1μF +2.5V R34 0Ω R37 OPT C62 1μF V+ C57 0.1μF V– C55 1μF 6 C45 V – 10μF C8 1μF R18 1k JP2 CM Partial Schematic of Demoboard 1 VREF/2 2 EXT C63 10μF 6.3V C43 0.1μF C59 1μF C44 1μF C60 0.1μF 9V TO 10V 3 E7 HD1X3-100 EXT_CM C46 1μF R40 1k COUPLING AC DC JP5 HD1X3-100 1 2 3 J8 C49 OPT AIN – R39 0Ω R41 OPT C47 OPT C48 10μF 6.3V + – 2 +IN2 – + 22 R1 33Ω +3.3V C2 0.1μF +3.3V C3 0.1μF 1 +3.3V 6 CLR\ Q\ 3 3 5 DB17 DB16 J2 CON-EDGE 40-100 PR\ Q 5 U3 NL17SZ74 C56 0.1μF JP6 FS 1 2 3 HD1X3-100 U6 OPT NC7SZ66P5X 5 CNV VCC 9 2B A1 13 SCK OE 4 14 SDO GND 11 BUSY 3 12 RD +3.3V +3.3V C13 0.8VREF 0.1μF VREF R8 33Ω DC590 DETECT TO CPLD 4 R4 7 33Ω 4 CP GND 8 D VCC 2 +3.3V C4 0.1μF 5 4 2 C11 0.1μF R31 OPT V+ +3.3V C7 0.1μF C20 47μF 6.3V 0805 4 U4 NC7SVU04P5X 2 CNVST_33 FROM CPLD 9V TO 10V R3 CLK 33Ω TO CPLD U20 LTC6655AHMS8-5 1 8 SHDN GND 2 7 VIN OUT_F 3 6 GND OUT_S 4 5 GND GND R32 0Ω 8 +IN1 OUT1 4 R32 20Ω +2.5V 3 V+ U15 7 LT6350CMS8 SHDN C6 10μF 6.3V DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 4 5 3 U9 NC7SZ04P5X 2 R17 R13 2k 1k C15 0.1μF CLKOUT C16 1 0.1μF 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J3 DC590 R10 4.99k R11 4.99k R12 4.99k SDO 1 3 5 7 9 11 13 2 4 6 8 10 12 14 U7 C14 0.1μF 8 24LC025-I/ST VCC SCL SCK SDA WP CNV ARRAY A2 EEPROM A1 A0 VSS 4 238016 BL +3.3V C5 0.1μF R2 1k +3.3V C1 0.1μF 5 J1 CLKIN 2 R5 49.9Ω 1206 U2 R6 3 U8 3 NC7SZ04P5X NC7SVU04P5X 1k COUPLING AC DC JP1 HD1X3-100 J4 AIN+ R14 0Ω C17 10μF 6 5 7 3 2 1 238016p LTC2380-16 PACKAGE DESCRIPTION DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) 4.00 ±0.10 (2 SIDES) 0.70 ±0.05 3.30 ±0.05 1.70 ± 0.05 PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 0.25 ± 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.200 REF R = 0.05 TYP 3.00 ±0.10 (2 SIDES) 3.30 ±0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45° CHAMFER (DE16) DFN 0806 REV Ø R = 0.115 TYP 9 0.40 ± 0.10 16 3.60 ±0.05 2.20 ±0.05 8 0.75 ±0.05 1 0.23 ± 0.05 0.45 BSC 3.15 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 4.039 0.102 (.159 .004) (NOTE 3) 16151413121110 9 0.889 (.035 0.127 .005) 0.280 0.076 (.011 .003) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) GAUGE PLANE 0.254 (.010) DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.305 0.038 (.0120 .0015) TYP 0.50 (.0197) BSC 0.18 (.007) 0.53 0.152 (.021 .006) DETAIL “A” 12345678 1.10 (.043) MAX 0.86 (.034) REF RECOMMENDED SOLDER PAD LAYOUT SEATING NOTE: PLANE 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MS16) 1107 REV Ø 238016p Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2380-16 TYPICAL APPLICATION LT6350 Configured to Accept a ±10V Input Signal While Running Off of a Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2380-16 5.5V 5V 1k VCM 10μF 1k LT6350 6.04k 8 4.32k 10μF V+ 3 4 OUT1 0.5V 20Ω 3300pF 47μF 4.5V 3300pF IN+ REF VDD 2.5V VIN LTC6655-5 VOUT_F VOUT_S + – RINT RINT LTC2380-16 IN– 3300pF REF/DGC 238016 TA03 1 10V 0V –10V RIN = 15k 3.01k 2 VCM – + 20Ω 5 V– 6 0.5V OUT2 4.5V RELATED PARTS PART NUMBER ADCs LTC2393-16/LTC2392-16/ 16-Bit, 1Msps/500ksps/250ksps Parallel/Serial LTC2391-16 ADC LTC2383-16/LTC2382-16/ 16-Bit, 1Msps/500ksps/250ksps Serial, Low LTC2381-16 Power ADC LTC1864/LTC1864L LTC1865/LTC1865L LTC2302/LTC2306 DACs LTC2757 LTC2641-16 LTC2630 REFERENCES LTC6652 LTC6655 AMPLIFIERS LT6350 LT6200/LT6200-5/ LT6200-10 LT6202/LT6203 LTC1992 Low Noise Single-Ended-To-Differential ADC Driver 165MHz/800MHz/1.6GHz Op Amp with Unity Gain/AV = 5/AV = 10 Single/Dual 100MHz Rail-to-Rail Input/Output Noise Low Power Amplifiers Low Power, Fully Differential Input/Output Amplifier/Driver Family Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time, DFN-8 or MSOP-8 Packages Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at 1MHz, TSOT23-6 Package 1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth 1mA Supply Current Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package 18-Bit Single Parallel IOUT SoftSpan DAC 16-Bit Single Serial VOUT DACs 12-/10-/8-Bit Single VOUT DACs ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package ±1LSB INL, ±1LSB DNL, MSOP-8 Package, 0V to 5V Output SC70 6-Pin Package, Internal Reference, ±1LSB INL (12Bits) 16-bit, 250ksps/150ksps 1-Channel μPower ADC 16-bit, 250ksps/150ksps 2-Channel μPower ADC 12-Bit, 500ksps, 1-/2-Channel, Low Noise, ADC 5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, Pin Compatible Family in 7mm × 7mm LQFP-48 and QFN package 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 package 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package 5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-8 Package 5V Supply, 14mW at 500ksps, 10-Pin DFN Package 3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package DESCRIPTION COMMENTS LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC 238016p 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0211 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORA TION 2011