LTC2410IGN

FEATURES s s s s s s LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and Differential Reference DESCRIPTIO The LTC®2410 is a 2.7V to 5.5V micropower 24-bit differential ∆Σ analog to digital converter with an integrated oscillator, 2ppm INL and 0.16ppm RMS noise. It uses delta-sigma technology and provides single cycle settling time for multiplexed applications. Through a single pin, the LTC2410 can be configured for better than 110dB input differential mode rejection at 50Hz or 60Hz ± 2%, or it can be driven by an external oscillator for a user defined rejection frequency. The internal oscillator requires no external frequency setting components. The converter accepts any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The fullscale differential input range is from – 0.5VREF to 0.5VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set anywhere within the GND to VCC range of the LTC2410. The DC common mode input rejection is better than 140dB. The LTC2410 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols. s s s s s s Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL, No Missing Codes 2.5ppm Full-Scale Error 0.1ppm Offset 0.16ppm Noise Single Conversion Settling Time for Multiplexed Applications Internal Oscillator—No External Components Required 110dB Min, 50Hz or 60Hz Notch Filter 24-Bit ADC in Narrow SSOP-16 Package (SO-8 Footprint) Single Supply 2.7V to 5.5V Operation Low Supply Current (200µA) and Auto Shutdown Fully Differential Version of LTC2400 APPLICATIO S s s s s s s s s s Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Gas Analyzers Strain-Gage Transducers Instrumentation Data Acquisition Industrial Process Control 6-Digit DVMs , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. TYPICAL APPLICATIO S 2.7V TO 5.5V 1µF 2 VCC LTC2410 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE –0.5VREF TO 0.5VREF 3 4 5 6 REF + REF – IN + IN – GND SDO CS 12 11 2410 TA01 VCC FO 14 = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 3 SCK 13 3-WIRE SPI INTERFACE BRIDGE IMPEDANCE 100Ω TO 10k 1, 7, 8, 9, 10, 15, 16 U 6 U U VCC 1µF 2 REF + VCC LTC2410 FO 14 2410 TA02 12 SDO 13 SCK 11 CS 3-WIRE SPI INTERFACE 5 IN + IN – 4 REF – GND 1, 7, 8 9, 10, 15, 16 1 LTC2410 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW GND VCC REF + REF – IN + IN – GND GND 1 2 3 4 5 6 7 8 16 GND 15 GND 14 FO 13 SCK 12 SDO 11 CS 10 GND 9 GND Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2410C ............................................... 0°C to 70°C LTC2410I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC2410CGN LTC2410IGN GN PART MARKING 2410 2410I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Consult factory for parts specified with wider operating temperature ranges. The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity CONDITIONS 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) q ELECTRICAL CHARACTERISTICS MIN 24 TYP 1 2 5 0.5 10 MAX UNITS Bits ppm of VREF ppm of VREF ppm of VREF µV nV/°C 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6) q REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC, (Note 14) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF – = GND, GND ≤ IN– = IN+ ≤ VCC, (Note 13) q q q 14 2.5 Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error 2.5 0.03 2.5 0.03 3 3 4 0.8 12 ppm of VREF ppm of VREF/°C 12 ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF µVRMS Output Noise 2 U W U U WW W LTC2410 CO VERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 60Hz ± 2% Input Common Mode Rejection 50Hz ± 2% Input Normal Mode Rejection 60Hz ± 2% Input Normal Mode Rejection 50Hz ± 2% Reference Common Mode Rejection DC Power Supply Rejection, DC Power Supply Rejection, 60Hz ± 2% CONDITIONS – 2.5V CC, REF = GND, GND ≤ IN– = IN+ ≤ VCC 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN – = IN+ ≤ VCC, (Note 7) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN – = IN+ ≤ VCC, (Note 8) The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN q q q q q q Power Supply Rejection, 50Hz ± 2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) A ALOG I PUT A D REFERE CE The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage Input Differential Voltage Range (IN+ – IN–) Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Differential Voltage Range (REF+ – REF–) IN+ Sampling Capacitance IN– Sampling Capacitance REF+ Sampling Capacitance REF– Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current REF+ DC Leakage Current REF– DC Leakage Current CS = VCC, IN+ = GND CS = VCC, IN– = GND CS = VCC, REF+ = 5V CS = VCC, REF– = GND q q q q SYMBOL IN+ IN– VIN REF+ REF– VREF CS (IN+) CS (IN–) CS CS (REF+) (REF–) (IN+) (REF+) IDC_LEAK IDC_LEAK IDC_LEAK (IN–) IDC_LEAK (REF–) U U U U TYP 140 MAX UNITS dB dB dB ≤ REF+ ≤ V 130 140 140 110 110 130 (Note 7) (Note 8) 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V, VREF = 2.5V, IN– = IN+ = GND REF+ = 2.5V, REF– = GND, IN– = IN+ = GND REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 140 140 140 120 120 120 dB dB dB dB dB dB U CONDITIONS q q q q q q MIN GND – 0.3V GND – 0.3V –VREF/2 0.1 GND 0.1 TYP MAX VCC + 0.3V VCC + 0.3V VREF/2 VCC VCC – 0.1V VCC UNITS V V V V V V pF pF pF pF 18 18 18 18 –10 –10 –10 –10 1 1 1 1 10 10 10 10 nA nA nA nA 3 LTC2410 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 9) IO = –800µA IO = 1.6mA IO = –800µA (Note 10) IO = 1.6mA (Note 10) q q q q q The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.3V (Note 9) 4.5V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 5.5V (Note 9) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Note 9) q q q q q q POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS q 4 UW U U MIN 2.5 2.0 TYP MAX UNITS V V 0.8 0.6 2.5 2.0 0.8 0.6 –10 –10 10 10 VCC – 0.5V 0.4V VCC – 0.5V 0.4V –10 10 10 10 V V V V V V µA µA pF pF V V V V µA MIN 2.7 TYP MAX 5.5 UNITS V µA µA CS = 0V (Note 12) CS = VCC (Note 12) q q 200 20 300 30 LTC2410 TI I G CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time F O = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9) q q q q q q q q q The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS q q q q q q fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN + – IN –, VINCM = (IN + + IN –)/2. Note 4: FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ± 2% (external oscillator). UW MIN 2.56 0.25 0.25 TYP MAX 2000 390 390 UNITS kHz µs µs ms ms ms kHz kHz 130.86 133.53 136.20 157.03 160.23 163.44 20510/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.64 1.67 1.70 256/fEOSC (in kHz) 32/fESCK (in kHz) 0 0 0 50 220 15 50 50 200 200 200 55 2000 Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS ↓ to SDO Low Z CS ↑ to SDO High Z CS ↓ to SCK ↓ CS ↓ to SCK ↑ SCK ↓ to SDO Valid SDO Hold After SCK ↓ SCK Set-Up Before CS ↓ SCK Hold After CS ↓ % kHz ns ns ms ms ms ns ns ns ns ns ns ns ns (Note 10) (Note 9) (Note 5) q q q q q q Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ± 2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. 5 LTC2410 TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 5V) 1.5 1.0 TUE (ppm OF VREF) TUE (ppm OF VREF) 0.5 0 –0.5 –1.0 VCC = 5V REF + = 5V REF – = GND VREF = 5V VINCM = 2.5V FO = GND TA = 90°C TA = 25°C TA = – 45°C 0.5 0 TA = 90°C TA = 25°C TA = – 45°C TUE (ppm OF VREF) –1.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 VIN (V) 1 Integral Nonlinearity vs Temperature (VCC = 5V, VREF = 5V) 1.5 1.0 INL ERROR (ppm OF VREF) INL ERROR (ppm OF VREF) 0.5 0 –0.5 –1.0 0.5 0 VCC = 5V REF + = 2.5V REF – = GND VREF = 2.5V VINCM = 1.25V FO = GND –1 –0.5 TA = 25°C TA = 90°C INL ERROR (ppm OF VREF) VCC = 5V REF + = 5V REF – = GND VREF = 5V VINCM = 2.5V FO = GND TA = – 45°C TA = 25°C 1.0 TA = – 45°C –1.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 VIN (V) 1 Noise Histogram (Output Rate = 7.5Hz, VCC = 5V, VREF = 5V) 12 10 8 6 4 2 0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 OUTPUT CODE (ppm OF VREF) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V FO = GND TA = 25°C GAUSSIAN DISTRIBUTION m = 0.105ppm σ = 0.153ppm 12 10 8 6 4 2 NUMBER OF READINGS (%) NUMBER OF READINGS (%) NUMBER OF READINGS (%) 6 UW 1.5 2 2410 G01 Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 2.5V) 1.5 1.0 VCC = 5V REF + = 2.5V REF – = GND VREF = 2.5V VINCM = 1.25V FO = GND 10 8 6 4 2 0 –2 –4 –6 –8 2.5 –1.5 –1 –0.5 0 VIN (V) 0.5 1 2410 G02 Total Unadjusted Error vs Temperature (VCC = 2.7V, VREF = 2.5V) TA = 90°C TA = 25°C VCC = 2.7V REF + = 2.5V REF – = GND VREF = 2.5V VINCM = 1.25V FO = GND –1 –0.5 0 VIN (V) –0.5 –1.0 TA = – 45°C –10 0.5 1 2410 G03 Integral Nonlinearity vs Temperature (VCC = 5V, VREF = 2.5V) 1.5 10 8 6 4 2 0 –2 –4 –6 –8 0 VIN (V) 0.5 1 2410 G05 Integral Nonlinearity vs Temperature (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V REF + = 2.5V VINCM = 1.25V REF – = GND FO = GND TA = 90°C –0.5 –1.0 –1.5 TA = 90°C TA = 25°C TA = – 45°C 1.5 2 2.5 –10 –1 –0.5 0 VIN (V) 0.5 1 2410 G06 2410 G04 Noise Histogram (Output Rate = 22.5Hz, VCC = 5V, VREF = 5V) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V FO = 460800Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 0.067ppm σ = 0.151ppm 12 10 8 6 4 2 Noise Histogram (Output Rate = 52.5Hz, VCC = 5V, VREF = 5V) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V FO = 1075200Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 8.285ppm σ = 0.311ppm 0.8 0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 OUTPUT CODE (ppm OF VREF) 0.8 0 –9.8 –9.4 –9 –8.6 –8.2 –7.8 –7.4 –7 –6.6 OUTPUT CODE (ppm OF VREF) 2410 G09 2410 G07 2410 G08 LTC2410 TYPICAL PERFOR A CE CHARACTERISTICS Noise Histogram (Output Rate = 7.5Hz, VCC = 5V, VREF = 2.5V) 12 10 8 6 4 2 0 –1.6 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = GND TA = 25°C GAUSSIAN DISTRIBUTION m = 0.033ppm σ = 0.293ppm 12 10 8 6 4 2 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF) NUMBER OF READINGS (%) NUMBER OF READINGS (%) NUMBER OF READINGS (%) –0.8 0 0.8 OUTPUT CODE (ppm OF VREF) Noise Histogram (Output Rate = 7.5Hz, VCC = 2.7V, VREF = 2.5V) 12 10 8 6 4 2 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF) 10,000 CONSECUTIVE READINGS VCC = 2.7V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = GND TA = 25°C GAUSSIAN DISTRIBUTION m = 0.079ppm σ = 0.298ppm 12 10 8 6 4 2 NUMBER OF READINGS (%) NUMBER OF READINGS (%) NUMBER OF READINGS (%) Long-Term Noise Histogram (Time = 60 Hrs, VCC = 5V, VREF = 5V) 12 10 8 6 4 2 GAUSSIAN DISTRIBUTION m = 0.101837ppm σ = 0.154515ppm ADC CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V FO = GND TA = 25°C 0.8 1.0 0.8 ADC READING (ppm OF VREF) NUMBER OF READINGS (%) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 VCC = 5V TA = 25°C IN + = 2.5V VREF = 5V REF + = 5V IN – = 2.5V VIN = 0V REF – = GND FO = GND 5 10 15 20 25 30 35 40 45 50 55 60 TIME (HOURS) 2410 G17 RMS NOISE (ppm OF VREF) 0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 OUTPUT CODE (ppm OF VREF) UW 1.6 2410 G10 Noise Histogram (Output Rate = 22.5Hz, VCC = 5V, VREF = 2.5V) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = 460800Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 0.014ppm σ = 0.292ppm 12 10 8 6 4 2 Noise Histogram (Output Rate = 52.5Hz, VCC = 5V, VREF = 2.5V) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = 1075200Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 3.852ppm σ = 0.326ppm 1.6 0 –5.5 –5.1 –4.7 –4.3 –3.9 –3.5 –3.1 –2.7 –2.3 OUTPUT CODE (ppm OF VREF) 2410 G12 2410 G11 Noise Histogram (Output Rate = 22.5Hz, VCC = 2.7V, VREF = 2.5V) 10,000 CONSECUTIVE READINGS VCC = 2.7V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = 460800Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 0.177ppm σ = 0.297ppm 10 Noise Histogram (Output Rate = 52.5Hz, VCC = 2.7V, VREF = 2.5V) 10,000 CONSECUTIVE 9 READINGS V = 2.7V 8 VCC = 2.5V REF 7 VIN = 0V REF + = 2.5V 6 REF – = GND IN + = 1.25V 5 IN – = 1.25V 4 FO = 1075200Hz TA = 25°C 3 2 1 GAUSSIAN DISTRIBUTION m = 3.714ppm σ = 1.295ppm 1.6 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF) 1.6 0 –10 –8.5 –7 –5.5 –4 –2.5 –1 0.5 OUTPUT CODE (ppm OF VREF) 2 2410 G13 2410 G14 2410 G15 Consecutive ADC Readings vs Time 0.5 RMS Noise vs Input Differential Voltage VCC = 5V VREF = 5V REF + = 5V REF – = GND VINCM = 2.5V FO = GND TA = 25°C 0.6 0.4 0.3 0.2 0.1 0 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) 2.5 2410 G16 2410 G18 7 LTC2410 TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs VINCM 850 825 800 RMS NOISE (nV) RMS NOISE (nV) 775 750 725 700 675 VCC = 5V REF + = 5V REF – = GND VREF = 5V IN + = VINCM IN – = VINCM VIN = 0V FO = GND TA = 25°C 775 750 725 700 675 650 –50 RMS NOISE (nV) 650 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 2410 G19 RMS Noise vs VREF 850 825 800 RMS NOISE (nV) OFFSET ERROR (ppm OF VREF) 775 750 725 700 675 650 0 0.1 0 –0.1 –0.2 VCC = 5V REF + = 5V REF – = GND VREF = 5V IN + = VINCM IN – = VINCM VIN = 0V FO = GND TA = 25°C OFFSET ERROR (ppm OF VREF) VCC = 5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 Offset Error vs VCC 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 2.7 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 +FULL-SCALE ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) REF + = 2.5V REF – = GND VREF = 2.5V IN + = GND IN – = GND FO = GND TA = 25°C 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 8 UW 4 4.5 2410 G22 2410 G25 RMS Noise vs Temperature (TA) 850 825 800 VCC = 5V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V VIN = 0V FO = GND 850 825 800 775 750 725 700 675 –25 0 25 50 TEMPERATURE (°C) 75 100 2410 G20 RMS Noise vs VCC REF + = 2.5V REF – = GND VREF = 2.5V IN + = GND IN – = GND FO = GND TA = 25°C 650 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 2410 G21 Offset Error vs VINCM 0.3 0.2 0.3 0.2 0.1 0 –0.1 –0.2 Offset Error vs Temperature (TA) VCC = 5V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V VIN = 0V FO = GND –25 0 25 50 TEMPERATURE (°C) 75 100 2410 G24 5 –0.3 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 2410 G23 –0.3 –50 Offset Error vs VREF 3 2 1 0 –1 –2 + Full-Scale Error vs Temperature (TA) VCC = 5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 5 VCC = 5V REF + = 5V REF – = GND IN + = 2.5V IN – = GND FO = GND 0 15 30 45 60 TEMPERATURE (°C) 75 90 –3 –45 –30 –15 2410 G26 2410 G27 LTC2410 TYPICAL PERFOR A CE CHARACTERISTICS + Full-Scale Error vs VCC 3 +FULL-SCALE ERROR (ppm OF VREF) 2 1 0 –1 –2 –3 2.7 +FULL-SCALE ERROR (ppm OF VREF) 3 2 1 0 –1 –2 –3 –FULL-SCALE ERROR (ppm OF VREF) REF + = 2.5V REF – = GND VREF = 2.5V IN + = 1.25V IN – = GND FO = GND TA = 25°C 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 – Full-Scale Error vs VCC 3 –FULL-SCALE ERROR (ppm OF VREF) –FULL-SCALE ERROR (ppm OF VREF) 2 1 0 –1 –2 –3 2.7 REF + = 2.5V REF – = GND VREF = 2.5V IN + = GND IN – = 1.25V FO = GND TA = 25°C 3 2 1 0 –1 –2 –3 REJECTION (dB) 3.1 3.5 3.9 4.3 VCC (V) 4.7 PSRR vs Frequency at VCC 0 –20 –40 REJECTION (dB) REJECTION (dB) REJECTION (dB) –60 –80 –100 –120 –140 VCC = 4.1VDC ± 1.4V REF + = 2.5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C 0 30 60 90 120 150 180 210 240 FREQUENCY AT VCC (Hz) 2410 G34 UW 2410 G28 + Full-Scale Error vs VREF 3 2 1 0 –1 –2 – Full-Scale Error vs Temperature (TA) VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = 2.5V FO = GND VCC = 5V REF + = VREF REF – = GND IN + = 0.5 • REF + IN – = GND FO = GND TA = 25°C 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 5 –3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2410 G29 2410 G30 – Full-Scale Error vs VREF 0 VCC = 5V REF + = VREF REF – = GND IN + = GND IN – = 0.5 • REF + FO = GND TA = 25°C –20 –40 –60 –80 –100 –120 PSRR vs Frequency at VCC VCC = 4.1VDC ± 1.4V REF + = 2.5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C 5.1 5.5 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 5 –140 0.01 0.1 1 10 FREQUENCY AT VCC (Hz) 100 2410 G33 2410 G31 2410 G32 PSRR vs Frequency at VCC 0 –20 –40 –60 –80 –100 –120 –140 REF + = 2.5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M PSRR vs Frequency at VCC VCC = 4.1VDC ± 0.7V REF + = 2.5V REF – = GND IN + = GND IN – = GND FO = GND TA = 25°C –100 7600 7620 7640 7660 7680 7700 7720 7740 FREQUENCY AT VCC (Hz) 2410 G36 2410 G35 9 LTC2410 TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Temperature (TA) 220 210 FO = GND CS = GND SCK = NC SDO = NC 1100 1000 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) VCC = 5.5V 200 190 180 VCC = 2.7V 170 160 –45 –30 –15 VCC = 4.1V 0 15 30 45 60 TEMPERATURE (°C) PI FU CTIO S GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All seven pins must be connected to ground for proper operation. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. REF + (Pin 3), REF – (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF –, by at least 0.1V. IN + (Pin 5), IN– (Pin 6): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF ) to 0.5 • (VREF ). Outside this input range the converter produces unique overrange and underrange output codes. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter first null is located at a frequency fEOSC/2560. 10 UW 75 90 2410 G37 Conversion Current vs Output Data Rate VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = GND TA = 25°C FO = EXTERNAL OSC CS = GND SCK = NC SDO = NC 23 22 21 20 19 Sleep Current vs Temperature (TA) FO = GND CS = VCC SCK = NC SDO = NC VCC = 5.5V VCC = 4.1V 900 800 700 600 500 400 300 200 100 0 VCC = 2.7V 18 17 16 –45 –30 –15 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 G38 0 15 30 45 60 TEMPERATURE (°C) 75 90 2410 G39 U U U LTC2410 FU CTIO AL BLOCK DIAGRA VCC GND AUTOCALIBRATION AND CONTROL IN + IN – + –∫ ∫ ∫ ∑ ADC SERIAL INTERFACE DECIMATING FIR REF + REF – –+ DAC Figure 1. Functional Block Diagram TEST CIRCUITS SDO SDO 1.69k CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 2410 TA03 APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2410 is a low power, delta-sigma analog-todigital converter with an easy to use 3-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2410 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state W INTERNAL OSCILLATOR FO (INT/EXT) SDO SCK CS 2410 FD U W U U U U VCC 1.69k Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2410 TA04 as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. CONVERT SLEEP FALSE CS = LOW AND SCK TRUE DATA OUTPUT 2410 F02 Figure 2. LTC2410 State Transition Diagram 11 LTC2410 APPLICATIO S I FOR ATIO Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2410 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50 or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2410 incorporates a highly accurate onchip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2410 achieves a minimum of 110dB rejection at the line frequency (50Hz or 60Hz ± 2%). Ease of Use The LTC2410 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. 12 U The LTC2410 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2410 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2410 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF – pin. The LTC2410 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates (see the Output Data Rate section). W U U LTC2410 APPLICATIO S I FOR ATIO Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2410 converts the bipolar differential input signal, VIN = IN+ – IN–, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN– pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN– pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/ Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2410 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS). Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. U This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential input resistance is 1.8MΩ which will generate a gain error of approximately 0.28ppm for each ohm of source resistance driving IN+ or IN –. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential input resistance is 2.16MΩ which will generate a gain error of approximately 0.23ppm for each ohm of source resistance driving IN+ or IN –. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 0.28 • 1012/fEOSCΩ and each ohm of source resistance driving IN+ or IN – will result in 1.78 • 10–6 • fEOSCppm gain error. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown in Figures 19 and 20. In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins 26 U IN+ and IN– and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW (internal oscillator and 60Hz notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.28ppm. When FO = HIGH (internal oscillator and 50Hz notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.23ppm. When FO is driven by an external oscillator with a frequency fEOSC, every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1.78 • 10–6 • fEOSCppm. Figure 21 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. W U U LTC2410 APPLICATIO S I FOR ATIO 300 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C CIN = 1µF, 10µF +FS ERROR (ppm OF VREF) 240 180 CIN = 0.1µF 120 CIN = 0.01µF 60 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 2410 F19 Figure 19. +FS Error vs RSOURCE 0 at IN+ or IN– (Large C CIN = 0.01µF –FS ERROR (ppm OF VREF) –60 –120 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C CIN = 0.1µF –180 –240 CIN = 1µF, 10µF –300 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 2410 F20 Figure 20. –FS Error vs RSOURCE 120 100 A B C D E F G 80 60 40 20 0 –20 –40 –60 –80 –100 –120 0 0.5 1 1.5 at IN+ or IN– (Large CIN) OFFSET ERROR (ppm OF VREF) VCC = 5V REF + = 5V REF – = GND IN + = IN – = VINCM FO = GND TA = 25°C RSOURCEIN – = 500Ω CIN = 10µF 2 2.5 3 VINCM (V) 3.5 4 4.5 5 A: ∆RIN = + 400Ω B: ∆RIN = + 200Ω C: ∆RIN = + 100Ω D: ∆RIN = 0Ω E: ∆RIN = – 100Ω F: ∆RIN = – 200Ω G: ∆RIN = – 400Ω 2410 F21 Figure 21. Offset Error vs Common Mode Voltage (VINCM = IN+ = IN–) and Input Source Resistance Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF) U In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 100Ω source resistance will create a 0.1µV typical and 1µV maximum offset voltage. Reference Current In a similar fashion, the LTC2410 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 0.01µF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential reference resistance is 1.3MΩ which will generate a gain error of approximately 0.38ppm for each ohm of source resistance driving REF+ or REF–. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential reference resistance is 1.56MΩ which will generate a gain error of approximately 0.32ppm for each ohm of source resistance driving REF+ or REF–. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.20 • 1012/fEOSCΩ and each ohm of source resistance drving REF + o r REF – w ill result in 2.47 • 10–6 • fEOSCppm gain error. The effect of the source resistance on the two reference pins is additive with respect to this gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the IN) W U U 27 LTC2410 APPLICATIO S I FOR ATIO REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 22, 23, 24 and 25. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 60Hz notch), every 100Ω of source resistance driving REF+ or REF– translates into about 1.34ppm additional INL error. When FO = HIGH (internal oscillator and 50Hz notch), every 100Ω of source resistance driving REF+ or REF– translates into about 1.1ppm additional INL error. When FO is driven by an 0 VCC = 5V REF + = 5V REF – = GND IN + = 5V IN – = 2.5V FO = GND TA = 25°C –FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) –10 –20 –30 CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF 1 10 100 1k RSOURCE (Ω) 10k 100k 2410 F22 –40 –50 Figure 22. +FS Error vs RSOURCE at REF+ or REF– (Small CIN) 0 CREF = 0.01µF –FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) –90 –180 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C CREF = 0.1µF –270 –360 CREF = 1µF, 10µF –450 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 2410 F24 Figure 24. +FS Error vs RSOURCE at REF+ and REF– (Large CREF) 28 U external oscillator with a frequency fEOSC, every 100Ω of source resistance driving REF+ or REF– translates into about 8.73 • 10–6 • fEOSCppm additional INL error. Figure 26 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+ and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it. 50 CREF = 0.01µF CREF = 0.001µF 40 CREF = 100pF CREF = 0pF 30 VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = 2.5V FO = GND TA = 25°C 1 10 100 1k RSOURCE (Ω) 10k 100k 2410 F23 W U U 20 10 0 Figure 23. –FS Error vs RSOURCE at REF+ or REF– (Small CIN) 450 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C CREF = 1µF, 10µF 360 270 CREF = 0.1µF 180 CREF = 0.01µF 90 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 2410 F25 Figure 25. –FS Error vs RSOURCE at REF+ and REF– (Large CREF) LTC2410 APPLICATIO S I FOR ATIO 15 12 9 INL (ppm OF VREF) 6 3 0 –3 –6 –9 –12 –15 –0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10µF TA = 25°C REF– = GND 2410 F26 VINCM = 0.5 • (IN + + IN –) = 2.5V RSOURCE = 100Ω RSOURCE = 1000Ω RSOURCE = 500Ω Figure 26. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF) The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF+ and REF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maximum full-scale error. Output Data Rate When using its internal oscillator, the LTC2410 can produce up to 7.5 readings per second with a notch frequency of 60Hz (FO = LOW) and 6.25 readings per second with a notch frequency of 50Hz (FO = HIGH). The actual output U data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2410 output data rate can be increased as desired. The duration of the conversion phase is 20510/ fEOSC. If fEOSC = 153600Hz, the converter behaves as if the internal oscillator is used and the notch is set at 60Hz. There is no significant difference in the LTC2410 performance between these two operation modes. An increase in fEOSC over the nominal 153600Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2410’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2410 typical performance can be inferred from Figures 17, 18, 22 and 23 in which the horizontal axis is scaled by 153600/fEOSC. Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linear- W U U 29 LTC2410 APPLICATIO S I FOR ATIO ity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 27, 28, 29, 30, 31, 32, 33 and 34. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal Sinc4 digital filter and of the analog and digital autocalibration circuits determines the LTC2410 input bandwidth. When the internal oscillator is used with the notch set at 60Hz (FO = LOW), the 3dB input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz (FO = HIGH), the 3dB input bandwidth is 3.02Hz. If an external conversion clock generator of frequency fEOSC is connected to the FO pin, the 3dB input bandwidth is 0.236 • 10–6 • fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2410 input bandwidth is shown in Figure 35 for FO = LOW and FO = HIGH. When an external oscillator of frequency fEOSC is used, the shape of the LTC2410 input bandwidth can be derived from Figure 35, FO = LOW curve in which the horizontal axis is scaled by fEOSC/153600. The conversion noise (800nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 62.75nV√Hz for an infinite bandwidth source and 86.1nV√Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) –FS ERROR (ppm OF VREF) 30 U 500 450 400 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F27 W U U VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 85°C TA = 25°C Figure 27. Offset Error vs Output Data Rate and Temperature 7000 6000 5000 4000 3000 2000 TA = 25°C 1000 0 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = EXTERNAL OSCILLATOR TA = 85°C 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F28 Figure 28. +FS Error vs Output Data Rate and Temperature 0 –1000 –2000 –3000 –4000 –5000 –6000 –7000 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F29 TA = 85°C TA = 25°C Figure 29. –FS Error vs Output Data Rate and Temperature LTC2410 APPLICATIO S I FOR ATIO 24 23 22 RESOLUTION (BITS) 21 20 19 18 17 16 15 14 13 12 0 TA = 85°C VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F30 TA = 25°C RESOLUTION (BITS) Figure 30. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature 250 225 OFFSET ERROR (ppm OF VREF) 200 175 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F32 RESOLUTION (BITS) VCC = 5V REF + = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 25°C VREF = 5V VREF = 2.5V Figure 32. Offset Error vs Output Data Rate and Reference Voltage 22 INPUT SIGNAL ATTENUATION (dB) 20 RESOLUTION (BITS) 18 16 VREF = 2.5V 14 12 10 8 RESOLUTION = LOG2(VREF/INLMAX) VREF = 5V TA = 25°C VCC = 5V REF – = GND VINCM = 0.5 • REF + –0.5V • VREF < VIN < 0.5 • VREF FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F34 Figure 34. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage U 22 20 18 TA = 85°C 16 14 12 10 8 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V –2.5V < VIN < 2.5V FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F31 W U U RESOLUTION = LOG2(VREF/INLMAX) TA = 25°C Figure 31. Resolution (INLRMS ≤ 1LSB) vs Output Data Rate and Temperature 24 23 22 21 20 19 18 17 16 15 14 13 12 0 VCC = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 25°C RESOLUTION = LOG2(VREF/NOISERMS) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2410 F33 VREF = 5V VREF = 2.5V Figure 33. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 –6.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2410 F35 FO = HIGH FO = LOW Figure 35. Input Signal Bandwidth Using the Internal Oscillator 31 LTC2410 APPLICATIO S I FOR ATIO When external amplifiers are driving the LTC2410, the ADC input referred system noise calculation can be simplified by Figure 36. The noise of an amplifier driving the LTC2410 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 36, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni • √freqi. The total system noise (referred to the LTC2410 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2410 internal noise (800nV), the noise of the IN + driving amplifier and the noise of the IN – driving amplifier. If the FO pin is driven by an external oscillator of frequency fEOSC, Figure 36 can still be used for noise calculation if the x-axis is scaled by fEOSC/153600. For large values of the ratio fEOSC/153600, the Figure 36 plot accuracy begins to decrease, but in the same time the LTC2410 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2410 significantly simplifies antialiasing filter requirements. The Sinc4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2410’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048 • fOUTMAX where fN in the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode with a 50Hz notch setting, fS = 12800Hz and with a 60Hz notch setting fS = 15360Hz. In the external oscillator mode, fS = fEOSC/10. INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) 32 U 100 10 FO = LOW FO = HIGH 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2410 F36 W U U Figure 36. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2410 F37 FO = HIGH Figure 37. Input Normal Mode Rejection, Internal Oscillator and 50Hz Notch 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2410 F38 FO = LOW OR FO = EXTERNAL OSCILLATOR, fEOSC = 10 • fS Figure 38. Input Normal Mode Rejection, Internal Oscillator and 60Hz Notch or External Oscillator LTC2410 APPLICATIO S I FOR ATIO The combined normal mode rejection performance is shown in Figure 37 for the internal oscillator with 50Hz notch setting (FO = HIGH) and in Figure 38 for the internal oscillator with 60Hz notch setting (FO = LOW) and for the external oscillator mode. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 39 (rejection near DC) and Figure 40 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. The user can expect to achieve in practice this level of performance using the internal oscillator as it is demonstrated by Figures 41 and 42. Typical measured values of 0 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 2410 F39 Figure 39. Input Normal Mode Rejection 0 NORMAL MODE REJECTION (dB) NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2410 F41 Figure 41. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (60Hz Notch) U the normal mode rejection of the LTC2410 operating with an internal oscillator and a 60Hz notch setting are shown in Figure 41 superimposed over the theoretical calculated curve. Similarly, typical measured values of the normal mode rejection of the LTC2410 operating with an internal oscillator and a 50Hz notch setting are shown in Figure 42 superimposed over the theoretical calculated curve. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2410. If passive RC components are placed in front of the LTC2410, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2410 F40 W U U Figure 40. Input Normal Mode Rejection 0 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN(P-P) = 5V FO = GND TA = 25°C –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN(P-P) = 5V FO = 5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2410 F42 Figure 42. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch) 33 LTC2410 APPLICATIO S I FOR ATIO Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2410 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and LTC2410 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2410 has a full-scale differential input range of 5V peak-to-peak. Figures 43 and 44 show measurement results for the LTC2410 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 0 15 30 45 60 Figure 43. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2410 F44 Figure 44. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch) 34 U signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peak-to-peak (full scale) input signal. In Figure 43, the LTC2410 uses the internal oscillator with the notch set at 60Hz (FO = LOW) and in Figure 44 it uses the internal oscillator with the notch set at 50Hz (FO = HIGH). It is clear that the LTC2410 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. SYNCHRONIZATION OF MULTIPLE LTC2410s Since the LTC2410’s absolute accuracy (total unadjusted error) is 5ppm, applications utilizing multiple synchronized ADCs are possible. VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V FO = GND TA = 25°C 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2410 F43 W U U VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V FO = 5V TA = 25°C LTC2410 APPLICATIO S I FOR ATIO Simultaneous Sampling with Two LTC2410s One such application is synchronizing multiple LTC2410s, see Figure 45. The start of conversion is synchronized to the rising edge of CS. In order to synchronize multiple LTC2410s, CS is a common input to all the ADCs. To prevent the converters from autostarting a new conversion at the end of data output read, 31 or fewer SCK clock signals are applied to the LTC2410 instead of 32 (the 32nd falling edge would start a conversion). The exact timing and frequency for the SCK signal is not critical since it is only shifting out the data. In this case, two LTC2410’s simultaneously start and end their conversion cycles under the external control of CS. Increasing the Output Rate Using Mulitple LTC2410s A second application uses multiple LTC2410s to increase the effective output rate by 4 ×, see Figure 46. In this case, four LTC2410s are interleaved under the control of separate CS signals. This increases the effective output rate SCK2 SCK1 LTC2410 #1 VCC REF + µCONTROLLER REF – IN + IN – GND CS SDO1 SDO2 VREF+ VREF – CS FO SCK SDO CS LTC2410 #2 VCC REF + REF – IN + IN – GND FO SCK SDO CS EXTERNAL OSCILLATOR (153,600HZ) SCK1 31 OR LESS CLOCK CYCLES SCK2 31 OR LESS CLOCK CYCLES SDO1 SDO2 2410 F45 Figure 45. Synchronous Conversion—Extendable U from 7.5Hz to 30Hz (up to a maximum of 60Hz). Additionally, the one-shot output spectrum is unfolded allowing further digital signal processing of the conversion results. SCK and SDO may be common to all four LTC2410s. The four CS rising edges equally divide one LTC2410 conversion cycle (7.5Hz for 60Hz notch frequency). In order to synchronize the start of conversion to CS, 31 or less SCK clock pulses must be applied to each ADC. Both the synchronous and 4 × output rate applications use the external serial clock and single cycle operation with reduced data output length (see Serial Interface Timing Modes section and Figure 6). An external oscillator clock is applied commonly to the FO pin of each LTC2410 in order to synchronize the sampling times. Both circuits may be extended to include more LTC2410s. W U U 35 LTC2410 APPLICATIO S I FOR ATIO U VREF+ VREF – EXTERNAL OSCILLATOR (153,600HZ) LTC2410 #2 FO SCK SDO CS VCC REF + REF – IN + IN – GND FO SCK SDO CS LTC2410 #3 VCC REF + REF – IN + IN – GND FO SCK SDO CS LTC2410 #4 VCC REF + REF – IN + IN – GND FO SCK SDO CS 2410 F46 LTC2410 #1 VCC REF + REF – IN + IN – µCONTROLLER SCK SDO CS1 CS2 CS3 CS4 GND CS1 CS2 CS3 CS4 31 OR LESS CLOCK PULSES SCK SDO Figure 46. Using Multiple LTC2410s to Increase Output Data Rate BRIDGE APPLICATIONS Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2410 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be limited to 5V. This gives only 10mV full scale input signal, which can be resolved to 1 part in 10000 without averaging. For many solid state sensors, this is still better than the sensor. Averaging 64 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 80000, comparable to better weighing systems. Hysteresis and creep effects in the load cells are typically much greater than this. Most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually 36 W U U not an issue. For those systems that require accurate measurement of a small incremental change on a significant tare weight, the lack of history effects in the LTC2400 family is of great benefit. For those applications that cannot be fulfilled by the LTC2410 alone, compensating for error in external amplification can be done effectively due to the “no latency” feature of the LTC2410. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. Correlated double sampling involves alternating the polarity of excitation and dealing with the reversal of input polarity mathematically. Alternatively, bridge excitation can be increased to as much as ±10V, if one of several precision attenuation LTC2410 APPLICATIO S I FOR ATIO techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2410 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 52 and 53. Figure 47 shows an example of a simple bridge connection. Note that it is suitable for any bridge application where measurement speed is not of the utmost importance. For many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. Often, large weighing applications involve load cells located at each load bearing point, the output of which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the ADC, or can be digitized via multiple ADC channels and summed mathematically. The mathematical summation of the output of multiple LTC2410’s provides the benefit of a root square reduction in noise. The low power consumption of the LTC2410 makes it attractive for multidrop communication schemes where the ADC is located within the load-cell housing. A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection LT1019 + R1 3 350Ω BRIDGE 4 5 REF + REF IN + LTC2410 6 R2 IN – GND FO 14 – 2 VREF SDO SCK CS 12 13 11 1, 7, 8, 9, 10, 15, 16 2410 F47 R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS Figure 47. Simple Bridge Connection U devices, RFI suppression and wiring. The LTC2410 exhibits extremely low temperature dependent drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all become factors. The circuit in Figure 48 shows an example of a simple amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as determined by the bridge. The use of a true three amplifier instrumentation amplifier is not necessary, as the LTC2410 has common mode rejection far beyond that of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 15 before its input referred noise dominates the LTC2410 noise. This example shows a gain of 34, that is determined by a feedback network built using a resistor array containing 8 individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal gradients. The second LTC1051 buffers the low noise input stage from the transient load steps produced during conversion. The gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor matching. A gain of 34 may seem low, when compared to common practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2410 changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. At a gain of 100, the gain error that could result from typical open-loop gain of 160dB is –1ppm, however, worst-case is at the minimum gain of 116dB, giving a gain error of –158ppm. Worst-case gain error at a gain of 34, is –54ppm. The use of the LTC1051A reduces the worstcase gain error to –33ppm. The advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement1 and gain accuracy is potentially compromised. Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in the output stage that usually dominates when an instru- W U U 37 LTC2410 APPLICATIO S I FOR ATIO mentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.1µVRMS. The buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity. Figure 49 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. If the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the bridge can be made to act in conjunction with the feedback resistor to determine the gain. If the feedback resistor is incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. The common mode voltage in this case, is again a function of the bridge output. Differential gain as used with a 350Ω bridge is AV = (R1+ R2)/(R1+175Ω). Common mode gain is half the differential gain. The maximum differential signal that can be used is 1/4 VREF, as opposed to 1/2 VREF in the 2-amplifier topology above. 5V 3 + – 8 U1A 1 2 0.1µF 5V 8 U2A 1 3 4 4 5 REF + REF – IN + LTC2410 U2B 5 7 6 IN – GND FO 14 VCC SDO SCK CS 2 12 13 11 0.1µF 2 350Ω BRIDGE 1 RN1 16 6 4 15 14 4 5 12 11 2 6 7 10 3 – U1B 7 5 + RN1 = 5k × 8 RESISTOR ARRAY U1A, U1B, U2A, U2B = 1/2 LTC1051 Figure 48. Using Autozero Amplifiers to Reduce Input Referred Noise 38 U Remote Half Bridge Interface As opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. Applications include RTD’s, thermistors and other resistive elements that undergo significant changes over their span. For single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 50. The LTC2410 can accept inputs up to 1/2 VREF. Hence, the reference resistor R1 must be at least 2x the highest value of the variable resistor. In the case of 100Ω platinum RTD’s, this would suggest a value of 800Ω for R1. Such a low value for R1 is not advisable due to self-heating effects. A value of 25.5k is shown for R1, reducing self-heating effects to acceptable levels for most sensors. The basic circuit shown in Figure 50 shows connections for a full 4-wire connection to the sensor, which may be located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the 1Input referred noise for A = 34 for approximately 0.05µV V RMS, whereas at a gain of 50, it would be 0.048µVRMS. W U U 5VREF 0.1µF – + 3 8 9 13 6 – + 1, 7, 8, 9, 10, 15, 16 2410 F48 LTC2410 APPLICATIO S I FOR ATIO reference inputs do not have the same rejection. If 60Hz or other noise is present on the reference input, a low pass filter is recommended as shown in Figure 51. Note that you cannot place a large capacitor directly at the junction of R1 and R2, as it will store charge from the sampling process. A better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (R3). The use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. If, for example, a 25k reference resistor is used to set the excitation current with a 100Ω RTD, the negative reference input is sampling the same external node as the positive input and may result in errors if used with a long cable. For short cable applications, the errors may be acceptalby low. If instead the single 25k resistor is replaced with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at higher frequencies, will be reduced. A filter can be introduced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. The reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the LSB, although, not the input referred noise level. 350Ω BRIDGE 3 2 + 1µF R1 4.99k AV = 9.95 = ( R1 + R2 R1 + 175Ω Figure 49. Bridge Amplification Using a Single Amplifier U The circuit shown in Figure 51 shows a more rigorous example of Figure 50, with increased noise suppression and more protection for remote applications. Figure 52 shows an example of gain in the excitation circuit and remote feedback from the bridge. The LTC1043’s provide voltage multiplication, providing ±10V from a 5V reference with only 1ppm error. The amplifiers are used at unity gain and introduce very little error due to gain error or due to offset voltages. A 1µV/°C offset voltage drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. Note that the amplifiers must have high open-loop gain or gain error will be a source of error. The fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. Note that the gain of a device such as an LF156, (25V/mV over temperature) will produce a worst-case error of –180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce –10V from a 5V reference. 10µF 5V 0.1µV 3 6 175Ω 1µF R2 46.4k 20k 6 4 REF + REF – IN + LTC2410 IN – GND 1, 7, 8, 9, 10, 15, 16 2 VCC W U U + 5V 0.1µF + – 7 LTC1050S8 4 + 20k 5 ) 2410 F49 39 LTC2410 APPLICATIO S I FOR ATIO The error associated with the 10V excitation would be –80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. Figure 53 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. The circuit is configured to provide 10V and –5V excitation to the bridge, producing a common mode voltage at the input to the LTC2410 of 2.5V, maximizing the AC input range for applications where induced 60Hz could reach amplitudes up to 2VRMS. The last two example circuits could be used where multiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2410, via an inexpensive multiplexer such as the 74HC4052. PLATINUM 100Ω RTD Figure 50. Remote Half Bridge Interface 5V R2 10k 0.1% R1 10k, 5% R3 10k 5% PLATINUM 100Ω RTD Figure 51. Remote Half Bridge Sensing with Noise Suppression on Reference 40 U Figure 54 shows the use of an LTC2410 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. Although the bridge output may be within the input range of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance. VS 2.7V TO 5.5V 2 R1 25.5k 0.1% 3 4 REF + REF – LTC2410 5 6 IN + IN – GND 1, 7, 8, 9, 10, 15, 16 2410 F50 W U U VCC 5V 2 3 560Ω 4 REF + REF – LTC2410 10k 10k 5 6 IN + IN – GND 1, 7, 8, 9, 10, 15, 16 2410 F51 + 1µF LTC1050 VCC – LTC2410 APPLICATIO S I FOR ATIO U 15V U1 4 LTC1043 10V 1µF 200Ω 8 11 7 47µF 5V 15V Q1 2N3904 20Ω 6 LTC1150 4 33Ω 1k 350Ω BRIDGE 10V 0.1µF –10V 33Ω Q2 2N3906 6 20Ω –15V LTC1150 4 –15V 0.1µF 1k Figure 52. LTC1043 Provides Precise 4X Reference for Excitation Voltages W 7 7 U U 15V + – 3 + LT1236-5 10V + 2 0.1µF * 12 14 17 0.1µF 2 VCC LTC2410 3 4 5 6 REF + REF – IN + IN – GND 6 2 1, 7, 8, 9, 10, 15, 16 5V 13 10µF –15V + 15V U2 LTC1043 + – 3 5 2 * 3 15 18 *FLYING CAPACITORS ARE 1µF FILM (MKP OR EQUIVALENT) SEE LTC1043 DATA SHEET FOR DETAILS ON UNUSED HALF OF U1 U2 LTC1043 8 11 5V 4 7 1µF FILM 200Ω –10V * 12 14 17 –10V 2410 F52 13 41 LTC2410 APPLICATIO S I FOR ATIO 15V Q1 2N3904 22Ω 20Ω RN1 10k 10V 350Ω BRIDGE TWO ELEMENTS VARYING 1 2 5V 3 4 RN1 10k 3 4 5 –5V 8 RN1 10k 5 6 7 RN1 10k 6 REF + REF – IN + IN – GND 1, 7, 8, 9, 10, 15, 16 2 VCC LTC2410 33Ω ×2 Q2, Q3 2N3906 ×2 20Ω 7 –15V Figure 53. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier 5V TO OTHER DEVICES Figure 54. Use a Differential Multiplexer to Expand Channel Capability 42 U + 1 C1 0.1µF 1/2 LT1112 3 5V W U U + 2 LT1236-5 C3 47µF C1 0.1µF – C2 0.1µF 15V RN1 IS CADDOCK T914 10K-010-02 8 – + 6 1/2 LT1112 4 –15V 5 2410 F53 5V 16 12 14 15 11 1 5 2 4 8 9 10 6 13 3 74HC4052 5 6 + 47µF 3 4 REF + REF – 2 VCC LTC2410 IN + IN – GND 1, 7, 8, 9, 10, 15, 16 A0 A1 2410 F54 LTC2410 TYPICAL APPLICATIO S Sample Driver for LTC2410 SPI Interface The LTC2410 has a very simple serial interface that makes interfacing to microprocessors and microcontrollers very easy. The listing in Figure 56 is a simple assembler routine for the 68HC11 microcontroller. It uses PORT D, configuring it for SPI data transfer between the controller and the LTC2410. Figure 55 shows the simple 3-wire SPI connection. The code begins by declaring variables and allocating four memory locations to store the 32-bit conversion result. This is followed by initializing PORT D’s SPI configuration. The program then enters the main sequence. It activates the LTC2410’s serial interface by setting the SS output low, sending a logic low to CS. It next waits in a loop for a logic low on the data line, signifying end-of-conversion. After the loop is satisfied, four SPI transfers are completed, retrieving the conversion. The main sequence ends by setting SS high. This places the LTC2410’s serial interface in a high impedance state and initiates another conversion. The performance of the LTC2410 can be verified using the demonstration board DC291A, see Figure 57 for the schematic. This circuit uses the computer’s serial port to generate power and the SPI digital signals necessary for starting a conversion and reading the result. It includes a Labview application software program (see Figure 58) which graphically captures the conversion results. It can be used to determine noise performance, stability and with an external source, linearity. As exemplified in the schematic, the LTC2410 is extremely easy to use. This demonstration board and associated software is available by contacting Linear Technology. Figure 55. Connecting the LTC2410 to a 68HC11 MCU Using the SPI Serial Interface U LTC2410 SCK SDO CS 13 12 11 68HC11 SCK (PD4) MISO (PD2) SS (PD5) 2410 F55 43 LTC2410 TYPICAL APPLICATIO S ***************************************************** * This example program transfers the LTC2410's 32-bit output * * conversion result into four consecutive 8-bit memory locations. * ***************************************************** *68HC11 register definition PORTD EQU $1008 Port D data register * " – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD" DDRD EQU $1009 Port D data direction register SPSR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, – ,MODF; – , – , – , – " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC2410's 32 conversion result * DIN1 EQU $00 This memory location holds the LTC2410's bits 31 - 24 DIN2 EQU $01 This memory location holds the LTC2410's bits 23 - 16 DIN3 EQU $02 This memory location holds the LTC2410's bits 15 - 08 DIN4 EQU $03 This memory location holds the LTC2410's bits 07 - 00 * ********************** * Start GETDATA Routine * ********************** * ORG $C000 Program start location INIT1 LDS #$CFFF Top of C page RAM, beginning location of stack LDAA #$2F –,–,1,0;1,1,1,1 * –, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 –,–,1,1;1,0,0,0 STAA DDRD SS*, SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs *DDRD's bit 5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2 * (This assumes an E-Clock frequency of 4MHz. For higher E* Clock frequencies, change the above value of $50 to a value * that ensures the SCK frequency is 2MHz or less.) GETDATA PSHX PSHY PSHA LDX #$0 The X register is used as a pointer to the memory locations * that hold the conversion data LDY #$1000 BCLR PORTD, Y %00100000 This sets the SS* output bit to a logic * low, selecting the LTC2410 * 44 U LTC2410 TYPICAL APPLICATIO S ********************************** * The next short loop waits for the * * LTC2410's conversion to finish before * * starting the SPI data transfer * ********************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2410's conversion is not * complete * Bit 2 = Lo; the LTC2410's conversion is complete BNE CONVEND Branch to the loop's beginning while bit 2 remains high * * ******************** * The SPI data transfer * ******************** * TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer STAA SPDR This writes the byte in the SPI data register and starts * the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR's MSB * and is set to one at the end of an SPI transfer. The branch * will occur while SPIF is a zero. LDAA SPDR Load accumulator A with the current byte of LTC2410 data that was just received STAA 0,X Transfer the LTC2410's data to memory INX Increment the pointer CPX #DIN4+1 Has the last byte been transferred/exchanged? BNE TRFLP1 If the last byte has not been reached, then proceed to the * next byte for transfer/exchange BSET PORTD,Y %00100000 This sets the SS* output bit to a logic high, * de-selecting the LTC2410 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 56. This is an Example of 68HC11 Code That Captures the LTC2410’s Conversion Results Over the SPI Serial Interface Shown in Figure 55 U 45 LTC2410 TYPICAL APPLICATIO S VCC JP1 JUMPER 1 3 2 U1 LT1460ACN8-2.5 6 VOUT VIN GND C1 4 2 VCC JP2 JUMPER 1 2 U2 LT1236ACN8-5 6 VOUT VIN GND C3 4 10µF 35V 2 R1 10Ω D1 BAV74LT1 2 3 1 1 C4 100µF 16V 1 U3E 74HC14 10 VCC J3 BANANA JACK J4 1 VEXT BANANA JACK J6 1 REF + BANANA JACK J7 1 REF – BANANA JACK J8 1 VIN+ BANANA JACK J9 1 VIN – BANANA JACK J10 1 GND 1 2 JP5 JUMPER NOTES: INSTALL JUMBER JP1 AT PIN 1 AND PIN 2 INSTALL JUMBER JP2 AT PIN 1 AND PIN 2 INSTALL JUMBER JP3 AT PIN 1 AND PIN 2 VCC J5 GND 1 1 C6 0.1µF JP4 JUMPER 1 3 2 2 VCC REF + REF – VIN+ 11 CS FO SCK 4 14 13 U3C 74HC14 5 6 9 R7 22k R8 51k VCC BYPASS CAP FOR U3 C7 0.1µF 2410 F57 + 10µF 35V R2 3Ω JP3 JUMPER 1 3 2 46 U 1 J1 VEXT J2 GND P1 DB9 6 + C2 22µF 25V + + U3F 74HC14 11 12 13 R3 51k 2 7 3 8 4 9 + C5 10µF 35V U3B 74HC14 3 2 U3A 74HC14 1 5 R4 51k 3 4 5 6 12 SDO 16 U4 GND VIN – LTC2410CGN 15 GND 10 GND GND GND GND GND 1 7 8 9 U3D 74HC14 8 R5 49.9Ω 1 3 2 R6 3k Q1 MMBT3904LT1 Figure 57. 24-Bit A/D Demo Board Schematic Figure 58. Display Graphic LTC2410 PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.016 – 0.050 (0.406 – 1.270) 0° – 8° TYP 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 0.053 – 0.068 (1.351 – 1.727) 0.004 – 0.0098 (0.102 – 0.249) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1 23 4 56 7 8 GN16 (SSOP) 1098 PCB LAYOUT A D FIL Silkscreen Top Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. W Top Layer U 47 LTC2410 PCB LAYOUT A D FIL W Bottom Layer COMMENTS 3ppm/°C Drift, 0.05% Max 80µA Supply Current, 0.5°C Initial Accuracy Precise Charge, Balanced Switching, Low Power No External Components 5µV Offset, 1.6µVP-P Noise 0.05% Max, 5ppm/°C Drift 0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 1.45µVRMS Noise, 4ppm INL Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408 sn2410 2410fs LT/TP 1100 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2000 RELATED PARTS PART NUMBER LT1019 LT1025 LTC1043 LTC1050 LT1236A-5 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2411 LTC2413 LTC2420 LTC2424/LTC2428 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Micropower Thermocouple Cold Junction Compensator Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference 24-Bit, No Latency ∆Σ ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 24-Bit, No Latency ∆Σ ADC in MSOP 24-Bit, No Latency ∆Σ ADC 20-Bit, No Latency ∆Σ ADC in SO-8 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs 48 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U