LTC2420I

Final Electrical Specifications LTC2420 20-Bit µPower No Latency ∆Σ ADC in SO-8 TM January 2000 FEATURES s s s s s s DESCRIPTIO s s s s s s s s 20-Bit ADC in SO-8 Package 8ppm INL, No Missing Codes at 20 Bits 4ppm Full-Scale Error 0.5ppm Offset 1.2ppm Noise Digital Filter Settles in a Single Cycle. Each Conversion Is Accurate, Even After an Input Step. Internal Oscillator—No External Components Required Fast Mode: 16-Bit Noise, 12 Bits TUE at 100sps 110dB Min, 50Hz/60Hz Notch Filter Reference Input Voltage: 0.1V to VCC Live Zero—Extended Input Range Accommodates 12.5% Overrange and Underrange Single Supply 2.7V to 5.5V Operation Low Supply Current (200µA) and Auto Shutdown Pin Compatible with 24-Bit LTC2400 The LTC®2420 is a micropower 20-bit A/D converter with an integrated oscillator, 8ppm INL and 1.2ppm RMS noise that operates from 2.7V to 5.5V. It uses delta-sigma technology and provides a digital filter that settles in a single cycle for multiplexed applications. Through a single pin, the LTC2420 can be configured for better than 110dB rejection at 50Hz or 60Hz ± 2%, or it can be driven by an external oscillator for a user-defined rejection frequency in the range 1Hz to 800Hz. The internal oscillator requires no external frequency setting components. The converter accepts any external reference voltage from 0.1V to VCC. With its extended input conversion range of –12.5% VREF to 112.5% VREF, the LTC2420 smoothly resolves the offset and overrange problems of preceding sensors or signal conditioning circuits. The LTC2420 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. APPLICATIO S s s s s s s s s Weight Scales Direct Temperature Measurement Gas Analyzers Strain-Gage Transducers Instrumentation Data Acquisition Industrial Process Control 4-Digit DVMs TYPICAL APPLICATIO 2.7V TO 5.5V 1µF 1 VCC LTC2420 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE –0.12VREF TO 1.12VREF 2 VREF SCK 7 FO 8 Total Unadjusted Error vs Output Code 10 TOTAL UNADJUSTED ERROR (ppm) 8 6 4 2 0 –2 –4 –6 –8 –10 0 VCC = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 3 4 VIN GND SDO CS 6 5 3-WIRE SPI INTERFACE 2420 TA01 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U VCC = 5V VREF = 5V TA = 25°C FO = LOW 524,288 OUTPUT CODE (DECIMAL) 1,048,575 2420 TA02 U U 1 LTC2420 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PACKAGE/ORDER INFORMATION TOP VIEW VCC 1 VREF 2 VIN 3 GND 4 8 7 6 5 FO SCK SDO CS Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2420C ............................................... 0°C to 70°C LTC2420I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC2420CS8 LTC2420IS8 S8 PART MARKING 2420 2420I S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 130°C/W Consult factory for Military grade parts. CONVERTER CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) CONDITIONS 0.1V ≤ VREF ≤ VCC, (Note 5) VREF = 2.5V (Note 6) VREF = 5V (Note 6) VREF = 5V, VREF = 2.5V, 100 Samples/Second, fO = 2.048MHz 2.5V ≤ VREF ≤ VCC 2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz 2.5V ≤ VREF ≤ VCC 2.5V ≤ VREF ≤ VCC 2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz 2.5V ≤ VREF ≤ VCC VREF = 2.5V VREF = 5V VIN = 0V (Note 13) VREF = 5V, 100 Samples/Second, fO = 2.048MHz (Note 7) (Note 8) VREF = 2.5V, VIN = 0V VREF = 2.5V, VIN = 0V, (Note 7) VREF = 2.5V, VIN = 0V, (Note 8) q q q q q q q q PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Integral Nonlinearity (Fast Mode) Offset Error Offset Error (Fast Mode) Offset Error Drift Full-Scale Error Full-Scale Error (Fast Mode) Full-Scale Error Drift Total Unadjusted Error Output Noise Output Noise (Fast Mode) Normal Mode Rejection 60Hz ± 2% Normal Mode Rejection 50Hz ± 2% Power Supply Rejection, DC Power Supply Rejection, 60Hz ± 2% Power Supply Rejection, 50Hz ± 2% MIN 20 TYP 4 8 40 0.5 3 0.04 4 10 0.04 8 16 6 20 MAX 10 20 250 10 UNITS Bits ppm of VREF ppm of VREF ppm of VREF ppm of VREF ppm of VREF ppm of VREF/°C 10 ppm of VREF ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF µVRMS µVRMS dB dB dB dB dB 110 110 130 130 100 110 110 2 U W U U WW W U LTC2420 A ALOG I PUT A D REFERE CE SYMBOL VIN VREF CS(IN) CS(REF) IIN(LEAK) IREF(LEAK) PARAMETER Input Voltage Range Reference Voltage Range Input Sampling Capacitance Reference Sampling Capacitance Input Leakage Current Reference Leakage Current CS = VCC The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS (Note 14) q q VREF = 2.5V, CS = VCC DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK High-Z Output Leakage SDO (Note 9) IO = – 800µA IO = 1.6mA IO = – 800µA (Note 10) IO = 1.6mA (Note 10) CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN q q q q q q 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.3V (Note 9) 4.5V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 5.5V (Note 9) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Note 9) POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS q CS = 0V (Note 12) CS = VCC (Note 12) U UW U U U U U MIN – 0.125 • VREF 0.1 TYP MAX 1.125 • VREF VCC UNITS V V pF pF 1 1.5 q q – 100 – 100 1 1 100 100 nA nA TYP MAX UNITS V V 2.5 2.0 0.8 0.6 2.5 2.0 0.8 0.6 –10 –10 10 10 10 10 V V V V V V µA µA pF pF V q q q q q VCC – 0.5 0.4 VCC – 0.5 0.4 –10 10 V V V µA MIN 2.7 TYP MAX 5.5 UNITS V µA µA q q 200 20 300 30 3 LTC2420 TI I G CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time F O = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9) q q q q q q q q The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS 20-Bit Effective Resolution 12-Bit Effective Resolution q q q q q q q fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: All voltages are with respect to GND. VCC = 2.7 to 5.5V unless otherwise specified. RSOURCE = 0Ω. Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ± 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ± 2% (external oscillator). 4 UW MIN 2.56 2.56 0.5 0.5 TYP MAX 307.2 2.048 390 390 UNITS kHz MHz µs µs ms ms ms kHz kHz 130.66 133.33 136 156.80 160 163.20 20480/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.23 1.25 1.28 192/fEOSC (in kHz) 24/fESCK (in kHz) 0 0 0 50 200 15 50 50 150 150 150 55 2000 Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time CS ↓ to SDO Low Z CS ↑ to SDO High Z CS ↓ to SCK ↓ CS ↓ to SCK ↑ SCK ↓ to SDO Valid SDO Hold After SCK ↓ SCK Set-Up Before CS ↓ SCK Hold After CS ↓ % kHz ns ns ms ms ms ns ns ns ns ns ns ns ns (Note 10) (Note 9) (Note 5) q q q q q q Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: For reference voltage values VREF > 2.5V the extended input of – 0.125 • VREF to 1.125 • VREF is limited by the absolute maximum rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤ 0.267V + 0.89 • VCC the input voltage range is – 0.3V to 1.125 • VREF. For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is – 0.3V to VCC + 0.3V. LTC2420 PIN FUNCTIONS VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin 4) with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. VREF (Pin 2): Reference Input. The reference voltage range is 0.1V to VCC. VIN (Pin 3): Analog Input. The input voltage range is – 0.125 • VREF to 1.125 • VREF. For VREF > 2.5V the input voltage range may be limited by the pin absolute maximum rating of – 0.3V to VCC + 0.3V. GND (Pin 4): Ground. Shared pin for analog ground, digital ground, reference ground and signal ground. Should be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single point grounding system. CS (Pin 5): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A LOW-to-HIGH transition on this pin disables the SDO digital output. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 6): Three-State Digital Output. During the data output period this pin is used for serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock mode is determined by the level applied to SCK at power up and the falling edge of CS. FO (Pin 8): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter’s first null is located at 50Hz. When the FO pin is connected to GND (FO = OV) the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560. APPLICATIO S I FOR ATIO The LTC2420 is pin compatible with the LTC2400. The two devices are designed to allow the user to incorporate either device in the same design with no modifications. While the LTC2420 output word length is 24 bits (as opposed to the 32-bit output of the LTC2400), its output clock timing can be identical to the LTC2400. As shown in Figure 1, the LTC2420 data output is concluded on the falling edge of the 24th serial clock (SCK). In order to maintain drop-in compatibility with the LTC2400, it is possible to clock the LTC2420 with an additional 8 serial clock pulses. This results in 8 additional output bits which are always logic HIGH. U W U U U U U Output Data Format The LTC2420 serial output data stream is 24 bits long. The first 4 bits represent status information indicating the sign, input range and conversion state. The next 20 bits are the conversion result, MSB first. Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. 5 LTC2420 APPLICATIO S I FOR ATIO CS SCK SDO EOC = 1 EOC = 0 CONVERSION SLEEP Figure 1. LTC2420 Compatible Timing with the LTC2400 Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is VREF or VIN < 0, this bit is HIGH. The function of these bits is summarized in Table 1. Table 1. LTC2420 Status Bits Input Range VIN > VREF 0 < VIN ≤ VREF VIN = 0+/0 – VIN < 0 Bit 23 EOC 0 0 0 0 Bit 22 DMY 0 0 0 0 Bit 21 SIG 1 1 1/0 0 Bit 20 EXR 1 0 0 1 Bit 19 (fifth output bit) is the most significant bit (MSB). Bits 19-0 are the 20-bit conversion result MSB first. Bit 0 is the least significant bit (LSB). Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 2. Whenever CS is HIGH, SDO remains high impedance and any SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising 6 U 8 8 8 8 (OPTIONAL) DATA OUT 4 STATUS BITS 20 DATA BITS CONVERSION EOC = 1 LAST 8 BITS ALWAYS 1 DATA OUTPUT 2420 F01 W U U edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the VIN pin is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from – 0.125 • VREF to 1.125 • VREF. For input voltages greater than 1.125 • VREF, the conversion result is clamped to the value corresponding to 1.125 • VREF. For input voltages below – 0.125 • VREF, the conversion result is clamped to the value corresponding to – 0.125 • VREF. Operation at Higher Data Output Rates The LTC2420 typically operates with an internal oscillator of 153.6kHz. This corresponds to a notch frequency of 60Hz and an output rate of 7.5 samples/second. The internal oscillator is enabled if the FO pin is logic LOW (logic HIGH for a 50Hz notch). It is possible to drive the FO pin with an external oscillator for higher data output rates. As shown in Figure 3, an external clock of 2.048MHz applied to the FO pin results in a notch frequency of 800Hz with a data output rate of 100 samples/second. Figure 4 shows the total unadjusted error (Offset Error + Full-Scale Error + INL + DNL) as a function of the output data rate with a 5V reference. The relationship between the LTC2420 APPLICATIO S I FOR ATIO CS BIT 23 SDO Hi-Z EOC BIT 22 “0” BIT 21 SIG SCK 1 SLEEP 2 3 Figure 2. Output Data Timing Table 2. LTC2420 Output Data Format Input Voltage VIN > 9/8 • VREF 9/8 • VREF VREF + 1LSB VREF 3/4VREF + 1LSB 3/4VREF 1/2VREF + 1LSB 1/2VREF 1/4VREF + 1LSB 1/4VREF 0+/0 – –1LSB –1/8 • VREF VIN < –1/8 • VREF Bit 23 EOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 22 DMY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 21 SIG 1 1 1 1 1 1 1 1 1 1 1/0* 0 0 0 Bit 20 EXR 1 1 1 0 0 0 0 0 0 0 0 1 1 1 Bit 19 MSB 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Bit 18 0 0 0 1 1 0 0 1 1 0 0 1 1 1 Bit 17 0 0 0 1 0 1 0 1 0 1 0 1 1 1 Bit 16 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Bit 15 1 1 0 1 0 1 0 1 0 1 0 1 0 0 … ... ... ... ... ... ... ... ... ... ... ... ... ... ... Bit 0 LSB 1 1 0 1 0 1 0 1 0 1 0 1 0 0 *The sign bit changes state during the 0 code. 256 VREF = 5V 12 BITS TOTAL UNADJUSTED ERROR (ppm) 800Hz NOTCH (100 SAMPLES/SECOND) 60Hz NOTCH (7.5 SAMPLES/SECOND) 1 2 3 4 LTC2420 VCC VREF VIN GND FO SCK SDO CS 8 7 6 5 EXTERNAL 2.048MHz CLOCK SOURCE 2420 F03 INTERNAL 153.6kHz OSCILLATOR Figure 3. Selectable 100 Samples/Second Turbo Mode U BIT 20 EXT BIT 19 MSB BIT 4 BIT 0 LSB20 4 5 19 20 24 CONVERSION 2420 F02 W U U DATA OUTPUT 224 192 160 128 96 14 BITS 64 32 0 0 50 100 16 BITS 150 2420 F04 13 BITS OUTPUT RATE (SAMPLES/SEC) Figure 4. Total Error vs Output Rate (VREF = 5V) 7 LTC2420 APPLICATIO S I FOR ATIO ODR = FO/20480 output data rate (ODR) and the frequency applied to the FO pin (FO) is: For output data rates up to 50 samples/second, the total unadjusted error (TUE) is better than 16 bits, and better than 12 bits at 100 samples/second. As shown in Figure 5, for output data rates of 100 samples/second, the TUE is better than 15 bits for VREF below 2.5V. Figure 6 shows an unaveraged total unadjusted error for the LTC2420 operating at 100 samples/second with VREF = 2.5V. Figure 7 shows the same device operating with a 5V reference and an output data rate of 7.5 samples/second. 256 OUTPUT RATE = 100sps 12 BITS TOTAL UNADJUSTED ERROR (ppm) TOTAL UNADJUSTED ERROR (ppm) 224 192 160 128 96 64 32 0 1.0 1.5 14 BITS 15 BITS 13 BITS 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) 4.5 5.0 2420 F05 Figure 5. Total Error vs VREF (Output Rate = 100sps) 6 TOTAL UNADJUSTED ERROR (ppm) 4 2 0 –2 –4 –6 –8 –10 0 INPUT VOLTAGE (V) Figure 7. Total Unadjusted Error at 7.5 Samples/Second (No Averaging) 8 U At 100 samples/second, the LTC2420 can be used to capture transient data. This is useful for monitoring settling or auto gain ranging in a system. The LTC2420 can monitor signals at an output rate of 100 samples/second. After acquiring 100 samples/second data the FO pin may be driven LOW enabling 60Hz rejection to 110dB and the highest possible DC accuracy. The no latency architecture of the LTC2420 allows consecutive readings (one at 100 samples/second the next at 7.5 samples/second) without interaction between the two readings. 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 0 INPUT VOLTAGE (V) 2420 F06 W U U VCC = 5V VREF = 2.5V 2.5 Figure 6. Total Unadjusted Error at 100 Samples/Second (No Averaging) VCC = 5V VREF = 5V 5 2420 F07 LTC2420 APPLICATIO S I FOR ATIO As shown in Figure 8, the LTC2420 can capture transient data with 90dB of dynamic range (with a 300mVP-P input signal at 2Hz). The exceptional DC performance of the LTC2420 enables signals to be digitized independent of a 0.20 ADC OUTPUT (NORMALIZED TO VOLTS) 500ms 0.15 0.10 fIN = 2Hz MAGNITUDE (dB) 0.05 0 –0.05 –0.10 –0.15 –0.20 TIME 2420 F08a 8a. Digitized Waveform Figure 8. Transient Signal Acquisiton 2.20 ADC OUTPUT (NORMALIZED TO VOLTS) VIN = 300mVP-P + 2V DC 2.15 2.10 MAGNITUDE (dB) 2.05 2.00 1.95 1.90 1.85 1.80 TIME 2420 F09a 9a. Digitized Waveform with 2V DC Offset 0.20 ADC OUTPUT (NORMALIZED TO VOLTS) VIN = 300mVP-P + 0V DC 0.15 0.10 MAGNITUDE (dB) 0.05 0.00 –0.05 –0.10 –0.15 –0.20 TIME 2420 F09c 9c. Digitized Waveform with No Offset Figure 9. Using the LTC2420’s High Accuracy Wide Dynamic Range to Digitize a 300mVP-P 15Hz Waveform with a Large DC Offset (VCC = 5V, VREF = 5V) U large DC offset. Figures 9a and 9b show the dynamic performance with a 15Hz signal superimposed on a 2V DC level. The same signal with no DC level is shown in Figures 9c and 9d. 0 –20 –40 –60 –80 2Hz 100sps 0V OFFSET –100 –120 FREQUENCY (Hz) 2420 F08b W U U 8b. Output FFT 0 –20 –40 –60 –80 15Hz 100sps 2V OFFSET –100 –120 FREQUENCY (Hz) 2420 F09b 9b. FFT Waveform with 2V DC Offset 0 –20 –40 –60 –80 15Hz 100sps 0V OFFSET –100 –120 FREQUENCY (Hz) 2420 F09d 9d. FFT Waveform with No Offset 9 LTC2420 APPLICATIO S I FOR ATIO Single-Chip Instrumentation Amplifier for the LTC2420 The circuit in Figure 10 is a simple solution for processing differential signals in pressure transducer, weigh scale or strain gauge applications that can operate on a supply voltage range of ±5V to ±15V. The circuit uses an LT®1920 single-chip instrumentation amplifier to perform a differential to single-ended conversion. The amplifier’s output voltage is applied to the LTC2420’s input and converted to a digital value with an overall accuracy exceeding 17 bits (0.0008%). Key circuit performance results are shown in Table 3. The practical gain range for this topology as shown is from 5 to 100 because the LTC2420’s wide dynamic range makes gains below 5 virtually unnecessary, whereas gain up to 100 significantly reduce the input referred noise. The optional passive RC lowpass filter between the amplifier’s output and the LTC2420’s input attenuates high frequency noise and its effects. Typically, the filter VS+ 0.1µF 2 DIFFERENTIAL INPUT RG** 1 8 3 VIN+ RG 7 6 0.1µF † † † R1* 47Ω R2* 10k C1* 1µF 2 3 LT1920 RG VIN– 4 VS – *OPTIONAL—SEE TEXT **RG = 49.4k/(AV – 1): USE 5.49k FOR AV = 10; 499Ω FOR AV = 100 †USE SHORT LEAD LENGTHS Figure 10. The LT1920 is a Simple Solution That Converts a Differential Input to a Ground Referred Single-Ended Signal for the LTC2420 10 U reduces the magnitude of averaged noise by 30% and improves resolution by 0.5 bit without compromising linearity. Resistor R2 performs two functions: it isolates C1 from the LTC2420’s input and limits the LTC2420’s input current should its input voltage drop below –300mV or swing above VCC + 300mV. The LT1920 is the choice for applications where low cost is important. For applications where more precision is required, the LT1167 is a pin-to-pin alternative choice with a lower offset voltage, lower input bias current and higher gain accuracy than the LT1920. The LT1920’s maximum total input-referred offset (VOST) is 135µV for a gain of 100. At the same gain, the LT1167’s VOST is 63µV. At gains of 10 or 100, the LT1920’s maximum gain error is 0.3% and its maximum gain nonlinearity is 30ppm. At the same gains, the LT1167’s maximum gain error is 0.1% and its maximum gain nonlinearity is 15ppm. Table 4 summarizes the performance of Figure 10’s circuit using the LT1167. 5V 0.1µF VREFIN 1 VCC VREF LTC2420 GND 4 FO 8 CS SDO SCK 5 6 7 CHIP SELECT SERIAL DATA OUT SERIAL CLOCK VIN 2429 F10 W U U SINGLE POINT “STAR” GROUND LTC2420 APPLICATIO S I FOR ATIO Table 3. Typical Performance of the LTC2420 ADC When Used with the LT1920 Instrumentation Amplifiers in Figure 9’s Differential Digitizing Circuit VS = ±5V PARAMETER Differential Input Voltage Range Zero Error Maximum Input Current Nonlinearity Noise (Without Averaging) Noise (Averaged 64 Readings) Resolution (with Averaged Readings) Overall Accuracy (Uncalibrated) Common Mode Rejection Ratio Common Mode Range 2/–1.5** 2.2/–1.7** ± 8.2 1.8* 0.2* 21 17.2 ± 7.4 0.25* 0.03* 20.6 17.3 ≥120 11.5/–11** 11.7/–11.2** AV = 10 – 30 to 400 –160 AV = 100 – 3 to 40 – 2650 2.0 ± 6.5 1.5* 0.19* 21.3 17.5 ± 6.1 0.27* 0.03* 20.5 18.2 AV = 10 – 30 to 500 – 213 VS = ±15V AV = 100 – 3 to 50 – 2625 TOTAL (UNITS) mV µV nA ppm µVRMS µVRMS Bits Bits dB V *Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier. Table 4. Typical Performance of the LTC2420 ADC When Used with the LT1167 Instrumentation Amplifiers in Figure 9’s Differential Digitizing Circuit VS = ±5V PARAMETER Differential Input Voltage Range Zero Error Maximum Input Current Nonlinearity Noise (Without Averaging) Noise (Averaged 64 Readings) Resolution (with Averaged Readings) Overall Accuracy (Uncalibrated) Common Mode Rejection Ratio Common Mode Range 2/–1.5** 2.2/–1.7** ± 4.1 1.4* 0.18* 21.4 18.2 ± 4.4 0.19* 0.02* 21.0 18.1 ≥120 11.5/–11** 11.7/–11.2** AV = 10 – 30 to 400 –94 AV = 100 – 3 to 40 – 1590 0.5 ± 4.1 1.5* 0.19* 21.3 18.2 ± 3.7 0.18* 0.02* 21.1 19.4 AV = 10 – 30 to 500 – 110 VS = ±15V AV = 100 – 3 to 50 – 1470 TOTAL (UNITS) mV µV nA ppm µVRMS µVRMS Bits Bits dB V *Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier. U W U U 11 LTC2420 PACKAGE I FOR ATIO S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 (0.406 – 1.270) RELATED PARTS PART NUMBER LT1019 LT1025 LTC1043 LTC1050 LT1236A-5 LTC1391 LT1460 LTC2400 LTC2408 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Micropower Thermocouple Cold Junction Compensator Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V 8-Channel Multiplexer Micropower Series Reference 24-Bit µPower, No Latency ∆Σ ADC in SO-8 8-Channel, 24-Bit No Latency ∆Σ ADC COMMENTS 3ppm/°C Drift, 0.05% Max 0.5°C Initial Accuracy, 80µA Supply Current Precise Charge, Balanced Switching, Low Power No External Components 5µV Offset, 1.6µVP-P Noise 0.05% Max, 5ppm/°C Drift Low RON: 45Ω, Low Charge Injection, Serial Interface 0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions, MSOP, PDIP, SO-8, SOT-23 and TO-92 Packages 4ppm INL, 10ppm Total Unadjusted Error, 200µA 4ppm INL, 10ppm Total Unadjusted Error, 200µA 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U W U Dimensions in inches (millimeters) unless otherwise noted. 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC SO8 1298 2420i LT/TP 0100 4K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2000