LTC2433-1

LTC2433-1 Differential Input 16-Bit No Latency ∆Σ ADC FEATURES s s s s s s s s DESCRIPTIO s s s s s 16-Bit Differential ADC in a Tiny MSOP Low Supply Current: 200µA, 4µA in Autosleep Rail-to-Rail Differential Input/Reference 0.12LSB INL, No Missing Codes 0.16LSB Full-Scale Error and 5µV Offset 1.45µV RMS Noise, Independent of VREF Very Low Transition Noise: 0, this bit is HIGH. If VIN is 0.01µF) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential input resistance is 6MΩ which will generate a gain error of approximately 1LSB at full scale for each 180Ω of source resistance driving IN+ or IN –. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 0.84 • 1012/fEOSCΩ and each ohm of source resistance driving IN+ or IN – will result in 3.7 • 10 –8 • fEOSCLSB gain error at full scale. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown in Figures 16 and 17. 24331fa 21 LTC2433-1 APPLICATIO S I FOR ATIO In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN– and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW (internal oscillator and 50Hz/60Hz notch), every 180Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1LSB. When FO is driven by an external oscillator with a frequency fEOSC, every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 3.7 • 10–8 • fEOSCLSB. Figure 18 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. 3 A 2 OFFSET ERROR (LSB) 1 0 –1 F –2 G –3 0 0.5 1 FO = GND TA = 25°C RSOURCEIN – = 500Ω CIN = 10µF 1.5 2 2.5 3 VINCM (V) 3.5 4 4.5 5 B C D E VCC = 5V REF + = 5V REF – = GND IN + = IN – = VINCM A: ∆RIN = + 400Ω B: ∆RIN = + 200Ω C: ∆RIN = + 100Ω D: ∆RIN = 0Ω E: ∆RIN = – 100Ω F: ∆RIN = – 200Ω G: ∆RIN = – 400Ω 24331 F18 Figure 18. Offset Error vs Common Mode Voltage (VINCM = IN+ = IN–) and Input Source Resistance Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF) 22 U If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 15k source resistance will create a 0LSB typical and 1LSB maximum offset voltage. Reference Current In a similar fashion, the LTC2433-1 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. 24331fa W UU LTC2433-1 APPLICATIO S I FOR ATIO Larger values of reference capacitors (CREF > 0.01µF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential reference resistance is 4.2MΩ which will generate a gain error of approximately 1LSB full scale for each 120Ω of source resistance driving REF+ or REF–. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.60 • 1012/fEOSCΩ and each ohm of source resistance drving REF+ or REF– will result in 5.1 • 10–8 • fEOSCLSB gain error at full scale. The effect 0 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C CREF = 0pF –2 CREF = 100pF CREF = 0.001µF CREF = 0.01µF –3 1 10 100 1k RSOURCE (Ω) 10k 100k 24331 F19 –1 –FS ERROR (LSB) +FS ERROR (LSB) Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN) 0 CREF = 0.1µF CREF = 0.01µF – FS ERROR (LSB) +FS ERROR (LSB) CREF = 10µF –5 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C –10 CREF = 1µF 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 24331 F21 Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF) U of the source resistance on the two reference pins is additive with respect to this gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 19, 20, 21 and 22. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), every 1000Ω of source resistance driving REF+ or REF– translates into about 1LSB additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 1000Ω of source resistance driving REF+ or REF– 3 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V 2 FO = GND TA = 25°C CREF = 0pF 1 CREF = 100pF CREF = 0.001µF CREF = 0.01µF 0 1 10 100 1k RSOURCE (Ω) 10k 100k 24331 F20 W UU Figure 20. –FS Error vs RSOURCE at REF+ or REF– (Small CIN) 10 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C 5 CREF = 0.1µF CREF = 10µF CREF = 1µF CREF = 0.01µF 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 24331 F22 Figure 22. –FS Error vs RSOURCE at REF+ and REF– (Large CREF) 24331fa 23 LTC2433-1 APPLICATIO S I FOR ATIO translates into about 7.15 • 10–6 • fEOSCLSB additional INL error. Figure 23 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+ and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF+ and REF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. 1 RSOURCE = 1000Ω INL (LSB) 0 –1 –0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10µF TA = 25°C REF– = GND 24331 F23 VINCM = 0.5 • (IN + + IN –) = 2.5V Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF) 24 U In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maximum full-scale error. Output Data Rate When using its internal oscillator, the LTC2433-1 can produce up to 6.8 readings per second. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2433-1 output data rate can be increased as desired. The duration of the conversion phase is 20510/fEOSC. If fEOSC = 139,800Hz, the converter behaves as if the internal oscillator is used with simultaneous 50Hz/60Hz. There is no significant difference in the LTC2433-1 performance between these two operation modes. An increase in fEOSC over the nominal 139,800Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2433-1’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external 24331fa W UU LTC2433-1 APPLICATIO S I FOR ATIO input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2433-1 typical performance can be inferred from Figures 14, 15, 19 and 20 in which the horizontal axis is scaled by 139,800/fEOSC. 8 VCC = 5V VREF = 5V VINCM = 2.5V VIN = 0V FO = EXT OSC TA = 85°C 0 OFFSET ERROR (LSB) +FS ERROR (LSB) TA = 25°C 0 –8 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24331 F24 Figure 24. Offset Error vs Output Data Rate and Temperature 6 TA = 25°C 0 TA = 85°C –3 VCC = 5V VREF = 5V –6 IN + = 1.25V IN – = 3.75V FO = EXT OSC –9 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24331 F26 NUMBER OF READINGS (%) 3 –FS ERROR (LSB) Figure 26. –FS Error vs Output Data Rate and Temperature U Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 24, 25, 26, 27, 28 and 29. In order to obtain the 15 12 9 6 TA = 85°C 3 TA = 25°C VCC = 5V VREF = 5V IN + = 3.75V IN – = 1.25V FO = EXT OSC –3 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24331 F25 W UU Figure 25. +FS Error vs Output Data Rate and Temperature 50 GAUSSIAN DISTRIBUTION m = 3.1µV σ = 1.59µVRMS VCC = 5V VREF = 0.1V VIN = 0V REF+ = 0.1V REF – = GND IN+ = GND IN– = GND FO = 2.048MHz TA = 125°C 40 30 20 10 0 –1 0 1 3 2 OUTPUT CODE 4 5 2433 F27 Figure 27. Noise Histogram (Output Rate = 100Hz, VCC = 5V, VREF = 100mV, 125°C) 24331fa 25 LTC2433-1 APPLICATIO S I FOR ATIO 22 20 18 16 14 12 10 VCC = 5V VREF+ = 5V VREF – = GND VINCM = 2.5V –2.5V < VIN < 2.5V FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/sec) 2433 F28 OFFSET ERROR (LSB) RESOLUTION (BITS) Figure 28. Integral Nonlinearity vs Output Data Rate highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Increasing Input Resolution by Reducing Reference Voltage The resolution of the LTC2433-1 can be increased by reducing the reference voltage. It is often necessary to amplify low level signals to increase the voltage resolution of ADCs that cannot operate with a low reference voltage. The LTC2433-1 can be used with reference voltages as low as 100mV, corresponding to a ±50mV input range with full 16-bit resolution. Reducing the reference voltage is functionally equivalent to amplifying the input signal, however no amplifier is required. The LTC2433-1 has a 76µV LSB when used with a 5V reference, however the thermal noise of the inputs is 1.45µVRMS and is independent of reference voltage. Thus reducing the reference voltage will increase the resolution at the inputs as long as the LSB voltage is significantly larger than 1.45µVRMS. A 570mV reference corresponds to a 8.7µV LSB, which is approximately the peak-to-peak value of the 1.45µVRMS input thermal noise. At this point, 26 U 3 VREF = 2.5V 0 VREF = 5V –3 VCC = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXT OSC TA = 25°C 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24331 F29 W UU –6 –9 Figure 29. Offset Error vs Output Data Rate and Reference Voltage the output code will be stable to ±1LSB for a fixed input. As the reference is decreased further, the measured noise will approach 1.45µVRMS. Figure 30 shows two methods of dividing down the reference voltage to the LTC2433-1. Where absolute accuracy is required, a precision divider such as the Vishay MPM series dividers in a SOT-23 package may be used. A 51:1 divider provides a 98mV reference to the LTC2433-1 from a 5V source. The resulting ±49mV input range and 1.5µV LSB is suitable for thermocouple and 10mV fullscale strain gauge measurements. If high initial accuracy is not critical, a standard 2% resistor array such as the Panasonic EXB series may be used. Single package resistor arrays provide better temperature stability than discrete resistors. An array of eight resistors can be configured as shown to provide a 294mV reference to the LTC2433-1 from a 5V source. The fully differential property of the LTC2433-1 reference terminals allow the reference voltage to be taken from four central resistors in the network connected in parallel, minimizing drift in the presence of thermal gradients. This is an ideal reference for medium accuracy sensors such as silicon micromachined pressure and force sensors. These devices typically have accuracies on the order of 2% and fullscale outputs of 50mV to 200mV. 24331fa LTC2433-1 PACKAGE DESCRIPTIO 5.23 (.206) MIN 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) GAUGE PLANE 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.13 ± 0.076 (.005 ± .003) MSOP (MS) 0802 0.50 (.0197) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF DETAIL “A” 0° – 6° TYP 12345 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 1.10 (.043) MAX 0.86 (.034) REF 4.90 ± 0.15 (1.93 ± .006) 3.00 ± 0.102 (.118 ± .004) NOTE 4 24331fa 27 LTC2433-1 TYPICAL APPLICATIO 5V 8 × 2k ARRAY PANASONIC EXB-2HV202G REF + 5V 0.1µF REF – VREF = 294mV ±147mV INPUT RANGE 4.5µV LSB VISHAY MPM1001/5002B 5V 50k REF + 1k REF – VREF = 95.04mV ± 49mV INPUT RANGE 1.5µV LSB HONEYWELL FSL05N2C 500 GRAM FORCE SENSOR 5 5V 1 2 3 4 VCC REF + REF – IN+ LTC2433-1 IN– SCK SDO 6 GND CS 9 8 7 24331 F30 Figure 30. Increased Resolution Bridge/Temperature Measurement RELATED PARTS PART NUMBER LT1019 LTC1043 LTC1050 LT1236A-5 LT1461 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2411 LTC2412 LTC2413 LTC2414/LTC2418 LTC2415 LTC2420 LTC2424/LTC2428 LTC2431 LTC2436-1 LTC2440 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Precision LDO Reference 24-Bit, No Latency ∆Σ ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 24-Bit, Fully Differential, No Latency ∆Σ ADC 24-Bit, No Latency ∆Σ ADC in MSOP 2-Channel, 24-Bit, Pin Compatible with LTC2436-1 24-Bit, No Latency ∆Σ ADC 8-/16-Channel, 24-Bit No Latency ∆Σ ADC 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate 20-Bit, No Latency ∆Σ ADC in SO-8 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs 20-Bit, Differential No Latency ∆Σ ADC Low Cost 16-Bit ∆Σ ADC High Speed, Low Noise 24-Bit ADC COMMENTS 3ppm/°C Drift, 0.05% Max Precise Charge, Balanced Switching, Low Power No External Components 5µV Offset, 1.6µVP-P Noise 0.05% Max, 5ppm/°C Drift High Accuracy 0.04% Max, 3ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA 1.45µVRMS Noise, 2ppm INL, Pin Compatible with LTC2433-1 800nV Noise, 2ppm INL, 3ppm TUE, 200µA Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA Pin Compatible with the LTC2410 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408 Pin Compatible with LTC2433-1 800nVRMS Noise 2-Channel Ping-Pong 4kHz Output Rate, 200µV Noise, 24.6 ENOBs 24331fa LT/TP 0104 1K REV A • PRINTED IN USA 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U 4.7µF 10 FO www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003