LTC2439-1 8-/16-Channel 16-Bit No Latency ∆ΣTM ADC
FEATURES
s s s s s s s
DESCRIPTIO
s
s s
s s s
16-Channel Single-Ended or 8-Channel Differential Inputs Low Supply Current (200µA, 4µA in Autosleep) Rail-to-Rail Differential Input/Reference 16-Bit No Missing Codes 1µV RMS Noise, 16-ENOBS Independent of VREF Very Low Transition Noise: Less Than 0.02LSB Operates with a Reference as Low as 100mV with 1.5µV LSB Step Size Guaranteed Modulator Stability and Lock-Up Immunity for Any Input and Reference Conditions Single Supply 2.7V to 5.5V Operation Internal Oscillator—No External Components Required 87dB Min, 50Hz and 60Hz Simultaneous Notch Filter Pin Compatible with the 24-Bit LTC2418 28-Lead SSOP Package
The LTC ®2439-1 is a 16-channel (8-differential) micropower 16-bit ∆Σ analog-to-digital converter. It operates from 2.7V to 5.5V and includes an integrated oscillator, 0.12LSB INL and 1µV RMS noise. It uses deltasigma technology and provides single cycle settling time for multiplexed applications. Through a single pin, the LTC2439-1 can be configured for better than 87dB differential mode rejection at 50Hz and 60Hz ± 2%, or it can be driven by an external oscillator for a user-defined rejection frequency. The internal oscillator requires no external frequency setting components. The LTC2439-1 accepts any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement applications. It can be configured to take 8 differential channels or 16 single-ended channels. The full-scale bipolar input range is from – 0.5V REF to 0.5VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set between GND and VCC. The DC common mode input rejection is better than 140dB. The LTC2439-1 communicates through a flexible 4-wire digital interface that is compatible with SPI and MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s s s s s
Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Gas Analyzers Strain Gauge Transducers Instrumentation Data Acquisition Industrial Process Control
TYPICAL APPLICATIO
21 CH0 22 CH1 • • • 28 CH7 1 CH8 • • • 8 CH15 10 COM REF – GND
2.7V TO 5.5V
REF +
VCC FO
MINIMUM RESOLVABLE SIGNAL (µV)
11
9 19
1µF
= EXTERNAL OSCILLATOR = 50Hz and 60Hz REJECTION
THERMOCOUPLE
16-CHANNEL MUX
+ –
DIFFERENTIAL 16-BIT ∆Σ ADC
SDI SCK SDO CS
20 18 17 16
4-WIRE SPI INTERFACE
12 15
LTC2439-1
241418 TA01a
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Minimum Resolvable Signal vs VREF
90 80 70 60 50 40 30 20 10 0 5 4 3 VREF (V) 24361 TA02 *FOR VREF = 0.4V RESOLUTION IS LIMITED BY STEP SIZE 1 2 0
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LTC2439-1
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 VCC 1 2 3 4 5 6 7 8 9 28 CH7 27 CH6 26 CH5 25 CH4 24 CH3 23 CH2 22 CH1 21 CH0 20 SDI 19 FO 18 SCK 17 SDO 16 CS 15 GND
Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2439-1C ............................................ 0°C to 70°C LTC2439-1I ........................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER LTC2439-1CGN LTC2439-1IGN
COM 10 REF+ 11 REF– 12 NC 13 NC 14
GN PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity CONDITIONS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
MIN
q q q
TYP 0.06 0.12 0.30 5 10
MAX
UNITS Bits LSB LSB LSB µV nV/°C
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) 4.5V ≤ VCC = GND, VINCM = 1.25V, (Note 6) 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Notes 6, 15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC, (Notes 12,15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ (Note 15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ (Note 15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 5V ≤ VCC ≤ 5.5V, REF + = 5V, VREF – = GND, GND ≤ IN – = IN + ≤ 5V (Note 12) ≤ 5.5V, REF+ = 2.5V, REF–
16 1.25 20
Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error
q
0.16 0.03
1.25
ppm of VREF/°C 1.25 LSB ppm of VREF/°C LSB LSB LSB µVRMS
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q
0.16 0.03 0.20 0.20 0.25 1
Output Noise
2
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LSB
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LTC2439-1
CO VERTER CHARACTERISTICS
PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 49Hz to 61.2Hz Input Normal Mode Rejection 49Hz to 61.2Hz Reference Common Mode Rejection DC Power Supply Rejection, DC Power Supply Rejection, Simultaneous 50Hz/60Hz ±2% CONDITIONS 2.5V ≤ REF+ ≤ V
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
MIN
q q q q
A ALOG I PUT A D REFERE CE
SYMBOL IN + IN – VIN REF + REF – VREF CS (IN +) CS CS (IN –) (REF +) (IN +) (IN –) (REF –) PARAMETER Absolute/Common Mode IN + Voltage Absolute/Common Mode IN – Voltage Input Differential Voltage Range (IN + – IN –) Absolute/Common Mode REF + Voltage Absolute/Common Mode REF – Voltage Reference Differential Voltage Range (REF + – REF –) IN + Sampling Capacitance IN – Sampling Capacitance REF + Sampling Capacitance REF – Sampling Capacitance IN + DC Leakage Current IN – DC Leakage Current REF + DC Leakage Current REF – DC Leakage Current Off Channel to On Channel Isolation (RIN = 100Ω) tOPEN IS(OFF) MUX Break-Before-Make Interval Channel Off Leakage Current
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
CONDITIONS
q q q q q q
CS (REF –) IDC_LEAK IDC_LEAK IDC_LEAK
IDC_LEAK (REF +)
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TYP 140
MAX
UNITS dB dB dB
– CC, REF = GND, – = IN+ ≤ V (Note 5) GND ≤ IN CC 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN – = IN+ ≤ VCC, (Note 5)
130 140 87 130
(Note 5) 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V, VREF = 2.5V, IN– = IN+ = GND (Note 5) REF+ = 2.5V, REF– = GND, IN– = IN+ = GND REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
140 120 120
dB dB dB
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MIN GND – 0.3 GND – 0.3 – VREF/2 0.1 GND 0.1
TYP
MAX VCC + 0.3 VCC + 0.3 VREF/2 VCC VCC – 0.1 VCC
UNITS V V V V V V pF pF pF pF
18 18 18 18 CS = VCC CS = VCC CS = VCC = 5.5V, IN+ = 5.5V, IN– = GND = 5V
q q q q
–100 –100 –100 –100
1 1 1 1 140 140 140 100
100 100 100 100
nA nA nA nA dB dB dB ns
CS = VCC = 5.5V, REF+ = 5V = 5.5V, REF– = GND DC 1Hz fS = 15,3600Hz 2.7V ≤ VCC ≤ 5.5V Channel at VCC and GND
q
–100
1
100
nA
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LTC2439-1 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO, SDI Low Level Input Voltage CS, FO, SDI High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO, SDI Digital Input Current SCK Digital Input Capacitance CS, FO, SDI Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 8) IO = – 800µA IO = 1.6mA IO = – 800µA (Note 9) IO = 1.6mA (Note 9)
q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V (Note 8) 2.7V ≤ VCC ≤ 3.3V (Note 8) 4.5V ≤ VCC ≤ 5.5V (Note 8) 2.7V ≤ VCC ≤ 5.5V (Note 8) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Note 8)
q q q q q q
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode Sleep Mode
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
CONDITIONS
q
4
UW
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MIN 2.5 2.0
TYP
MAX
UNITS V V
0.8 0.6 2.5 2.0 0.8 0.6 –10 –10 10 10 VCC – 0.5 0.4 VCC – 0.5 0.4 –10 10 10 10
V V V V V V µA µA pF pF V V V V µA
MIN 2.7
TYP
MAX 5.5
UNITS V µA µA µA
CS = 0V (Note 11) CS = VCC (Note 11) CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 11, 14)
q q
200 4 2
300 15
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LTC2439-1 TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 t7 t8 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 19-Bit Data Output Time F O = 0V External Oscillator (Note 10) Internal Oscillator (Note 9) External Oscillator (Notes 9, 10) (Note 9) (Note 8) (Note 8) (Note 8) Internal Oscillator (Notes 9, 11) External Oscillator (Notes 9, 10)
q q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
CONDITIONS
q q q q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN+ – IN –, VINCM = (IN + + IN –)/2, IN+ and IN– are defined as the selected positive and negative input respectively. Note 4: FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size (VREF/216) and the single shot measurement. Typical specifications are measured from the center of the quantization band. Note 7: FO = GND (internal oscillator) or fEOSC = 139800Hz ± 2% (external oscillator).
UW
MIN 2.56 0.25 0.25 143.8
TYP
MAX 2000 390 390
UNITS kHz µs µs ms ms kHz kHz
146.7 149.6 20510/fEOSC (in kHz) 17.5 fEOSC/8
45 250 250 1.06
55 2000
% kHz ns ns
1.09 1.11 152/fEOSC (in kHz) 19/fESCK (in kHz) 200 200 200 220
ms ms ms ns ns ns ns ns ns ns
External SCK 19-Bit Data Output Time (Note 7) CS ↓ to SDO Low CS ↑ to SDO High Z CS ↓ to SCK ↓ CS ↓ to SCK ↑ SCK ↓ to SDO Valid SDO Hold After SCK ↓ SCK Set-Up Before CS ↓ SCK Hold After CS ↓ SDI Setup Before SCK↑ SDI Hold After SCK↑ (Note 5) (Note 5) (Note 5) (Note 9) (Note 8)
0 0 0 50 15 50
q q q q q q q q
50 100 100
ns ns ns
Note 8: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 12: 1µV RMS noise is independent of VREF. Since the noise performance is limited by the quantization, lowering VREF improves the effective resolution. Note 13: Guaranteed by design and test correlation. Note 14: The low sleep mode current is valid only when CS is high. Note 15: These parameters are guaranteed by design over the full supply and temperature range. Automated testing proceedures are limited by the LSB Step Size (VREF/216).
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LTC2439-1
PI FU CTIO S
CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog Inputs. May be programmed for single-ended or differential mode. VCC (Pin 9): Positive Supply Voltage. Bypass to GND (Pin 15) with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. COM (Pin 10): The common negative input (IN–) for all single-ended multiplexer configurations. The voltage on Channel 0 to 15 and COM input pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range (VIN = IN+ – IN–) from – 0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique overrange and underrange output codes. REF + (Pin 11), REF – (Pin 12): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the positive reference input, REF +, is maintained more positive than the negative reference input, REF –, by at least 0.1V. GND (Pin 15): Ground. Connect this pin to a ground plane through a low impedance connection. CS (Pin 16): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 17): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 19): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and rejects 50Hz and 60Hz simultaneously. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter has 87dB minimum rejection in the range fEOSC/2560 ±14% and 110dB minimum rejection at fEOSC/2560 ±4%. SDI (Pin 20): Serial Digital Data Input. During the Data Output period, this pin is used to shift in the multiplexer address started from the first rising SCK edge. During the Conversion and Sleep periods, this pin is in the DON’T CARE state. However, a HIGH or LOW logic level should be maintained on SDI in the DON’T CARE mode to avoid an excessive current in the SDI input buffers. NC (Pins 13, 14): Not Internally Connected. Do not connect or connect to ground.
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LTC2439-1
FU CTIO AL BLOCK DIAGRA
VCC GND REF + REF – CH0 CH1 • • • MUX
IN + IN –
–
CH15 COM
DIFFERENTIAL 3RD ORDER ∆Σ MODULATOR
TEST CIRCUITS
SDO 1.69k CLOAD = 20pF
241418 TC01
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2439-1 is a multichannel, low power, delta-sigma analog-to-digital converter with an easy-to-use 4-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data input/output (see Figure 2). The 4-wire interface consists of serial data input (SDI), serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2439-1 performs a conversion. Once the conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. While in the sleep state, power consumption is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
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AUTOCALIBRATION AND CONTROL INTERNAL OSCILLATOR FO (INT/EXT)
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+
SERIAL INTERFACE DECIMATING FIR ADDRESS
24391 F01
SDI SCK SDO CS
Figure 1
VCC 1.69k SDO CLOAD = 20pF
241418 TA03
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
POWER UP IN + = CH0, IN – = CH1
CONVERT
SLEEP
FALSE
CS = LOW AND SCK TRUE DATA OUTPUT ADDRESS INPUT
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Figure 2. LTC2439-1 State Transition Diagram
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LTC2439-1
APPLICATIO S I FOR ATIO
Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW after the first rising edge of SCK, the device begins outputting the conversion result and inputting channel selection bits. Taking CS high at this point will terminate the data output state and start a new conversion. The channel selection control bits are shifted in through SDI from the first rising edge of SCK and depending on the control bits, the converter updates its channel selection immediately and is valid for the next conversion. The details of channel selection control bits are described in the Input Data Mode section. The output data is shifted out the SDO pin under the control of the serial clock (SCK). The output data is updated on the falling edge of SCK allowing
CS BIT18 SDO Hi-Z EOC BIT17 (0) BIT16 SIG BIT15 MSB BIT14 B22 BIT13 BIT12 BIT11
SCK
SDI SLEEP
(1)
(0)
EN
SGL
ODD/ SIGN
A2
Figure 3a. Input/Output Data Timing
CONVERSION RESULT N–1 SDO Hi-Z Hi-Z Hi-Z CONVERSION RESULT N CONVERSION RESULT N+1
SCK
SDI ADDRESS N OPERATION OUTPUT N–1
DON’T CARE ADDRESS N+1 CONVERSION N OUTPUT N
Figure 3b. Typical Operation Sequence
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the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 19 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. In order to maintain compatibility with 24-/32-bit data transfers, it is possible to clock the LTC2439-1 with additional serial clock pulses. This results in additional data bits which are always logic HIGH. Through timing control of the CS and SCK pins, the LTC2439-1 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.
BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 LSB CONVERSON RESULT A1 A0 DATA INPUT/OUTPUT CONVERSION
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DON’T CARE
DON’T CARE ADDRESS N+2 CONVERSION N + 1 OUTPUT N+1
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LTC2439-1
APPLICATIO S I FOR ATIO
Conversion Clock
A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz and 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2439-1 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2436-1 achieves a minimum of 87dB rejection over the range 49Hz to 61.2Hz. Ease of Use The LTC2439-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. The LTC2439-1 performs offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2439-1 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 3-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a typical duration of 1ms. The POR signal clears all internal registers. Following the POR signal, the LTC2439-1 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the
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specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range The LTC2439-1 accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF – pin. The LTC2439-1 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will significantly improve the converter’s effective resolution, since the thermal noise (1µV) is well below the quantization level of the device (75.6µV for a 5V reference). At the minimum reference (100mV) the thermal noise remains constant at 1µV RMS (or 6µVP-P), while the quantization is reduced to 1.5µV per LSB. As a result, lowering the reference improves the effective resolution for low level input voltages. Input Voltage Range The two selected pins are labeled IN+ and IN– (see Table 1). Once selected (either differential or single-ended multiplexing mode), the analog input is differential with a common mode range for the IN+ and IN– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2439-1 converts the bipolar differential input signal, VIN = IN + – IN –, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF –. Outside this range the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN– pins may extend 300mV below ground or above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ or IN– pins without affecting the performance of the device. In the physical layout, it is important to
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LTC2439-1
APPLICATIO S I FOR ATIO
maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. In addition, series
Table 1. Channel Selection
MUX ADDRESS SGL *0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ODD/ SIGN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 A1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– 0 IN+ 1 IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– 2 3 4 5 6 CHANNEL SELECTION 7 8 9 10 11 12 13 14 15 COM
*Default at power up
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resistors will introduce a temperature dependent offset error due to the input leakage current. A 10nA input leakage current will develop a 1LBS offset error on an 8k resistor if VREF = 5V. This error has a very strong temperature dependency.
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LTC2439-1
APPLICATIO S I FOR ATIO
Input Data Format
When the LTC2439-1 is powered up, the default selection used for the first conversion is IN+ = CH0 and IN– = CH1 (Address = 00000). In the data input/output mode following the first conversion, a channel selection can be updated using an 8-bit word. The LTC2439-1 serial input data is clocked into the SDI pin on the rising edge of SCK (see Figure 3a). The input is composed of an 8-bit word with the first 3 bits acting as control bits and the remaining 5 bits as the channel address bits. The first 2 bits are always 10 for proper updating operation. The third bit is EN. For EN = 1, the following 5 bits are used to update the input channel selection. For EN = 0, previous channel selection is kept and the following bits are ignored. Therefore, the address is updated when the 3 control bits are 101 and kept for 100. Alternatively, the 3 control bits can be all zero to keep the previous address. This alternation is intended to simplify the SDI interface allowing the user to simply connect SDI to ground if no update is needed. Combinations other than 101, 100 and 000 of the 3 control bits should be avoided. When update operation is set (101), the following 5 bits are the channel address. The first bit, SGL, decides if the differential selection mode (SGL = 0) or the single-ended selection mode is used (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input; for SGL = 1, one of the 16 channels (CH0-CH15) is selected as the positive input and the COM pin is used as the negative input. For a given channel selection, the converter will measure the voltage between the two channels indicated by IN+ and IN– in the selected row of Table 1. Output Data Format The LTC2439-1 serial output data stream is 19 bits long. The first 3 bits represent status information indicating the conversion state and sign. The next 16 bits are the conversion result, MSB first. The third and fourth bit together are also used to indicate an underrange condition (both bits low means the differential input voltage is below –FS) or an overrange condition (both bits high means the differential input voltage is above +FS). Bit 18 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the
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conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 17 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 16 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential input resistance is 2MΩ which will generate a gain error of approximately 1LSB at full scale for each 60Ω of source resistance driving IN+ or IN –. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 0.28 • 1012/fEOSCΩ
+FS ERROR (LSB)
–FS ERROR (LSB)
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RSOURCE CPAR ≅ 20pF IN + CIN VINCM + 0.5VIN LTC2439-1 RSOURCE CPAR ≅ 20pF IN – CIN
24361 F13
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VINCM – 0.5VIN
Figure 13. An RC Network at IN + and IN –
3
CIN = 0.01µF CIN = 0.001µF CIN = 100pF
2 CIN = 0pF VCC = 5V REF + = 5V REF – = GND IN + = 5V IN – = 2.5V FO = GND TA = 25°C 1 10 100 1k RSOURCE (Ω) 10k 100k
24361 F14
1
0
Figure 14. +FS Error vs RSOURCE at IN + or IN – (Small CIN)
0
–1
VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = 2.5V FO = GND TA = 25°C CIN = 0.01µF
–2 CIN = 0.001µF CIN = 100pF –3 1 10 CIN = 0pF 100 1k RSOURCE (Ω) 10k 100k
24361 F15
Figure 15. –FS Error vs RSOURCE
at IN + or IN – (Small C
IN)
24391f
LTC2439-1
APPLICATIO S I FOR ATIO
and each ohm of source resistance driving IN+ or IN – will result in 1.11 • 10 –7 • fEOSCLSB gain error at full scale. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown in Figures 16 and 17. In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN– and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW (internal oscillator and 50Hz/60Hz notch), every 60Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1LSB. When FO is driven by an external oscillator with a frequency fEOSC, every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1.11 • 10–7 • fEOSCLSB. Figure 18 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and
+FS ERROR (LSB)
–FS ERROR (LSB)
OFFSET ERROR (LSB)
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20 16 12 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C CIN = 1µF, 10µF CIN = 0.1µF 8 CIN = 0.01µF 4 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω)
24361 F16
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Figure 16. +FS Error vs RSOURCE
0
at IN+
or IN– (Large CIN)
CIN = 0.01µF –4
–8 CIN = 0.1µF –12 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C
–16
CIN = 1µF, 10µF
–20
0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω)
24361 F17
Figure 17. –FS Error vs RSOURCE
8 A 4 B C 0 D E F –4 G
at IN+ or IN– (Large C
IN)
VCC = 5V REF + = 5V REF – = GND IN + = IN – = VINCM
–8
FO = GND TA = 25°C RSOURCEIN – = 500Ω CIN = 10µF 1 1.5 2 2.5 3 VINCM (V) 3.5 4 4.5 5
0
0.5
A: ∆RIN = + 400Ω B: ∆RIN = + 200Ω C: ∆RIN = + 100Ω D: ∆RIN = 0Ω
E: ∆RIN = – 100Ω F: ∆RIN = – 200Ω G: ∆RIN = – 400Ω
24361 F18
Figure 18. Offset Error vs Common Mode Voltage (VINCM = IN+ = IN–) and Input Source Resistance Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
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LTC2439-1
APPLICATIO S I FOR ATIO
IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 15k source resistance will create a 0LSB typical and 1LSB maximum offset voltage. Reference Current In a similar fashion, the LTC2439-1 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 0.01µF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge
0 VCC = 5V REF + = 5V REF – = GND IN + = 5V IN – = 2.5V FO = GND TA = 25°C CREF = 0.01µF –2 CREF = 0.001µF CREF = 100pF –3 1 10 CREF = 0pF 100 1k RSOURCE (Ω) 10k 100k
24361 F19
–FS ERROR (LSB)
+FS ERROR (LSB)
–1
Figure 19. +FS Error vs RSOURCE
at REF+
or REF–
(Small CIN)
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and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential reference resistance is 1.4MΩ which will generate a gain error of approximately 1LSB full scale for each 40Ω of source resistance driving REF+ or REF–. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.20 • 1012/fEOSCΩ and each ohm of source resistance drving REF+ or REF– will result in 1.54 • 10–7 • fEOSCLSB gain error at full scale. The effect of the source resistance on the two reference pins is additive with respect to this gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 19, 20, 21 and 22. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), every 1000Ω of source resistance driving REF+ or REF– translates into about 1LSB additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100Ω of source resistance driving REF+ or REF– translates into about 5.5 • 10–7 • fEOSCLSB additional INL error. Figure 23 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source
3 CREF = 0.01µF CREF = 0.001µF CREF = 100pF 2 CREF = 0pF VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = 2.5V FO = GND TA = 25°C 1 10 100 1k RSOURCE (Ω) 10k 100k
2412 F19
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1
0
Figure 20. –FS Error vs RSOURCE
at REF+
or REF– (Small CIN)
24391f
LTC2439-1
APPLICATIO S I FOR ATIO
0 CREF = 0.01µF 6
+FS ERROR (LSB)
11 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C
–FS ERROR (LSB)
CREF = 0.1µF
17
22
CREF = 1µF, 10µF
30
0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω)
24361 F21
Figure 21. +FS Error vs RSOURCE
1
at REF+
and REF–
(Large CREF)
RSOURCE = 1000Ω
INL (LSB)
0
–1 –0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10µF TA = 25°C REF– = GND 24361 F23 VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF)
impedance for the REF+ and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF+ and REF–, the expected drift of the dynamic
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30 22 17 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C CREF = 1µF, 10µF CREF = 0.1µF 11 CREF = 0.01µF 6 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω)
24361 F22
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Figure 22. –FS Error vs RSOURCE
at REF+
and REF– (Large CREF)
current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maximum full-scale error. Output Data Rate When using its internal oscillator, the LTC2439-1 can produce up to 6.8 readings per second. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2439-1 output data rate can be increased as desired. The duration of the conversion phase is 20510/fEOSC. If fEOSC = 139,800Hz, the converter behaves as if the internal oscillator is used with simultaneous 50Hz/60Hz. There is no significant difference in the LTC2439-1 performance between these two operation modes. An increase in fEOSC over the nominal 139,800Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered.
24391f
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LTC2439-1
APPLICATIO S I FOR ATIO
First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2439-1’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2439-1 typical performance can be inferred from Figures 14, 15, 19 and 20 in which the horizontal axis is scaled by 139,800/fEOSC. Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 24, 25, 26, 27, 28 and 29. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Increasing Input Resolution by Reducing Reference Voltage The resolution of the LTC2439-1 can be increased by reducing the reference voltage. It is often necessary to
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amplify low level signals to increase the voltage resolution of ADCs that cannot operate with a low reference voltage. The LTC2439-1 can be used with reference voltages as low as 100mV, corresponding to a ±50mV input range with full 16-bit resolution. Reducing the reference voltage is functionally equivalent to amplifying the input signal, however no amplifier is required. The LTC2439-1 has a 76µV LSB when used with a 5V reference, however the thermal noise of the inputs is 1µVRMS and is independent of reference voltage. Thus reducing the reference voltage will increase the resolution at the inputs as long as the LSB voltage is significantly larger than 1µVRMS. A 325mV reference corresponds to a 5µV LSB, which is approximately the peak-to-peak value of the 1µVRMS input thermal noise. At this point, the output code will be stable to ±1LSB for a fixed input. As the reference is decreased further, the measured noise will approach 1µVRMS. Figure 30 shows two methods of dividing down the reference voltage to the LTC2439-1. Where absolute accuracy is required, a precision divider such as the Vishay MPM series dividers in a SOT-23 package may be used. A 51:1 divider provides a 98mV reference to the LTC2439-1 from a 5V source. The resulting ±49mV input range and 1.5µV LSB is suitable for thermocouple and 10mV fullscale strain gauge measurements. If high initial accuracy is not critical, a standard 2% resistor array such as the Panasonic EXB series may be used. Single package resistor arrays provide better temperature stability than discrete resistors. An array of eight resistors can be configured as shown to provide a 294mV reference to the LTC2439-1 from a 5V source. The fully differential property of the LTC2439-1 reference terminals allow the reference voltage to be taken from four central resistors in the network connected in parallel, minimizing drift in the presence of thermal gradients. This is an ideal reference for medium accuracy sensors such as silicon micromachined pressure and force sensors. These devices typically have accuracies on the order of 2% and fullscale outputs of 50mV to 200mV.
24391f
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LTC2439-1
APPLICATIO S I FOR ATIO
30
420
VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 85°C TA = 25°C
360
+FS ERROR (LSB)
OFFSET ERROR (LSB)
240 180 120 TA = 25°C 60
–FS ERROR (LSB)
300
VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = EXTERNAL OSCILLATOR
15
0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24361 F24
0
0
Figure 24. Offset Error vs Output Data Rate and Temperature
17
Figure 25. +FS Error vs Output Data Rate and Temperature
18 16
16 RESOLUTION (BITS) RESOLUTION (BITS) TA = 25°C 15 TA = 85°C 14 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24361 F27
16 TA = 85°C 14
OFFSET ERROR (LSB)
12
13
10
12
8 0
VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V –2.5V < VIN < 2.5V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/INLMAX) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24361 F28
Figure 27. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature
Figure 28. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature
PACKAGE DESCRIPTIO
.045 ± .005
GN Package 28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.254 MIN
.150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988)
.0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS)
.0250 TYP 1 .015 ± .004 × 45° (0.38 ± 0.10) 0° – 8° TYP .053 – .069 (1.351 – 1.748) 23 4 56 7 8 9 10 11 12 13 14 .004 – .009 (0.102 – 0.249)
.0075 – .0098 (0.191 – 0.249) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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0 60 120 180 240 300 360 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24361 F26
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TA = 85°C TA = 25°C
TA = 85°C
10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24361 F25
420
Figure 26. –FS Error vs Output Data Rate and Temperature
VCC = 5V REF + = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 25°C
TA = 25°C
8 VREF = 5V VREF = 2.5V
0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24361 F29
Figure 29. Offset Error vs Output Data Rate and Reference Voltage
.386 – .393* (9.804 – 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615
.033 (0.838) REF
.016 – .050 (0.406 – 1.270)
.008 – .012 (0.203 – 0.305)
.0250 (0.635) BSC
GN28 (SSOP) 0502
24391f
27
LTC2439-1
TYPICAL APPLICATIO
5V 8 × 2k ARRAY
PANASONIC EXB-2HV202G REF + 5V 0.1µF REF – VREF = 294mV ±147mV INPUT RANGE 4.5µV LSB VISHAY MPM1001/5002B 5V 50k REF + 1k REF – VREF = 95.04mV ± 49mV INPUT RANGE 1.5µV LSB 9 11 5V 12 21 HONEYWELL FSL05N2C 500 GRAM FORCE SENSOR 4.7µF 19 20
Figure 30. Increased Resolution Bridge/Temperature Measurement
RELATED PARTS
PART NUMBER LTC1043 LT1236A-5 LT1461 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2411 LTC2411-1 LTC2412 LTC2413 LTC2414/LTC2418 LTC2415 LTC2420 LTC2424/LTC2428 LTC2433-1 LTC2436-1 LTC2440 LTC2444/45/48/49 DESCRIPTION Dual Precision Instrumentation Switched Capacitor Building Block Precision Bandgap Reference, 5V Micropower Precision LDO Reference 24-Bit, No Latency ∆Σ ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 24-Bit, Fully Differential, No Latency ∆Σ ADC 24-Bit, No Latency ∆Σ ADC in MSOP 24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC 2-Channel, 24-Bit, Pin Compatible with LTC2439-1 24-Bit, No Latency ∆Σ ADC 8-/16-Channel, 24-Bit No Latency ∆Σ ADC 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate 20-Bit, No Latency ∆Σ ADC in SO-8 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs Differential Single Channel 16-Bit ∆Σ ADC 2-Channel Differential 16-Bit ∆Σ ADC High Speed, Low Noise 24-Bit ADC 8-/16-Channel High Speed, Low Noise 24-Bit ADC COMMENTS Precise, Charge Balanced Switching, Low Power 0.05% Max, 5ppm/°C Drift High Accuracy 0.04% Max, 3ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA 1.45µVRMS Noise, 2ppm INL 0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411 800nV Noise, 2ppm INL, 3ppm TUE, 200µA Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA Pin Compatible with the LTC2410 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408 Low Noise, 16-Bits at ±50mV Input Range Low Noise, 16-Bits at ±50mV Input Range 4kHz Output Rate, 200nV Noise, 24.6 ENOBs 4kHz MUX Rate, 200nV Noise
24391f LT/TP 0404 1K • PRINTED IN USA
28
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
VCC REF
+
FO SD1
REF –
CH0 LTC2439-1 CH1 SCK SDO 18 17 16
22
8 THERMOCOUPLE 10 15
CH15 CH10 GND
CS
24391 F30
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
