LTC2450IDCTRPBF

Features ■ ■ ■ ■ ■ ■ LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit DS ADC Description The LTC®2450 is an ultra-tiny 16-bit analog-to-digital converter. The LTC2450 uses a single 2.7V to 5.5V supply, accepts a single-ended analog input voltage, and communicates through an SPI interface. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and provides single-cycle settling time for multiplexed applications. The converter is available in a 6-pin, 2mm × 2mm DFN package. The internal oscillator does not require any external components. The LTC2450 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude. The LTC2450 is capable of up to 30 conversions per second and, due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. The LTC2450 includes continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. The converter uses its power supply voltage as the reference voltage and the single-ended, rail-to-rail input voltage range extends from GND to VCC. Following a conversion, the LTC2450 can automatically enter a sleep mode and reduce its power to less than 200nA. If the user samples the ADC once a second, the LTC2450 consumes an average of less than 50µW from a 2.7V supply. ■ ■ ■ ■ ■ ■ ■ ■ GND to VCC Single-Ended Input Range 0.02LSB RMS Noise 2LSB INL, No Missing Codes 2LSB Offset Error 4LSB Full-Scale Error Single Conversion Settling Time for Multiplexed Applications Single Cycle Operation with Auto Shutdown 350µA Supply Current 50nA Sleep Current 30 Conversions Per Second Internal Oscillator—No External Components Required Single Supply, 2.7V to 5.5V Operation SPI Interface Ultra-Tiny 2mm × 2mm DFN Package applications ■ ■ ■ ■ ■ ■ ■ System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. typical application 0.1µF VCC VIN LTC2450 GND 10µF Integral Nonlinearity, VCC = 3V 3.0 2.5 2.0 1.5 1.0 INL (LSB) 0.5 0 –0.5 –1.0 –1.5 2450 TA01 VCC = VREF = 3V 1k SENSE CLOSE TO CHIP 0.1µF CS SCK SDO 3-WIRE SPI INTERFACE TA = –45°C, 25°C, 90°C –2.0 –2.5 –3.0 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 2450 G02 2450fa  LTC2450 absolute MaxiMuM ratinGs (Notes 1, 2) pin conFiGuration TOP VIEW VCC 1 VIN 2 GND 3 7 6 SCK 5 SDO 4 CS Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (VIN) ............ –0.3V to (VCC + 0.3V) Digital Input Voltage...................... –0.3V to (VCC + 0.3V) Digital Output Voltage ................... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2450C ................................................ 0°C to 70°C LTC2450I.............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10sec) ................... 300°C DC PACKAGE 6-LEAD (2mm x 2mm) PLASTIC DFN TJMAX = 125°C, θJA = 102°C/W EXPOSED PAD (PIN7) IS GND, MUST BE SOLDERED TO PCB orDer inForMation Lead Free Finish TAPE AND REAL (MINI) TAPE AND REEL LTC2450CDC#TRMPBF LTC2450IDC#TRMPBF LTC2450CDC#TRPBF LTC2450IDC#TRPBF PART MARKING LCTR LCTR PACKAGE DESCRIPTION 6-Lead (2mm × 2mm) Plastic DFN 6-Lead (2mm × 2mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics PARAMETER Resolution (No missing codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise Power Supply Rejection DC (Note 3) (Note 4) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) CONDITIONS ● ● ● MIN 16 TYP 2 2 0.02 0.01 0.02 1.4 MAX 10 8 0.02 UNITS Bits LSB LSB LSB/°C % of FS LSB/°C µVRMS dB ● 100Hz-100kHz 80 analoG input The ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. SYMBOL VIN CIN IDC_LEAK (VIN) ICONV PARAMETER Input Voltage Range IN Sampling Capacitance IN DC Leakage Current Input Sampling Current (Note 9) VIN = GND (Note 5) VIN = VCC (Note 5) ● ● CONDITIONS ● MIN 0 TYP 0.35 MAX VCC UNITS pF –10 –10 1 1 50 10 10 nA nA nA 2450fa  LTC2450 power requireMents The ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep CS = GND (Note 6) CS = VCC (Note 6) CONDITIONS ● ● ● MIN 2.7 TYP MAX 5.5 UNITS V µA µA 350 0.05 600 0.5 DiGital inputs anD DiGital outputs The ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 2) SYMBOL VIH VIL IIN CIN VOH VOL IOZ PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current IO = –800mA IO = –1.6mA ● ● ● CONDITIONS ● ● ● MIN VCC – 0.3 TYP MAX 0.3 UNITS V V µA pF V –10 10 VCC – 0.5 10 0.4 –10 10 V µA tiMinG characteristics The ● denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. SYMBOL tCONV fSCK tlSCK thSCK t1 t2 t3 tKQ PARAMETER Conversion Time SCK Frequency Range SCK Low Period SCK High Period CS Falling Edge to SDO Low Z CS Rising Edge to SDO High Z CS Falling Edge to SCK Falling Edge SCK Falling Edge to SDO Valid (Note 7) (Notes 7, 8) (Notes 7, 8) CONDITIONS ● ● ● ● ● ● ● ● MIN 29 250 250 0 0 100 0 TYP 33.3 MAX 42 2 UNITS ms MHz ns ns 100 100 100 ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. Note 3: Guaranteed by design, not subject to test. Note 4: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Guaranteed by design, test correlation and 3 point transfer curve measurement. Note 5: CS = VCC. A positive current is flowing into the DUT pin. Note 6: SCK = VCC or GND. SDO is high impedance. Note 7: See Figure 3. Note 8: See Figure 4. Note 9: Input sampling current is the average input current drawn from the input sampling network while the LTC2450 is actively sampling the input. 2450fa  LTC2450 typical perForMance characteristics Integral Nonlinearity, VCC = 5V 3.0 2.5 2.0 1.5 1.0 INL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 2450 G01 Integral Nonlinearity, VCC = 3V 3.0 2.5 2.0 1.5 1.0 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 2450 G02 Maximum INL vs Temperature 5.0 4.5 4.0 3.5 VCC = VREF = 5V VCC = VREF = 3V TA = –45°C, 25°C, 90°C INL (LSB) 0.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 2450 G03 TA = –45°C, 25°C, 90°C VCC = 5V VCC = 4.1V VCC = 3V Offset Error vs Temperature 5.0 4.5 4.0 OFFSET (LSB) VCC = 3V GAIN ERROR (LSB) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 2450 G04 Gain Error vs Temperature 5.0 4.5 TRANSITION NOISE RMS (µV) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 2450 G05 Transition Noise vs Temperature 3.00 2.75 2.50 2.25 2.00 1.75 1.50 VCC = 4.1V 1.25 1.00 0.50 0.75 0.25 0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 2450 G06 VCC = 5V VCC = 4.1V VCC = 4.1V VCC = 5V VCC = 3V VCC = 5V VCC = 3V Transition Noise vs Output Code 3.00 2.75 TRANSITION NOISE RMS (µV) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.50 0.75 0.25 0 0.80 1.00 0.40 0.60 0 0.20 OUTPUT CODE (NORMALIZED TO FULL SCALE) 2450 G07 Conversion Mode Power Supply Current vs Temperature 500 VCC = 5V VCC = 3V VCC = 4.1V TA = 25°C CONVERSION CURRENT (µA) 400 VCC = 5V VCC = 3V 300 200 100 0 –45 –25 35 15 –5 55 TEMPERATURE (°C) 75 95 2450 G08 2450fa  LTC2450 typical perForMance characteristics Sleep Mode Power Supply Current vs Temperature 250 Average Power Dissipation vs Temperature, VCC = 3V 10000 AVERAGE POWER DISSIPATION (µW) SLEEP MODE CURRENT (nA) 200 VCC = 5V 150 VCC = 4.1V 25Hz OUTPUT SAMPLE RATE 1000 10Hz OUTPUT SAMPLE RATE 100 100 1Hz OUTPUT SAMPLE RATE 50 VCC = 3V 0 –45 –25 35 15 –5 55 TEMPERATURE (°C) 75 95 10 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2450 G12 2450 G09 Power Supply Rejection vs Frequency at VCC 0 42 40 CONVERSION TIME (ms) 38 36 34 32 Conversion Period vs Temperature –20 REJECTION (dB) –40 VCC = 5V, 4.1V, 3V –60 –80 –100 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M 30 –45 –25 35 15 55 –5 TEMPERATURE (°C) 75 95 2450 G10 2450 G11 2450fa  LTC2450 pin Functions VCC (Pin 1): Positive Supply Voltage and Converter Reference Voltage. Bypass to GND (Pin 3) with a 10µF capacitor in parallel with a low series inductance 0.1µF capacitor located as close to the part as possible. VIN (Pin 2): Analog Input Voltage. GND (Pin 3): Ground. Connect to a ground plane through a low impedance connection. CS (Pin 4): Chip Select Active LOW Digital Input. A LOW on this pin enables the SDO digital output. A HIGH on this pin places the SDO output pin in a high impedance state. SDO (Pin 5): Three-State Serial Data Output. SDO is used for serial data output during the DATA OUTPUT state and can be used to monitor the conversion status. SCK (Pin 6): Serial Clock Input. SCK synchronizes the serial data output. While digital data is available (the ADC is not in CONVERT state) and CS is LOW (ADC is not in SLEEP state) a new data bit is produced at the SDO output pin following every falling edge applied to the SCK pin. Exposed Pad (Pin 7): Ground. The Exposed Pad must be soldered to the same point as Pin 3. Functional block DiaGraM VCC VCC VIN GND REF + 16 BIT DS A/D CONVERTER REF – SPI INTERFACE INTERNAL OSCILLATOR CS SDO SCK 2450 BD Figure 1. Functional Block Diagram 2450fa  LTC2450 applications inForMation CONVERTER OPERATION Converter Operation Cycle The LTC2450 is a low power, delta-sigma analog-todigital converter with a simple 3-wire interface (see Figure 1). Its operation is composed of three successive states: CONVERT, SLEEP and DATA OUTPUT. The operating cycle begins with the CONVERT state, is followed by the SLEEP state and ends with the DATA OUTPUT state (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock input (SCK) and the active low chip select input (CS). The CONVERT state duration is determined by the LTC2450 conversion time (nominally 33.3 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. After the completion of a conversion, the LTC2450 enters the SLEEP state and remains here until both the chip select and clock inputs are low (CS = SCK = LOW). Following this condition the ADC transitions into the DATA OUTPUT state. POWER-ON RESET While in the SLEEP state, whenever the chip select input is pulled high (CS = HIGH), the LTC2450’s power supply current is reduced to less than 200nA. When the chip select input is pulled low (CS = LOW), and SCK is maintained at a HIGH logic level, the LTC2450 will return to a normal power consumption level. During the SLEEP state, the result of the last conversion is held indefinitely in a static register. Upon entering the DATA OUTPUT state, SDO outputs the most significant bit (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this result and it corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low, which corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2450 will enter the CONVERT state and initiate a new conversion cycle. Power-Up Sequence When the power supply voltage VCC applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2450 starts a conversion cycle and follows the succession of states described in Figure 2. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. 2450fa CONVERT SLEEP NO SCK = LOW AND CS = LOW? YES DATA OUTPUT NO 16TH FALLING EDGE OF SCK OR CS = HIGH? YES 2450 F02 Figure 2. LTC2450 State Transition Diagram  LTC2450 applications inForMation Ease of Use The LTC2450 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2450 performs offset and full-scale calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is extreme stability of the ADC performance with respect to time and temperature. The LTC2450 includes a proprietary input sampling scheme that reduces the average input current several orders of magnitude as compared to traditional delta sigma architectures. This allows external filter networks to interface directly to the LTC2450. Since the average input sampling current is 50nA, an external RC lowpass filter using a 1kΩ and 0.1µF results in