FEATURES
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LTC2452 Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface DESCRIPTION
The LTC®2452 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. The LTC2452 uses a single 2.7V to 5.5V supply and communicates through an SPI interface. The ADC is available in an 8-pin, 3mm × 2mm DFN package or TSOT-23 package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. The LTC2452 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude when compared to conventional delta-sigma converters. Additionally, due to its architecture, there is negligible current leakage between the input pins. The LTC2452 can sample at 60 conversions per second, and due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. The LTC2452 includes continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. The converter has an external REF pin and the differential input voltage range can extend up to ±VREF. Following a single conversion, the LTC2452 can automatically enter a sleep mode and reduce its supply current to less than 0.2μA. If the user reads the ADC once a second, the LTC2452 consumes an average of less than 50μW from a 2.7V supply.
Integral Nonlinearity, VCC = 3V
3 2.7V TO 5.5V 0.1μF 0.1μF IN+ REF VCC INL (LSB) CS LTC2452 SCK SDO GND –2
2452 TA01a
±VCC Differential Input Range 16-Bit Resolution (Including Sign), No Missing Codes 2LSB Offset Error 4LSB Full-Scale Error 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 800μA Supply Current 0.2μA Sleep Current Internal Oscillator—No External Components Required SPI Interface Ultra-Tiny 3mm × 2mm DFN and TSOT-23 Packages
APPLICATIONS
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System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
2 1 10μF
TA = –45°C, 25°C, 90°C 0 –1
10k
10k IN–
3-WIRE SPI INTERFACE
10k
R
0.1μF
–3
–3
1 2 –2 –1 0 DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 TA01b
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LTC2452 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN–) .. –0.3V to (VCC + 0.3V) Reference Voltage (VREF) .............. –0.3V to (VCC + 0.3V) Digital Voltage (VSDO, VSCK, VCS) .. –0.3V to (VCC + 0.3V)
Storage Temperature Range................... –65°C to 150°C Operating Temperature Range LTC2452C ................................................ 0°C to 70°C LTC2452I.............................................. –40°C to 85°C
PIN CONFIGURATION
TOP VIEW SCK GND REF VCC 1 2 3 4 9 8 7 6 5 SDO CS IN
+
TOP VIEW SCK 1 GND 2 REF 3 VCC 4 8 SDO 7 CS 6 IN+ 5 IN–
IN–
DD8 PACKAGE 8-LEAD (3mm 2mm) PLASTIC DFN C/I GRADE TJMAX = 125°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 C/I GRADE TJMAX = 125°C, θJA = 140°C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C LTC2452CDDB#TRMPBF LTC2452CDDB#TRPBF LDNJ 8-Lead Plastic (3mm × 2mm) DFN LTC2452IDDB#TRMPBF LTC2452IDDB#TRPBF LDNJ 8-Lead Plastic (3mm × 2mm) DFN LTC2452CTS8#TRMPBF LTC2452CTS8#TRPBF LTDPK 8-Lead Plastic TSOT-23 LTC2452ITS8#TRMPBF LTC2452ITS8#TRPBF LTDPK 8-Lead Plastic TSOT-23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise Power Supply Rejection DC
l
ELECTRICAL CHARACTERISTICS
CONDITIONS (Note 3) (Note 4)
l l l
MIN 16
TYP 1 2 0.02 0.01 0.02 2.2 80
MAX 10 10 0.02
UNITS Bits LSB LSB LSB/°C % of FS LSB/°C μVRMS dB
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LTC2452 ANALOG INPUTS AND REFERENCES
SYMBOL VIN VIN
+ –
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PARAMETER Positive Input Voltage Range Negative Input Voltage Range Reference Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN– IN+, IN– Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current REF DC Leakage Current Input Sampling Current (Note 5) VIN = GND (Note 10) VIN = VCC (Note 10) VIN = GND (Note 10) VIN = VCC (Note 10) VREF = 3V (Note 10)
l l l l l
CONDITIONS
l l l
MIN 0 0 2.5
TYP
MAX VCC VCC VCC
UNITS V V V LSB LSB pF
VREF VOR+, VUR+ VOR–, VUR– CIN IDC_LEAK(IN+) IDC_LEAK(IN–) IDC_LEAK(REF) ICONV
VREF = 5V, VIN– = 2.5V (See Figure 3) VREF = 5V, VIN+ = 2.5V (See Figure 3) –10 –10 –10 –10 –10
8 8 0.35 1 1 1 1 1 50 10 10 10 10 10
nA nA nA nA nA nA
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep CS = GND (Note 6) CS = VCC (Note 6) CONDITIONS
l l l
POWER REQUIREMENTS
MIN 2.7
TYP
MAX 5.5
UNITS V μA μA
800 0.2
1200 0.6
The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL VIH VIL IIN CIN VOH VOL IOZ PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current IO = –800μA IO = 1.6mA
l l l
DIGITAL INPUTS AND DIGITAL OUTPUTS
CONDITIONS
MIN
l l l
TYP
MAX 0.3
UNITS V V μA pF V
VCC – 0.3 –10 10 VCC – 0.5 0.4 –10 10 10
V μA
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LTC2452 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL tCONV fSCK tlSCK thSCK t1 t2 t3 tKQ PARAMETER Conversion Time SCK Frequency Range SCK Low Period SCK High Period CS Falling Edge to SDO Low Z CS Rising Edge to SDO High Z CS Falling Edge to SCK Falling Edge SCK Falling Edge to SDO Valid (Note 7) (Notes 7, 8) (Notes 7, 8) CONDITIONS
l l l l l l l l
MIN 13 250 250 0 0 100 0
TYP 16.6
MAX 23 2
UNITS ms MHz ns ns
100 100 100
ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = VREF VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2. Note 3. Guaranteed by design, not subject to test. Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation.
Note 5: CS = VCC. A positive current is flowing into the DUT pin. Note 6: SCK = VCC or GND. SDO is high impedance. Note 7: See Figure 4. Note 8: See Figure 5. Note 9: Input sampling current is the average input current drawn from the input sampling network while the LTC2452 is actively sampling the input. Note 10: A positive current is flowing into the DUT pin.
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, unless otherwise noted)
Integral Nonlinearity, VCC = 5V
3 2 1 INL (LSB) 0 TA = –45°C, 25°C –1 –2 –3 TA = 90°C INL (LSB) 3 2 1 0 –1 –2 –3 –5 –4 –3 –2 –1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5
Integral Nonlinearity, VCC = 3V
3 2 1 INL (LSB) TA = –45°C, 25°C, 90°C 0 –1 –2
Maximum INL vs Temperature
VCC = VREF = 5V, 4.1V, 3V
–3
1 2 –2 –1 0 DIFFERENTIAL INPUT VOLTAGE (V)
3
2452 G02
–3 –50
–25
25 50 0 TEMPERATURE (°C)
75
100
2452 G03
2452 G01
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LTC2452 TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs Temperature
5 4 3 OFFSET ERROR (LSB) GAIN ERROR (LSB) 2 1 0 –1 –2 –3 –4 –5 –50 –25 25 50 0 TEMPERATURE (°C) 75 100
2452 G04
(TA = 25°C, unless otherwise noted)
Gain Error vs Temperature
5 4 3 2 1 0 –1 –2 –3 –4 –5 –50 –25 25 50 0 TEMPERATURE (°C) 75 100
2452 G05
Transition Noise vs Temperature
10 9 TRANSITION NOISE RMS (μV) 8 7 6 5 4 3 2 1 0 –50 –25 VCC = 3V VCC = 5V
VCC = VREF = 3V
VCC = VREF = 4.1V VCC = VREF = 5V
VCC = VREF = 5V
VCC = VREF = 4.1V VCC = VREF = 3V
25 50 0 TEMPERATURE (°C)
75
100
2452 G06
Conversion Mode Power Supply Current vs Temperature
900 800 CONVERSION CURRENT (μA) 700 600 500 400 300 200 100 0 –50 –25 25 50 0 TEMPERATURE (°C) 75 100
2452 G07
Sleep Mode Power Supply Current vs Temperature
250 10000 AVERAGE POWER DISSIPATION (μW)
Average Power Dissipation vs Temperature, VCC = 3V
VCC = 5V VCC = 4.1V VCC = 3V SLEEP CURRENT (nA)
200 VCC = 5V 150
1000
25Hz OUTPUT SAMPLE RATE
10Hz OUTPUT SAMPLE RATE 100 1Hz OUTPUT SAMPLE RATE 10
100
VCC = 4.1V
50
VCC = 3V
0 –50
–25
25 50 0 TEMPERATURE (°C)
75
100
2452 G08
0 –50
–25
25 50 0 TEMPERATURE (°C)
75
100
2452 G09
Power Supply Rejection vs Frequency at VCC
0 –20 CONVERSION TIME (ms) REJECTION (dB) –40 –60 –80 21 20 19 18 17 16 15
Conversion Time vs Temperature
VCC = 5V, 4.1V, 3V
–100 –120
1
10
100 1k 10k 100k FREQUENCY AT VCC (Hz)
1M
10M
14 –50
–25
25 50 0 TEMPERATURE (°C)
75
100
2452 G11
2452 G10
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LTC2452 PIN FUNCTIONS
SCK (Pin 1): Serial Clock Input. SCK synchronizes the serial data output. While digital data is available (the ADC is not in CONVERT state) and CS is LOW (ADC is not in SLEEP state) a new data bit is produced at the SDO output pin following every falling edge applied to the SCK pin. GND (Pin 2): Ground. Connect to a ground plane through a low impedance connection. REF (Pin 3): Reference Input. The voltage on REF can have any value between 2.5V and VCC. The reference voltage sets the full-scale range. VCC (Pin 4): Positive Supply Voltage. Bypass to GND (Pin 2) with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to the LTC2452 as possible. IN– (Pin 5), IN+ (Pin 6): Differential Analog Input. CS (Pin 7): Chip Select (Active LOW) Digital Input. A LOW on this pin enables the SDO digital output. A HIGH on this pin places the SDO output pin in a high impedance state. SDO (Pin 8): Three-State Serial Data Output. SDO is used for serial data output during the DATA OUTPUT state and can be used to monitor the conversion status. Exposed Pad (Pin 9): Ground. Must be soldered to PCB ground. For prototyping purposes, this pad may remain floating.
BLOCK DIAGRAM
3 REF 4 VCC CS 6 IN+ 16-BIT ΔΣ A/D CONVERTER SPI INTERFACE SDO SCK 7 8 1
–
5 IN– 16-BIT ΔΣ A/D CONVERTER
DECIMATING SINC FILTER INTERNAL OSCILLATOR
2, 9
GND
2452 BD
Figure 1. Functional Block Diagram
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LTC2452 APPLICATIONS INFORMATION
CONVERTER OPERATION Converter Operation Cycle The LTC2452 is a low power, fully differential, delta-sigma analog-to-digital converter with a simple 3-wire SPI interface (see Figure 1). Its operation is composed of three successive states: CONVERT, SLEEP and DATA OUTPUT. The operating cycle begins with the CONVERT state, is followed by the SLEEP state, and ends with the DATA OUTPUT state (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock input (SCK), and the active low chip select input (CS). The CONVERT state duration is determined by the LTC2452 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. After the completion of a conversion, the LTC2452 enters the SLEEP state and remains there until both the chip select and serial clock inputs are low (CS = SCK = LOW). Following this condition, the ADC transitions into the DATA OUTPUT state.
POWER-ON RESET
While in the SLEEP state, whenever the chip select input is pulled high (CS = HIGH), the LTC2452’s power supply current is reduced to less than 200nA. When the chip select input is pulled low (CS = LOW), and SCK is maintained at a HIGH logic level, the LTC2452 will return to a normal power consumption level. During the SLEEP state, the result of the last conversion is held indefinitely in a static register. Upon entering the DATA OUTPUT state, SDO outputs the sign (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2452 will enter the CONVERT state and initiate a new conversion cycle. Power-Up Sequence
CONVERT
SLEEP
NO
SCK = LOW AND CS = LOW?
YES
When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2452 starts a conversion cycle and follows the succession of states shown in Figure 2. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval.
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DATA OUTPUT
NO
16TH FALLING EDGE OF SCK OR CS = HIGH?
YES
2452 F02
Figure 2. LTC2452 State Transition Diagram
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LTC2452 APPLICATIONS INFORMATION
Ease of Use The LTC2452 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2452 performs offset calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2452 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the LTC2452. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1μF results in
