LTC2453CDDB-TRMPBF

FEATURES ■ ■ ■ ■ ■ ■ LTC2453 Ultra-Tiny, Differential, 16-Bit ΔΣ ADC With I2C Interface DESCRIPTION The LTC®2453 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. The LTC2453 uses a single 2.7V to 5.5V supply and communicates through an I2C interface. The ADC is available in an 8-pin, 3mm × 2mm DFN package or 8-pin, 3mm × 3mm TSOT package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. The LTC2453 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude lower than conventional delta-sigma converters. Additionally, due to its architecture, there is negligible current leakage between the input pins. The LTC2453 can sample at 60 conversions per second, and due to the very large oversampling ratio, has ex-tremely relaxed antialiasing requirements. The LTC2453 includes continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring accuracy over time and over the operating temperature range. The converter has external REF+ and REF– pins and the differential input voltage range can extend up to ±(VREF+ – VREF–). Following a single conversion, the LTC2453 can auto-matically enter a sleep mode and reduce its power to less than 0.2μA. If the user reads the ADC once a second, the LTC2453 consumes an average of less than 50μW from a 2.7V supply. ■ ■ ■ ■ ■ ■ ±VCC Differential Input Range 16-Bit Resolution (Including Sign), No Missing Codes 2LSB Offset Error 4LSB Full-Scale Error 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 800μA Supply Current 0.2μA Sleep Current Internal Oscillator—No External Components Required 2-Wire I2C Interface Ultra-Tiny 8-Pin 3mm × 2mm DFN and TSOT23 Packages APPLICATIONS ■ ■ ■ ■ ■ ■ ■ System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. No Latency ΔΣ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6208279, 6411242, 7088280, 7164378. TYPICAL APPLICATION 2.0 1.5 2.7V TO 5.5V 0.1μF 0.1μF IN+ 10k 10k IN– 10k R 0.1μF REF– REF+ VCC SCL LTC2453 SDA 2-WIRE I C INTERFACE 2 Integral Nonlinearity, VCC = 3V VCC = 3V VREF+ = 3V VREF– = 0V 1.0 INL (LSB) 0.5 0 –0.5 –1.0 TA = –45°C, 25°C, 90°C 10μF GND –1.5 2453 TA01 –2.0 –3 –2 –1 1 2 0 DIFFERENTIAL INPUT VOLTAGE (V) 3 2453 TA01b 2453fb 1 LTC2453 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN–) .. –0.3V to (VCC + 0.3V) Reference Voltage (VREF+, VREF–) .. –0.3V to (VCC + 0.3V) Digital Voltage (SDA, SCL) ............ –0.3V to (VCC + 0.3V) Storage Temperature Range................... –65°C to 150°C Operating Temperature Range LTC2453C ................................................ 0°C to 70°C LTC2453I.............................................. –40°C to 85°C PIN CONFIGURATION TOP VIEW GND 1 REF – 8 9 7 6 5 SDA SCL IN+ IN– GND 1 REF¯ 2 REF+ 3 VCC 4 TOP VIEW 8 SDA 7 SCL 6 IN+ 5 IN¯ 2 REF+ 3 VCC 4 DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN C/I GRADE TJMAX = 125°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 C/I GRADE TJMAX = 125°C, θJA = 140°C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) LTC2453CDDB#TRMPBF LTC2453IDDB#TRMPBF LTC2453CTS8#TRMPBF LTC2453ITS8#TRMPBF TAPE AND REEL LTC2453CDDB#TRPBF LTC2453IDDB#TRPBF LTC2453CTS8#TRPBF LTC2453ITS8#TRPBF PART MARKING* LDBQ LDBQ LTDCG LTDCG PACKAGE DESCRIPTION 8-Lead Plastic (3mm × 2mm) DFN 8-Lead Plastic (3mm × 2mm) DFN 8-Lead Plastic TSOT-23 8-Lead Plastic TSOT-23 TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Transition Noise Power Supply Rejection DC The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) CONDITIONS (Note 3) (Note 4) l l l l MIN 16 TYP 2 2 0.02 0.01 0.02 1.4 80 MAX 10 10 0.02 UNITS Bits LSB LSB LSB/°C % of FS LSB/°C μVRMS dB 2453fb 2 LTC2453 ANALOG INPUTS AND REFERENCES SYMBOL VIN VIN + – The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER Positive Input Voltage Range Negative Input Voltage Range Positive Reference Voltage Range Negative Reference Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN– IN+, IN– Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current VIN = GND (Note 8) VIN = VCC (Note 8) VIN = GND (Note 8) VIN = VCC (Note 8) VREF = 3V (Note 8) l l l l l CONDITIONS l l MIN 0 0 VCC – 2.5 0 TYP MAX VCC VCC VCC VCC – 2.5 UNITS V V V V LSB LSB pF VREF+ VREF– VOR+, VUR+ VOR–, VUR– CIN IDC_LEAK(IN+) IDC_LEAK(IN–) VREF+ – VREF– ≥ 2.5V VREF+ – VREF– ≥ 2.5V VREF = 5V, VIN– = 2.5V (See Figure 2) VREF = 5V, VIN+ = 2.5V (See Figure 2) l l 8 8 0.35 –10 –10 –10 –10 –10 1 1 1 1 1 50 10 10 10 10 10 nA nA nA nA nA nA IDC_LEAK(REF+, REF–) REF+, REF– DC Leakage Current ICONV Input Sampling Current (Note 5) POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Sleep The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS l l l MIN 2.7 TYP MAX 5.5 UNITS V μA μA 800 0.2 1200 0.6 I2C INPUTS AND OUTPUTS SYMBOL VIH VIL II VHYS VOL IIN CI CB PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) CONDITIONS l l l MIN 0.7VCC TYP MAX 0.3VCC UNITS V V μA V V μA pF pF –10 0.05VCC 10 0.4 1 Hysteresis of Schmidt Trigger Inputs Low Level Output Voltage (SDA) Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line (Note 3) I = 3mA 0.1VCC ≤ VIN ≤ 0.9VCC l l l l l 10 400 2453fb 3 LTC2453 I2C TIMING CHARACTERISTICS SYMBOL tCONV fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF tOF tSP PARAMETER Conversion Time SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Pin HIGH Period of the SCL Pin Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for SDA, SCL Signals Fall Time for SDA, SCL Signals Set-Up Time for STOP Condition Bus Free Time Between a Stop and Start Condition Output Fall Time VIHMIN to VILMAX Input Spike Suppression Bus Load CB 10pF to 400pF (Note 6) (Note 6) (Note 6) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) CONDITIONS l l l l l l l l l l l l l l MIN 13 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 20 + 0.1CB TYP 16.6 MAX 23 400 UNITS ms kHz μs μs μs μs 0.9 300 300 μs ns ns ns μs μs 250 50 ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREF = VREF+ – VREF–, VREFCM = (VREF+ + VREF–)/2, FS = VREF+ – VREF–; VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF ; VINCM = (VIN+ + VIN–)/2. Note 3. Guaranteed by design, not subject to test. Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation. Note 5. Input sampling current is the average input current drawn from the input sampling network while the LTC2453 is converting. Note 6. CB = capacitance of one bus line in pF. Note 7. All values refer to VIH(MIN) and VIL(MAX) levels. Note 8. A positive current is flowing into the DUT pin. TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity, VCC = 5V 2.0 1.5 1.0 INL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 –5 –4 –3 –2 –1 0 1 2 3 4 DIFFERENTIAL INPUT VOLTAGE (V) 5 TA = –45°C, 25°C, 90°C VCC = 5V VREF+ = 5V VREF– = 0V 2.0 1.5 1.0 VCC = 3V VREF+ = 3V VREF– = 0V (TA = 25°C, unless otherwise noted) Maximum INL vs Temperature 2.0 VCC = VREF+ = 5V, 4.1V, 3V Integral Nonlinearity, VCC = 3V 1.5 INL (LSB) TA = –45°C, 25°C, 90°C 0.5 0 –0.5 –1.0 –1.5 –2.0 –3 1.0 0.5 1 2 0 DIFFERENTIAL INPUT VOLTAGE (V) –2 –1 3 2453 G02 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G03 2453 G01 2453fb 4 LTC2453 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs Temperature 5 4 OFFSET ERROR (LSB) GAIN ERROR (LSB) 3 2 1 VCC = VREF+ = 5V 0 –1 –50 5 (TA = 25°C, unless otherwise noted) Transition Noise vs Temperature 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 VCC = 4.1V Gain Error vs Temperature 4 VCC = VREF+ = 3V VCC = VREF+ = 4.1V VCC = VREF+ = 3V VCC = VREF+ = 4.1V 3 2 TRANSITION NOISE RMS (μV) VCC = 5V VCC = 3V 1 VCC = VREF+ = 5V –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G04 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G05 –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G06 Transition Noise vs Output Code 3.0 2.5 2.0 1.5 1.0 0.5 0 –32768 VCC = VREF+ = 5V VCC = VREF+ = 3V 1200 Conversion Mode Power Supply Current vs Temperature 250 60Hz OUTPUT SAMPLE RATE CONVERSION CURRENT (μA) 1000 800 600 400 200 0 –50 VCC = 3V VCC = 4.1V SLEEP CURRENT (nA) VCC = 5V 200 Sleep Mode Power Supply Current vs Temperature TRANSITION NOISE RMS (μV) VCC = 5V 150 VCC = 4.1V 100 50 VCC = 3V –16384 0 16384 OUTPUT CODE 32768 2453 G07 –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G08 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G09 Average Power Dissipation vs Temperature, VCC = 3V 10000 AVERAGE POWER DISSIPATION (μW) 0 Power Supply Rejection vs Frequency at VCC 21 VCC = 4.1V VREF+ = 2.7V VREF– = 0V VIN+ = 1V VIN– = 2V 20 CONVERSION TIME (ms) Conversion Time vs Temperature 1000 25Hz OUTPUT SAMPLE RATE REJECTIOIN (dB) –20 VCC = 3V 19 VCC = 4.1V 18 VCC = 5V 17 16 15 10Hz OUTPUT SAMPLE RATE 100 1Hz OUTPUT SAMPLE RATE –40 –60 10 –80 1 –50 –100 –25 0 25 50 TEMPERATURE (°C) 75 100 2453 G10 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M 14 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 2453 G12 2453 G11 2453fb 5 LTC2453 PIN FUNCTIONS GND (Pin 1): Ground. Connect to a ground plane through a low impedance connection. REF– (Pin 2), REF+ (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF–, by at least 2.5V. The differential reference voltage (VREF = REF+ to REF–) sets the full-scale range. VCC (Pin 4): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to the part as possible. IN– (Pin 5), IN+ (Pin 6): Differential Analog Input. SCL (Pin 7): Serial Clock Input of the I2C Interface. The LTC2453 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted into the SDA pin on the rising edges of SCL and output through the SDA pin on the falling edges of SCL. SDA (Pin 8): Bidirectional Serial Data Line of the I2C Interface. The conversion result is output through the SDA pin. The pin is high impedance unless the LTC2453 is in the data output mode. While the LTC2453 is in the data output mode, SDA is an open drain pull down (which requires an external 1.7k pull-up resistor to VCC). Exposed Pad (Pin 9, DFN Only): Ground. Must be soldered to PCB ground. BLOCK DIAGRAM 3 REF+ 4 VCC 6 IN+ 16-BIT Δ∑ A/D CONVERTER I2C INTERFACE SCL SDA 7 8 – 5 IN– 16-BIT Δ∑ A/D CONVERTER DECIMATING SINC FILTER INTERNAL OSCILLATOR 2 REF– 1 GND 2453 BD 2453fb 6 LTC2453 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2453 is a low-power, fully differential, delta-sigma analog-to-digital converter with an I2C interface. Its operation, as shown in Figure 1, is composed of three successive states: CONVERSION, SLEEP and DATA OUTPUT. Initially, at power up, the LTC2453 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by several orders of magnitude. The part remains in the sleep state as long as it is not addressed for a read operation. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. POWER-ON RESET edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated by a stop condition following a valid read operation, or by the conclusion of a complete read cycle (all 16 bits read out of the device). Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2453 starts a conversion cycle and follows the succession of states described in Figure 1. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage VCC is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Ease of Use The LTC2453 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions. The LTC2453 performs offset calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is extreme stability of the ADC performance with respect to time and temperature. The LTC2453 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the LTC2453. Since the average input sampling current is 50nA, an external RC lowpass filter using a 1kΩ and 0.1μF results in (2.5V + VREF–). The LTC2453 differential reference input range is 2.5V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF– can be shorted to GND. Input Voltage Range For most applications, VREF– ≤ (VIN+, VIN–) ≤ VREF+. Under these conditions the output code is given (see Data Format section) as 32768 • (VIN+ – VIN–)/(VREF+ – VREF–) + 32768. The output of the LTC2453 is clamped at a minimum value of 0 and clamped at a maximum value of 65535. The LTC2453 includes a proprietary system that can, typically, correctly digitize each input 8LSB above VREF+ and below VREF–, if the LTC2453’s output is not clamped. As an example (Figure 2), if the user desires to measure a signal slightly below ground, the user could set VIN– = VREF– = GND, and VREF+ = 5V. If VIN+ = GND, the output code would be approximately 32768. If VIN+ = GND – 8LSB = –1.22 mV, the output code would be approximately 32760. 32788 32784 32780 32776 OUTPUT CODE 32772 32768 32764 32760 32756 32752 32748 –0.001 –0.005 0.005 0 VIN+/VREF+ 0.001 0.0015 2453 F02 I2C INTERFACE The LTC2453 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the data line (SDA) LOW and never drive it HIGH. SDA must be externally connected to the supply through a pull-up resistor. When the data line is free, it is HIGH. Data on the I2C bus can be transferred at rates up to 100kbits/s in the Standard-Mode and up to 400kbits/s in the Fast-Mode. The VCC power should not be removed from the device when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. Each device on the I2C bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed by the master are considered a slave. The address of the LTC2453 is 0010100. The LTC2453 can only be addressed as a slave. It can only transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2453 and the serial data line SDA is bidirectional. Figure 3 shows the definition of the I2C timing. The START and STOP Conditions A START (S) condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP (P) condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free after a STOP is generated. START and STOP conditions are always generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START timing is functionally identical to the START and is used for reading from the device before the initiation of a new conversion. 2453fb SIGNALS BELOW GND Figure 2. Output Code vs VIN+ with VIN– = 0 and VREF– = 0 8 LTC2453 APPLICATIONS INFORMATION SDA tf tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF SCL tHD(STA) S tHD(DAT) tHIGH tSU(STA) Sr tSU(STO) P S 2453 F03 Figure 3. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus Data Transferring After the START condition, the bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA LOW or issue a Not Acknowledge (NAK) by leaving the SDA line HIGH impedance (the external pull-up resistor will hold the line HIGH). Change of data only occurs while the clock line (SCL) is LOW. Data Format After a START condition, the master sends a 7-bit address followed by a read request (R) bit. The bit R is 1 for a Read Request. If the 7-bit address matches the LTC2453’s address (hard-wired at 0010100) the ADC is selected. When the device is addressed during the conversion state, it does not accept the request and issues a NAK by leaving the SDA line HIGH. If the conversion is complete, the LTC2453 issues an ACK by pulling the SDA line LOW. Following the ACK, the LTC2453 can output data. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 4). The first bit output by the LTC2453, the MSB, is the sign, which is 1 for VIN+ ≥ VIN– and 0 for VIN+ < VIN– (see Table 1). The MSB (D15) is followed by successively less significant bits (D14, D13…) until the LSB is output by the LTC2453. This sequence is shown in Figure 5. I2C OPERATION SEQUENCE Continuous Read Conversions from the LTC2453 can be continuously read, see Figure 6. At the end of a read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not complete and a valid address selects the device, the LTC2453 generates a NAK signal indicating the conversion cycle is in progress. Discarding a Conversion Result and Initiating a New Conversion It is possible to start a new conversion without reading the old result, as shown in Figure 7. Following a valid 7-bit address, a read request (R) bit, and a valid ACK, a STOP command will start a new conversion. PRESERVING THE CONVERTER ACCURACY The LTC2453 is designed to dramatically reduce the conversion result’s sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the range of 0.5V to VCC – 0.5V may result in additional current leakage from the part. 2453fb 9 LTC2453 APPLICATIONS INFORMATION 1 SCL 7 8 9 1 2 3 8 9 1 2 3 8 9 SDA 7-BIT ADDRESS R D15 (SGN) MSB D14 D13 D8 D7 D6 D5 D0 LSB START BY MASTER SLEEP ACK BY LTC2453 ACK BY MASTER DATA OUTPUT NACK BY MASTER CONV Figure 4. Read Sequence Timing Diagram Table 1. LTC2453 Output Data Format. FS = VREF+ – VREF-. DIFFERENTIAL INPUT VOLTAGE VIN+ - VIN≥FS FS - 1LSB 0.5 • FS 0.5 • FS - 1LSB 0 -1LSB -0.5 • FS -0.5 • FS - 1LSB ≤-FS D15 (MSB) 1 1 1 1 1 0 0 0 0 D14 1 1 1 0 0 1 1 0 0 D13 1 1 0 1 0 1 0 1 0 D12 ... D2 1 1 0 1 0 1 0 1 0 D1 1 1 0 1 0 1 0 1 0 D0 CORRESPONDING (LSB) DECIMAL VALUE 1 0 0 1 0 1 0 1 0 65535 65534 49152 49151 32768 32767 16384 16383 0 S CONVERSION 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATA OUTPUT P CONVERSION 2453 F05 Figure 5. The LTC2453 Coversion Sequence S CONVERSION 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATA OUTPUT P CONVERSION S 7-BIT ADDRESS (0010100) SLEEP R ACK READ DATA OUTPUT P CONVERSION 2453 F06 Figure 6. Consecutive Reading at the Same Configuration S CONVERSION 7-BIT ADDRESS (0010100) SLEEP R ACK READ (OPTIONAL) DATA OUTPUT P CONVERSION 2453 F07 Figure 7. Start a New Conversion without Reading Old Conversion Result 2453fb 10 LTC2453 APPLICATIONS INFORMATION Driving VCC and GND In relation to the VCC and GND pins, the LTC2453 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. A 0.1μF, high quality, ceramic capacitor in parallel with a 10μF ceramic capacitor should be connected between the VCC and GND pins, as close as possible to the package. The 0.1μF capacitor should be placed closest to the ADC package. It is also desirable to avoid any via in the circuit path, starting from the converter VCC pin, passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. Very low impedance ground and power planes, and star connections at both VCC and GND pins, are preferable. The VCC pin should have three distinct connections: the VCC ILEAK REF+ ILEAK RSW 15k (TYP) first to the decoupling capacitors described above, the second to the ground return for the input signal source, and the third to the ground return for the power supply voltage source. Driving REF+ and REF– A simplified equivalent circuit for REF+ and REF– is shown in Figure 8. Like all other A/D converters, the LTC2453 is only as accurate as the reference it is using. Therefore, it is important to keep the reference line quiet by careful low and high frequency power supply decoupling. The LT6660 reference is an ideal match for driving the LTC2453’s REF+ pin. The LTC6660 is available in a 2mm × 2mm DFN package with 2.5V, 3V, 3.3V and 5V options. A 0.1μF, high quality, ceramic capacitor in parallel with a 10μF ceramic capacitor should be connected between the REF+/REF– and GND pins, as close as possible to the package. The 0.1μF capacitor should be placed closest to the ADC. Driving VIN+ and VIN– The input drive requirements can best be analyzed using the equivalent circuit of Figure 9. The input signal VSIG is connected to the ADC input pins (IN+ and IN–) through an equivalent source resistance RS. This resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pins. VCC RSW 15k (TYP) CEQ 0.35pF (TYP) VCC RSW 15k (TYP) CEQ 0.35pF (TYP) VCC ILEAK IN+ ILEAK RSW 15k (TYP) VCC ILEAK IN– ILEAK RSW 15k (TYP) CEQ 0.35pF (TYP) RS SIG+ ILEAK IN+ CIN CPAR ILEAK + – ICONV VCC ILEAK REF– ILEAK RSW 15k (TYP) 2453 F08 RS SIG– ILEAK IN– CIN CPAR ILEAK + – ICONV 2453 F09 Figure 8. LTC2453 Analog Input/Reference Equivalent Circuit Figure 9. LTC2453 Input Drive Equivalent Circuit 2453fb 11 LTC2453 APPLICATIONS INFORMATION Optional input capacitors CIN are also connected to the ADC input pins. This capacitor is placed in parallel with the ADC input parasitic capacitance CPAR . Depending on the PCB layout, CPAR has typical values between 2pF and 15pF. In addition, the equivalent circuit of Figure 9 includes the converter equivalent internal resistor RSW and sampling capacitor CEQ. There are some immediate trade-offs in RS and CIN without needing a full circuit analysis. Increasing RS and CIN can give the following benefits: 1) Due to the LTC2453’s input sampling algorithm, the input current drawn by either VIN+ or VIN– over a conversion cycle is 50nA. A high RS • CIN attenuates the high frequency components of the input current, and RS values up to 1k result in