LTC2460CDD

FEATURES n n n n n n n n n n n n n LTC2460/LTC2462 Ultra-Tiny, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference DESCRIPTION The LTC®2460/LTC2462 are ultra tiny, 16-Bit analog-todigital converters with an integrated precision reference. They use a single 2.7V to 5.5V supply and communicate through an SPI Interface. The LTC2460 is single-ended with a 0V to VREF input range and the LTC2462 is differential with a ±VREF input range. Both ADC’s include a 1.25V integrated reference with 2ppm/°C drift performance and 0.1% initial accuracy. The converters are available in a 12-pin DFN 3mm × 3mm package or an MSOP-12 package. They include an integrated oscillator and perform conversions with no latency for multiplexed applications. The LTC2460/LTC2462 include a proprietary input sampling scheme that reduces the average input current several orders of magnitude when compared to conventional delta sigma converters. Following a single conversion, the LTC2460/LTC2462 automatically power down the converter and can also be configured to power down the reference. When both the ADC and reference are powered down, the supply current is reduced to 200nA. The LTC2460/LTC2462 can sample at 60 conversions per second, and due to the very large oversampling ratio, have extremely relaxed antialiasing requirements. Both include continuous internal offset and fullscale calibration algorithms which are transparent to the user, ensuring accuracy over time and the operating temperature range. 16-Bit Resolution, No Missing Codes Internal Reference, High Accuracy 10ppm/°C (Max) Single-Ended (LTC2460) or Differential (LTC2462) 2LSB Offset Error 0.01% Gain Error 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 1.5mA Supply Current 2μA (Max) Sleep Current Internal Oscillator—No External Components Required SPI Interface Ultra-Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages APPLICATIONS n n n n n n n System Monitoring Environmental Monitoring Direct Temperature Measurements Instrumentation Industrial Process Control Data Acquisition Embedded ADC Upgrades L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378. TYPICAL APPLICATION 2.7V TO 5.5V REFERENCE OUTPUT VOLTAGE (V) 1.2520 1.2515 1.2510 1.2505 1.2500 1.2495 1.2490 1.2485 1.2480 –50 0.1μF 0.1μF IN + VREF vs Temperature 0.1μF REFOUT COMP VCC SCK LTC2462 IN– SDO CS REF– GND 0.1μF 10μF 10k 10k SPI INTERFACE 10k 0.1μF R 24602 TA01a –30 –10 10 30 50 TEMPERATURE (°C) 70 90 24602 TA01b 24602f 1 LTC2460/LTC2462 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (IN+, IN–, IN, REF–, COMP REFOUT) ............................ –0.3V to (VCC + 0.3V) , Digital Voltage (VSDI, VSDO, VSCK, VCS) ................. –0.3V to (VCC + 0.3V) Storage Temperature Range................... –65°C to 150°C Operating Temperature Range LTC2460C/LTC2462C ............................... 0°C to 70°C LTC2460I/LTC2462I.............................. –40°C to 85°C PIN CONFIGURATION LTC2462 TOP VIEW REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 12 VCC 11 GND 10 IN– 9 IN+ 8 REF– 7 GND REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 TOP VIEW 12 11 10 9 8 7 VCC GND IN– IN+ REF– GND LTC2462 DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL LTC2460 TOP VIEW REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 12 VCC 11 GND 10 GND 9 IN 8 REF– 7 GND LTC2460 MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W TOP VIEW REFOUT COMP CS SDI SCK SDO 1 2 3 4 5 6 12 11 10 9 8 7 VCC GND GND IN REF– GND DD PACKAGE 12-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W ORDER INFORMATION LEAD FREE FINISH LTC2460CDD#PBF LTC2460IDD#PBF LTC2460CMS#PBF LTC2460IMS#PBF LTC2462CDD#PBF LTC2462IDD#PBF LTC2462CMS#PBF LTC2462IMS#PBF TAPE AND REEL LTC2460CDD#TRPBF LTC2460IDD#TRPBF LTC2460CMS#TRPBF LTC2460IMS#TRPBF LTC2462CDD#TRPBF LTC2462IDD#TRPBF LTC2462CMS#TRPBF LTC2462IMS#TRPBF PART MARKING* LFDQ LFDQ 2460 2460 LDXM LDXM 2462 2462 PACKAGE DESCRIPTION 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic MSOP-12 12-Lead Plastic MSOP-12 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic (3mm × 3mm) DFN 12-Lead Plastic MSOP-12 12-Lead Plastic MSOP-12 TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 24602f 2 LTC2460/LTC2462 ELECTRICAL CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Gain Error Gain Error Drift Includes Contributions of ADC and Internal Reference Includes Contributions of ADC and Internal Reference C-Grade I-Grade l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) CONDITIONS (Note 3) (Note 4) l l l MIN 16 TYP 1 2 0.02 ±0.01 ±2 ±5 2.2 80 MAX 10 10 ±0.25 ±10 UNITS Bits LSB LSB LSB/°C % of FS ppm/°C ppm/°C μVRMS dB Transition Noise Power Supply Rejection DC ANALOG INPUTS specifications are at TA = 25°C. PARAMETER SYMBOL VIN+ VIN VIN VOR+, VUR+ VOR–, VUR– CIN IDC_LEAK(IN+, IN–, IN) IDC_LEAK(IN–) ICONV VREF – The l denotes the specifications which apply over the full operating temperature range, otherwise CONDITIONS LTC2462 LTC2462 LTC2460 VIN– = 0.625V (See Figure 3) VIN+ = 0.625V (See Figure 3) VIN = GND (Note 8) VIN = VCC (Note 8) VIN = GND (Note 8) VIN = VCC (Note 8) l l l l l l l l MIN 0 0 0 TYP MAX VREF VREF VREF UNITS V V V LSB LSB pF Positive Input Voltage Range Negative Input Voltage Range Input Voltage Range Overrange/Underrange Voltage, IN+ Overrange/Underrange Voltage, IN– IN+, IN–, IN Sampling Capacitance IN+, IN– DC Leakage Current (LTC2462) IN DC Leakage Current (LTC2460) IN– DC Leakage Current Input Sampling Current (Note 5) Reference Output Voltage Reference Voltage Coefficient 8 8 0.35 –10 –10 –10 –10 1.247 1 1 1 1 50 1.25 ±2 ±5 –90 l l 10 10 10 10 1.253 ±10 nA nA nA nA nA V ppm/°C ppm/°C dB mA μA mV/mA nV/√Hz (Note 11) C-Grade I-Grade 2.7V ≤ VCC ≤ 5.5V VCC = 5.5, Forcing Output to GND VCC = 5.5, Forcing Output to GND 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing , , CCOMP= 0.1μF CREFOUT = 0.1μF At f = 1kHz l Reference Line Regulation Reference Short Circuit Current COMP Pin Short Circuit Current Reference Load Regulation Reference Output Noise Density 35 200 3.5 30 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Nap Sleep CONDITIONS l l l l POWER REQUIREMENTS MIN 2.7 TYP MAX 5.5 UNITS V mA μA μA 24602f 1.5 800 0.2 2.5 1500 2 3 LTC2460/LTC2462 The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 2) SYMBOL VIH VIL IIN CIN VOH VOL IOZ PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current IO = –800μA IO = 1.6mA l l l DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS MIN l l l TYP MAX 0.3 UNITS V V μA pF V VCC – 0.3 –10 10 VCC – 0.5 0.4 –10 10 10 V μA TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C. SYMBOL tCONV fSCK tlSCK thSCK t1 t2 t3 tKQ t4 t5 PARAMETER Conversion Time SCK Frequency Range SCK Low Period SCK High Period CS Falling Edge to SDO Low Z CS Rising Edge to SDO High Z CS Falling Edge to SCK Falling Edge SCK Falling Edge to SDO Valid SDI Setup Before SCK↑ SDI Hold After SCK↑ (Note 7) (Note 3) (Note 3) (Notes 7, 8) (Notes 7, 8) CONDITIONS l l l l l l l l l l MIN 13 250 250 0 0 100 0 100 100 TYP 16.6 MAX 23 2 UNITS ms MHz ns ns 100 100 100 ns ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = VREF VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2. Note 3. Guaranteed by design, not subject to test. Note 4. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation. Note 5: CS = VCC. A positive current is flowing into the DUT pin. Note 6: SCK = VCC or GND. SDO is high impedance. Note 7: See Figure 4. Note 8: See Figure 5. Note 9: Input sampling current is the average input current drawn from the input sampling network while the LTC2460/LTC2462 is actively sampling the input. Note 10: A positive current is flowing into the DUT pin. Note 11: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. 24602f 4 LTC2460/LTC2462 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity 3 2 1 INL (LSB) INL (LSB) 0 –1 –2 –3 –1.25 VCC = 5.5V TA = –45°C, 25°C, 90°C 3 2 1 0 –1 –2 –3 –1.25 INL (LSB) (TA = 25°C, unless otherwise noted) Integral Nonlinearity VCC = 2.7V TA = –45°C, 25°C, 90°C 3 2 1 0 –1 –2 Maximum INL vs Temperature VCC = 5.5V, 4.1V, 2.7V 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 –3 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 24602 G03 24602 G01 24602 G02 Offset Error vs Temperature 5 4 3 OFFSET ERROR (LSB) 2 1 0 –1 –2 –3 –4 –5 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 VCC = 2.7V VCC = 4.1V VCC = 5.5V ADC GAIN ERROR (LSB) 25 ADC Gain Error vs Temperature 10 VCC = 5.5V 20 TRANSITION NOISE RMS (μV) 9 8 7 6 5 4 3 2 1 75 100 24602 G05 Transition Noise vs Temperature 15 10 VCC = 4.1V VCC = 2.7V 5 VCC = 2.7V 0 –50 VCC = 5.5V –25 0 25 50 TEMPERATURE (°C) 0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24602 G04 24602 G06 Conversion Mode Power Supply Current vs Temperature 2.0 1.9 CONVERSION CURRENT (mA) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 50 VCC = 2.7V SLEEP CURRENT (nA) VCC = 5.5V VCC = 4.1V 350 300 250 200 150 Sleep Mode Power Supply Current vs Temperature 1.2508 REFERENCE OUTPUT VOLTAGE (V) 1.2507 1.2506 1.2505 1.2504 1.2503 VREF vs Temperature VCC = 5.5V VCC = 4.1V 100 VCC = 2.7V –30 50 –10 10 30 TEMPERATURE (°C) 70 90 0 –50 1.2502 –50 –30 50 –10 10 30 TEMPERATURE (°C) 70 90 24602 G07 24602 G08 24602 G09 24602f 5 LTC2460/LTC2462 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Rejection vs Frequency at VCC 0 –20 CONVERSION TIME (ms) REJECTION (dB) –40 –60 –80 21 20 19 18 17 16 15 14 –50 VREF (V) VCC = 5V, 4.1V, 3V (TA = 25°C, unless otherwise noted) Conversion Time vs Temperature 1.24892 1.24891 1.24890 1.24889 1.24888 1.24887 1.24886 1.24885 –25 25 50 0 TEMPERATURE (°C) 75 100 24602 G11 VREF vs VCC TA = 25°C –100 –120 1 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 10M 1.24884 2.0 2.5 3.0 3.5 24602 G10 4.0 4.5 VCC (V) 5.0 5.5 6.0 24602 G12 PIN FUNCTIONS REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V, this voltage sets the fullscale input range of the ADC. For noise and reference stability connect to a 0.1μF capacitor tied to GND. This capacitor value must be less than or equal to the capacitor tied to the reference compensation pin (COMP). REFOUT cannot be overdriven by an external reference. For applications that require an input range greater than 0V to 1.25V, please refer to the LTC2450/ LTC2452. COMP (Pin 2): Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1μF capacitor to GND. CS (Pin 3): Chip Select (Active LOW) Digital Input. A LOW on this pin enables the SDO output. A HIGH on this pin places the SDO output pin in a high impedance state and any inputs on SDI and SCK will be ignored. SDI (Pin 4): Serial Data Input Pin. This pin is used to program the sleep mode and 30Hz/60Hz output rate (LTC2460). SCK (Pin 5): Serial Clock Input. SCK synchronizes the serial data input/output. Once the conversion is complete, a new data bit is produced at the SDO pin following each SCK falling edge. Data is shifted into the SDI pin on each rising edge of SCK. SDO (Pin 6): Three-State Serial Data Output. SDO is used for serial data output during the DATA INPUT/OUTPUT state and can be used to monitor the conversion status. GND (Pins 7, 11): Ground. Connect directly to the ground plane through a low impedance connection. REF– (Pin 8): Negative Reference Input to the ADC. The voltage on this pin sets the zero input to the ADC. This pin should tie directly to ground or the ground sense of the input sensor. IN+ (LTC2462), IN (LTC2460) (Pin 9): Positive input voltage for the LTC2462 differential device. ADC input for the LTC2460 single-ended device. IN– (LTC2462), GND (LTC2460) (Pin 10): Negative input voltage for the LTC2462 differential device. GND for the LTC2460 single-ended device. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to the device as possible. Exposed Pad (Pin 13 – DFN Package): Ground. Connect directly to the ground plane through a low impedance connection. 24602f 6 LTC2460/LTC2462 BLOCK DIAGRAM 1 REFOUT 2 COMP 12 VCC CS SPI INTERFACE SCK SDO 3 5 6 4 9 IN+ (IN) A/D CONVERTER INTERNAL REFERENCE – 10 IN– (GND) A/D CONVERTER DECIMATING SINC FILTER SDI INTERNAL OSCILLATOR REF– 7,11,13 (DD PACKAGE) GND 24602 BD 8 ( ) PARENTHESIS INDICATE LTC2460 Figure 1. Functional Block Diagram APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2460/LTC2462 are low power, delta sigma, analog to digital converters with a simple SPI interface (see Figure 1). The LTC2462 has a fully differential input while the LTC2460 is single-ended. Both are pin and software compatible. Their operation is composed of three distinct states: CONVERT, SLEEP/NAP and DATA INPUT/OUTPUT. , The operation begins with the CONVERT state (see Figure 2). Once the conversion is finished, the converter automatically powers down (NAP) or under user control, both the converter and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT state. Once all 16-bits are read or an abort is initiated the device begins a new conversion. The CONVERT state duration is determined by the LTC2460/ LTC2462 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (VCC < 2.1V) which generates an internal power-on reset signal. After the completion of a conversion, the LTC2460/LTC2462 enters the SLEEP/NAP state and remains there until the chip select is LOW (CS = LOW). Following this condition, the ADC transitions into the DATA INPUT/OUTPUT state. POWER-ON RESET CONVERT SLEEP/NAP NO CS = LOW? YES DATA INPUT/OUTPUT NO 16TH FALLING EDGE OF SCK OR CS = HIGH? YES 24602 F02 Figure 2. LTC2460/LTC2462 State Transition Diagram While in the SLEEP/NAP state, when chip select input is HIGH (CS = HIGH), the LTC2460/LTC2462’s converters are powered down. This reduces the supply current by approximately 50%. While in the Nap state the reference remains powered up. In order to power down the reference in addition to the converter, the user can select the SLEEP 24602f 7 LTC2460/LTC2462 APPLICATIONS INFORMATION mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete, the SLEEP state is entered and power is reduced to less than 2μA. The reference is powered up once CS is brought low. The reference startup time is 12ms (if the reference and compensation capacitor values are both 0.1μF). Upon entering the DATA INPUT/OUTPUT state, SDO outputs the sign (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin. During the DATA INPUT/OUTPUT state, the LTC2460/ LTC2462 can be programmed to SLEEP or NAP (default) following the next conversion cycle. Data is shifted into the device through the SDI pin on the rising edge of SCK. The input word is 4 bits. If the first bit EN1 = 1 and the second bit EN2 = 0 the device is enabled for programming. The following two bits (SPD and SLP) will be written into the device. SPD (only used for the LTC2460) to select the 60Hz output rate, no offset calibration mode (SPD = 0, default). Set SPD = 1 for 30Hz mode with offset calibration. SPD is ignored for the LTC2462. The next bit (SLP) enables the sleep or nap mode. If SLP = 0 (default) the reference remains powered up at the end of the next conversion 20 16 12 8 OUTPUT CODE 4 0 –4 –8 –12 –16 –20 –0.001 –0.005 0.005 0 VIN+/VREF+ 0.001 0.0015 24602 F03 cycle. If SLP = 1, the reference powers down following the next conversion cycle. The remaining 12 SDI input bits are ignored (don’t care). SDI may also be tied directly to GND or VDD in order to simplify the user interface. In the case of the LTC2460, the 60Hz output rate is selected if SDI is tied low and the 30Hz output rate is selected if SDI is tied to VDD. The LTC2462 output rate is always 60Hz independent of SDI or SPD. The reference sleep mode is disabled for both the LTC2460 and LTC2462 if SDI is tied to GND or VDD. The DATA INPUT/OUTPUT state concludes in one of two different ways. First, the DATA INPUT/OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA INPUT/OUTPUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the LTC2460/LTC2462 will enter the CONVERT state and initiate a new conversion cycle. Power-Up Sequence When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result. When VCC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2460/LTC2462 start a conversion cycle and follow the succession of states shown in Figure 2. The reference startup time following a POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conversion following powerup will be invalid since the reference voltage has not completely settled. The first conversion following power up can be discarded using the data abort command or simply read and ignored. The following conversions are accurate to the device specifications. Ease of Use The LTC2460/LTC2462 data output has no latency, filter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, 24602f SIGNALS BELOW GND Figure 3. Output Code vs VIN+ with VIN– = 0 (LTC2462) 8 LTC2460/LTC2462 APPLICATIONS INFORMATION multiplexing multiple analog input voltages requires no special actions. The LTC2460/LTC2462 perform offset calibrations every conversion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature. The LTC2460/LTC2462 include a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks to interface directly to the LTC2460/LTC2462. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1μF results in