LTC2480IDD

LTC2480 16-Bit ∆Σ ADC with Easy Drive Input Current Cancellation FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy Programmable Gain from 1 to 256 Integrated Temperature Sensor GND to VCC Input/Reference Common Mode Range Programmable 50Hz, 60Hz or Simultaneous 50Hz/60Hz Rejection Mode 2ppm (0.25LSB) INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error Selectable 2x Speed Mode (15Hz Using Internal Oscillator) No Latency: Digital Filter Settles in a Single Cycle Single Supply 2.7V to 5.5V Operation Internal Oscillator Available in a Tiny (3mm × 3mm) 10-Lead DFN Package The LTC®2480 combines a 16-bit plus sign No Latency ∆ΣTM analog-to-digital converter with patented Easy DriveTM technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals, with rail-to-rail input range to be directly digitized while maintaining exceptional DC accuracy. The LTC2480 includes on-chip programmable gain, a temperature sensor and an oscillator. The LTC2480 can be configured to provide a programmable gain from 1 to 256 in 8 steps, measure an external signal or internal temperature sensor and reject line frequencies. 50Hz, 60Hz or simultaneous 50Hz/60Hz line frequency rejection can be selected as well as a 2x speed-up mode. The LTC2480 allows a wide common mode input range (0V to VCC) independent of the reference voltage. The reference can be as low as 100mV or can be tied directly to VCC. The LTC2480 includes an on-chip trimmed oscillator eliminating the need for external crystals or oscillators. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending. APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Strain Gauge Transducers Instrumentation Industrial Process Control DVMs and Meters TYPICAL APPLICATIO VCC +FS Error vs RSOURCE at IN+ and IN– VCC = 5V 60 VREF = 5V VIN+ = 3.75V VIN– = 1.25V 40 FO = GND 20 TA = 25°C CIN = 1µF 0 –20 –40 –60 –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2480 TA04 80 10k SENSE 10k IDIFF = 0 1µF VIN+ VREF LTC2480 VCC SDI SDO SCK 4-WIRE SPI INTERFACE VIN – GND FO CS 2480 TA01 +FS ERROR (ppm) 1µF U 2480f U U 1 LTC2480 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW SDI VCC VREF IN + Supply Voltage (VCC) to GND ...................... – 0.3V to 6V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2480C ................................................... 0°C to 70°C LTC2480I ................................................ – 40°C to 85°C Storage Temperature Range ................ – 65°C to 125°C 1 2 3 4 5 11 10 FO 9 SCK 8 GND 7 SDO 6 CS ORDER PART NUMBER LTC2480CDD LTC2480IDD DD PART MARKING* LBJY IN– DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS ( OR AL SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC , IN+ = 0.75VREF , IN– = 0.25VREF The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Notes 3, 4) MIN ● ● ● ● TYP 2 1 0.5 10 MAX 10 2.5 25 UNITS Bits ppm of VREF ppm of VREF µV nV/°C ppm of VREF ppm of VREF/°C 16 0.1 ● 25 0.1 15 ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF µVRMS mV mV/°C 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13) TA = 27°C ● Output Noise Internal PTAT Signal Internal PTAT Temperature Coefficient Programmable Gain 0.6 420 1.4 1 256 2 U 2480f W U W U U WW W LTC2480 ELECTRICAL CHARACTERISTICS (2x SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Output Noise Programmable Gain CONDITIONS 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Notes 3, 4) MIN ● ● ● ● TYP 2 1 0.5 100 MAX 10 2 25 UNITS Bits ppm of VREF mV nV/°C ppm of VREF ppm of VREF/°C 16 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC , IN+ = 0.75VREF , IN– = 0.25VREF 0.1 ● 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13) (Note 15) 25 0.1 0.84 ppm of VREF ppm of VREF/°C µVRMS ● 1 128 CO VERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz ± 2% Input Common Mode Rejection 60Hz ± 2% Input Normal Mode Rejection 50Hz ± 2% Input Normal Mode Rejection 60Hz ± 2% Input Normal Mode Rejection 50Hz/60Hz ± 2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ± 2% Power Supply Rejection, 60Hz ± 2% CONDITIONS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN IN– = IN+ ≤ VCC (Note 5) IN– = IN+ ≤ VCC (Note 5) ● ● ● ● ● ● ● A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage – IN–) ● ● ● ● SYMBOL IN+ IN– FS LSB VIN VREF Full Scale of the Differential Input (IN+ Least Significant Bit of the Output Code Input Differential Voltage Range (IN+ – IN–) Reference Voltage Range U U U U TYP MAX UNITS dB dB dB 2.5V ≤ VREF ≤ VCC, GND ≤ 2.5V ≤ VREF ≤ VCC, GND ≤ 140 140 140 110 110 87 120 140 120 120 120 120 120 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) VREF = 2.5V, IN– = IN+ = GND VREF = 2.5V, IN– = IN+ = GND (Notes 7, 9) VREF = 2.5V, IN– = IN+ = GND (Notes 8, 9) dB dB dB dB dB dB dB U CONDITIONS MIN GND – 0.3V GND – 0.3V 0.5VREF/GAIN FS/216 –FS 0.1 TYP MAX VCC + 0.3V VCC + 0.3V UNITS V V V +FS VCC V V 2480f 3 LTC2480 A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) PARAMETER IN+ IN– Sampling Capacitance Sampling Capacitance Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, VREF = VCC ● ● ● SYMBOL CS CS (IN+) (IN–) CS (VREF) IDC_LEAK (IN+) IDC_LEAK (IN–) IDC_LEAK (VREF) VREF Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current VREF DC Leakage Current –10 –10 –100 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO, SDI Low Level Input Voltage CS, FO, SDI High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO, SDI Digital Input Current SCK Digital Input Capacitance CS, FO, SDI Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO IO = –800µA IO = 1.6mA IO = –800µA IO = 1.6mA CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN ● ● ● ● ● ● 2.7V ≤ VCC ≤ 5.5V (Note 10) 2.7V ≤ VCC ≤ 5.5V (Note 10) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Note 10) POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● Conversion Mode (Note 12) Sleep Mode (Note 12) 4 U UW U U U U U CONDITIONS MIN TYP 11 11 11 1 1 1 MAX UNITS pF pF pF 10 10 100 nA nA nA TYP MAX UNITS V VCC – 0.5 0.5 VCC – 0.5 0.5 –10 –10 10 10 10 10 V V V µA µA pF pF V ● ● ● ● ● VCC – 0.5 0.4 VCC – 0.5 0.4 –10 10 V V V µA MIN 2.7 ● ● TYP 160 1 MAX 5.5 250 2 UNITS V µA µA 2480f LTC2480 TI I G CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time for 1x Speed Mode The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS (Note 15) ● ● ● tCONV_2 fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 t7 t8 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = 0.5VREF/GAIN VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2 Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator). UW MIN 10 0.125 0.125 157.2 131.0 144.1 78.7 65.6 72.2 TYP MAX 4000 100 100 UNITS kHz µs µs ms ms ms ms ms ms ms ms kHz kHz 50Hz Mode 60Hz Mode Simultaneous 50Hz/60Hz Mode External Oscillator 50Hz Mode 60Hz Mode Simultaneous 50Hz/60Hz Mode External Oscillator Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 10) (Note 10) (Note 10) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 10) ● ● ● ● ● ● ● ● 160.3 163.5 133.6 136.3 146.9 149.9 41036/fEOSC (in kHz) 81.9 68.2 75.1 20556/fEOSC (in kHz) 38.4 fEOSC/8 80.3 66.9 73.6 Conversion Time for 2x Speed Mode Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time CS↓ to SDO Low CS↑ to SDO High Z CS↓ to SCK↓ CS↓ to SCK↑ SCK↓ to SDO Valid SDO Hold After SCK↓ SCK Set-Up Before CS↓ SCK Hold After CS↓ SDI Setup Before SCK↑ SDI Hold After SCK↑ ● ● ● ● ● ● ● ● ● 45 125 125 0.61 55 4000 % kHz ns ns 0.625 0.64 192/fEOSC (in kHz) 24/fESCK (in kHz) 200 200 200 200 ms ms ms ns ns ns ns ns ns ns 0 0 0 50 15 50 Internal SCK Mode External SCK Mode (Note 5) ● ● ● ● ● ● 50 100 100 ns ns ns (Note 5) (Note 5) ● ● Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as digital input and the driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital output and the output clock signal during the data output is fISCK. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: Refer to Applications Information section for performance vs data rate graphs. 2480f 5 LTC2480 TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND –45°C INL (ppm OF VREF) INL (ppm OF VREF) 1 0 25°C 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C 4 0 –4 –8 –12 –1.25 –45°C TUE (ppm OF VREF) 25°C 85°C Noise Histogram (6.8sps) 14 12 14 12 NUMBER OF READINGS (%) NUMBER OF READINGS (%) ADC READING (µV) 10,000 CONSECUTIVE READINGS RMS = 0.60µV VCC = 5V AVERAGE = –0.69µV VREF = 5V 10 VIN = 0V GAIN = 256 8 TA = 25°C 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (µV) 1.2 1.8 6 UW 2 2480 G04 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) 3 2 1 0 –1 –2 –3 –1.25 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 90°C 3 2 1 0 –1 –2 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 90°C 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2480 G05 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2480 G06 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) 12 8 VCC = 5V VREF = 5V VIN(CM) = 1.25V FO = GND 12 85°C 25°C 8 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 25°C 85°C –45°C 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2480 G02 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2480 G03 2480 G01 Noise Histogram (7.5sps) 10,000 CONSECUTIVE READINGS RMS = 0.59µV VCC = 2.7V AVERAGE = –0.19µV VREF = 2.5V 10 VIN = 0V GAIN = 256 8 TA = 25°C 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (µV) 1.2 1.8 Long-Term ADC Readings 5 VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V 4 GAIN = 256, TA = 25°C, RMS NOISE = 0.60µV 3 2 1 0 –1 –2 –3 –4 –5 0 10 30 40 20 TIME (HOURS) 50 60 2480 G09 2480 G07 2480 G08 2480f LTC2480 TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Input Differential Voltage 1.0 0.9 RMS NOISE (ppm OF VREF) 0.7 0.6 0.5 0.4 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) RMS NOISE (µV) RMS NOISE (µV) 0.8 VCC = 5V VREF = 5V GAIN = 256 VIN(CM) = 2.5V TA = 25°C RMS Noise vs VCC 1.0 0.9 1.0 OFFSET ERROR (ppm OF VREF) RMS NOISE (µV) RMS NOISE (µV) 0.8 0.7 0.6 0.5 VREF = 2.5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 0.4 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 Offset Error vs Temperature 0.3 0.2 0.1 0 0.3 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.2 0.1 0 –0.1 –0.2 OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) UW 2480 G10 RMS Noise vs VIN(CM) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 –1 0 1 2 3 4 5 6 VIN(CM) (V) 2480 G11 RMS Noise vs Temperature (TA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 –45 –30 –15 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND GAIN = 256 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 2.5 0 15 30 45 60 TEMPERATURE (°C) 75 90 2480 G12 RMS Noise vs VREF 0.9 0.8 0.7 0.6 0.5 0.4 VCC = 5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C Offset Error vs VIN(CM) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 VCC = 5V VREF = 5V VIN = 0V GAIN = 256 TA = 25°C 5.1 5.5 0 1 2 3 VREF (V) 4 5 2480 G14 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2480 G13 2480 G15 Offset Error vs VCC REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF– = GND VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C –0.1 –0.2 –0.3 75 90 –0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 0 1 2 3 VREF (V) 4 5 2480 G18 2480 G16 2480 G17 2480f 7 LTC2480 TYPICAL PERFOR A CE CHARACTERISTICS Temperature Sensor vs Temperature 0.40 VCC = 5V VREF = 1.4V FO = GND 5 4 TEMPERATURE ERROR (°C) 3 VREF = 1.4V 0.35 FREQUENCY (kHz) VPTAT/VREF (V) 0.30 0.25 0.20 –60 –30 0 30 60 TEMPERATURE (°C) On-Chip Oscillator Frequency vs VCC 310 VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND REJECTION (dB) 308 FREQUENCY (kHz) 306 –60 –80 –100 REJECTION (dB) 304 302 300 2.5 3.0 3.5 4.0 VCC (V) 4.5 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 FO = GND TA = 25°C –60 –80 –100 –120 –140 30600 0 CONVERSION CURRENT (µA) VCC = 5V SLEEP MODE CURRENT (µA) REJECTION (dB) 30650 30750 FREQUENCY AT VCC (Hz) 30700 8 UW 90 120 2480 G24 Temperature Sensor Error vs Temperature 310 On-Chip Oscillator Frequency vs Temperature VCC = 5V FO = GND 308 2 1 0 –1 –2 –3 –4 –5 –60 –30 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (°C) 75 90 302 30 60 0 TEMPERATURE (°C) 90 120 2480 G25 300 –45 –30 –15 2480 G26 PSRR vs Frequency at VCC 0 –20 –40 VCC = 4.1V DC VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 0 –20 –40 –60 –80 –100 –120 –140 PSRR vs Frequency at VCC VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C –120 –140 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 5.0 5.5 2480 G27 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2480 G29 2480 G28 Conversion Current vs Temperature 200 2.0 Sleep Mode Current vs Temperature FO = GND 1.8 CS = VCC SCK = NC 1.6 SDO = NC 1.4 SDI = GND 1.2 1.0 0.8 0.6 0.4 0.2 VCC = 2.7V VCC = 5V 180 FO = GND CS = GND SCK = NC SDO = NC SDI = GND 160 VCC = 2.7V 140 120 30800 2480 G30 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2480 G31 2480 G32 2480f LTC2480 TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Output Data Rate 500 450 SUPPLY CURRENT (µA) 400 350 300 250 200 150 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 G33 INL (ppm OF VREF) 1 0 –1 –45°C –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 25°C, 90°C INL (ppm OF VREF) VREF = VCC IN+ = GND IN– = GND SCK = NC SDO = NC SDI = GND CS GND FO = EXT OSC TA = 25°C VCC = 5V VCC = 3V Integral Nonlinearity (2x Speed Mode; VCC = 2.7V, VREF = 2.5V) 3 2 INL (ppm OF VREF) 90°C RMS NOISE (µV) 1 0 –1 –2 –3 –1.25 NUMBER OF READINGS (%) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) Offset Error vs VIN(CM) (2x Speed Mode) 200 198 196 VCC = 5V VREF = 5V VIN = 0V FO = GND TA = 25°C OFFSET ERROR (µV) OFFSET ERROR (µV) 194 192 190 188 186 184 182 180 –1 0 1 UW 2480 G36 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 5V) 3 2 VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 3 2 1 0 –1 –2 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND 90°C –45°C, 25°C 2 2.5 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2480 G35 2480 G34 Noise Histogram (2x Speed Mode) 16 RMS = 0.86µV 10,000 CONSECUTIVE AVERAGE = 0.184mV 14 READINGS VCC = 5V 12 VREF = 5V VIN = 0V GAIN = 256 10 TA = 25°C 8 6 4 2 1.0 RMS Noise vs VREF (2x Speed Mode) 0.8 0.6 0.4 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 0 1 3 2 VREF (V) 4 5 2480 G38 0.2 1.25 0 179 0 181.4 186.2 OUTPUT READING (µV) 183.8 188.6 2480 G37 Offset Error vs Temperature (2x Speed Mode) 240 230 220 210 200 190 180 170 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 3 2 VIN(CM) (V) 4 5 6 2480 G39 160 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2480 G40 2480f 9 LTC2480 TYPICAL PERFOR A CE CHARACTERISTICS Offset Error vs VCC (2x Speed Mode) 250 VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 200 OFFSET ERROR (µV) OFFSET ERROR (µV) 150 210 200 190 180 170 REJECTION (dB) 100 50 0 2 2.5 3 4 3.5 VCC (V) 4.5 5 5.5 2480 G41 PSRR vs Frequency at VCC (2x Speed Mode) 0 –20 –40 –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2480 G44 RREJECTION (dB) REJECTION (dB) VCC = 4.1V DC ±1.4V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C PI FU CTIO S SDI (Pin 1): Serial Data Input. This pin is used to select the GAIN, line frequency rejection, input, temperature sensor and 2x speed mode. Data is shifted into the SDI pin on the rising edge of serial clock (SCK). VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. VREF (Pin 3): Positive Reference Input. The voltage on this pin can have any value between 0.1V and VCC. The negative reference input is GND (Pin 8). IN+ (Pin 4), IN– (Pin 5): Differential Analog Inputs. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from – 0.5 • VREF /GAIN to 0.5 • VREF/GAIN. Outside this input range the converter produces unique overrange and underrange output codes. CS (Pin 6): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long 2480f 10 UW Offset Error vs VREF (2x Speed Mode) 240 230 220 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C PSRR vs Frequency at VCC (2x Speed Mode) 0 –20 –40 –60 –80 –100 –120 –140 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M VCC = 4.1V DC REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C 160 0 1 2 3 VREF (V) 4 5 2480 G42 2480 G43 PSRR vs Frequency at VCC (2x Speed Mode) –20 VCC = 4.1V DC ±0.7V REF+ = 2.5V REF– = GND IN+ = GND –40 IN– = GND FO = GND –60 TA = 25°C –80 –100 –120 –140 30600 0 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2480 G45 U U U LTC2480 PI FU CTIO S as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 7): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. GND (Pin 8): Ground. Shared pin for analog ground, digital ground and reference ground. Should be connected directly to a ground plane through a minimum impedance. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Input/Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 10): Frequency Control Pin. Digital input that controls the conversion clock. When FO is connected to GND the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate or the digital filter rejection null. Exposed Pad (Pin 11): This pin is ground and should be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating. FU CTIO AL BLOCK DIAGRA 3 4 5 VREF IN+ IN – MUX TEMP SENSOR TEST CIRCUITS SDO 1.69k CLOAD = 20pF SDO Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 2480 TA02 W U U U U U 2 VCC SDI SCK SERIAL INTERFACE SD0 CS IN+ REF+ 1 9 7 6 3RD ORDER ∆Σ ADC (1-256) IN – REF – GAIN AUTOCALIBRATION AND CONTROL FO 10 GND 8 INTERNAL OSCILLATOR 2480 FD VCC 1.69k CLOAD = 20pF Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2480 TA03 2480f 11 LTC2480 TI I G DIAGRA S Timing Diagram Using Internal SCK CS t1 SDO t3 SCK t7 SDI SLEEP DATA IN/OUT t8 tKQMIN tKQMAX t2 CS t1 SDO t5 SCK t7 SDI SLEEP DATA IN/OUT t8 t6 t4 tKQMIN tKQMAX t2 APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2480 is a low power, delta-sigma analog-todigital converter with an easy to use 4-wire serial interface and automatic differential input current cancellation. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1). The 4-wire interface consists of serial data output (SDO), serial clock (SCK), chip select (CS) and serial data input (SDI). Initially, the LTC2480 performs a conversion. Once the conversion is complete, the device enters the sleep state. 12 U W W UU UW 2480 TD1 CONVERSION Timing Diagram Using External SCK 2480 TD2 CONVERSION CONVERT SLEEP FALSE CS = LOW AND SCK TRUE DATA OUTPUT CONFIGURATION INPUT 2480 F01 Figure 1. LTC2480 State Transition Diagram 2480f LTC2480 APPLICATIO S I FOR ATIO While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data input and output state and start a new conversion. The conversion result is shifted out of the device through the serial data output pin (SDO) on the falling edge of the serial clock (SCK) (see Figure 2). The LTC2480 includes a serial data input pin (SDI) in which data is latched by the device on the rising edge of SCK (Figure 2). The bit stream applied to this pin can be used to select various features of the LTC2480, including an on-chip temperature sensor, programmable GAIN, line frequency rejection and output data rate. Alternatively, this pin may be tied to ground and the part will perform conversions in a default state. In the default state (SDI grounded) the device simply performs conversions on the user applied input with a GAIN of 1 and simultaneous rejection of 50Hz and 60Hz line frequencies. Through timing control of the CS and SCK pins, the LTC2480 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Easy Drive Input Current Cancellation The LTC2480 combines a high precision delta-sigma ADC with an automatic differential input current cancellation front end. A proprietary front-end passive sampling U network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2480 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Input Current Cancellation section). This unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to VCC. Furthermore, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity) is maintained even with external RC networks. Accessing the Special Features of the LTC2480 The LTC2480 combines a high resolution, low noise ∆Σ analog-to-digital converter with an on-chip selectable temperature sensor, programmable gain, programmable digital filter and output rate control. These special features are selected through a single 8-bit serial input word during the data input/output cycle (see Figure 2). The LTC2480 powers up in a default mode commonly used for most measurements. The device will remain in this mode as long as the serial data input (SDI) is low. In this default mode, the measured input is external, the GAIN is 1, the digital filter simultaneously rejects 50Hz and 60Hz line frequency noise, and the speed mode is 1x (offset automatically, continuously calibrated). A simple serial interface grants access to any or all special functions contained within the LTC2480. In order to change the mode of operation, an enable bit (EN) followed by up to 7 bits of data are shifted into the device (see Table 1). The first 3 bits (GS2, GS1, GS0) control the GAIN of the converter from 1 to 256. The 4th bit (IM) is used to select the internal temperature sensor as the conversion input, while the 5th and 6th bits (FA, FB) combine to determine the line frequency rejection mode. The 7th bit (SPD) is used to double the output rate by disabling the offset auto calibration. 2480f W UU 13 LTC2480 APPLICATIO S I FOR ATIO CS BIT 23 SDO Hi-Z EOC BIT 22 DMY BIT 21 SIG BIT 20 MSB BIT 19 B16 CONVERSION RESULT SCK SDI SLEEP EN GS2 GS1 GS0 IM Figure 2. Input/Output Data Timing Table 1. Selecting Special Modes Rejection Mode IM FA FB SPD X XXX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Any 0 0 Rejection 1 0 Mode 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 Any 1 0 Speed 0 1 1 0 1 0 0 X 1 0 1 X 1 1 0 X 1 1 1 X 2480 TBL1 Gain EN GS2 GS1 GS0 0XXX 00 0 1 01 0 1 10 0 1 11 0 1 00 1 1 01 1 1 10 1 1 11 1 1 00 0 1 01 0 1 10 0 1 11 0 1 00 1 1 01 1 1 10 1 1 11 1 1 1 1 Any Gain 1 1 1XXX 1XXX 1XXX 1XXX 14 U BIT 18 BIT 4 LSB BIT 3 GS2 BIT 2 GS1 BIT 1 GS0 BIT 0 IM PREVIOUS CONFIGURATION BITS FA FB SPD DON’T CARE CONVERSION 2480 F02 W UU DATA INPUT/OUTPUT Comments Keep Previous Mode External Input, Gain = 1, Autocalibration External Input, Gain = 4, Autocalibration External Input, Gain = 8, Autocalibration External Input, Gain = 16, Autocalibration External Input, Gain = 32, Autocalibration External Input, Gain = 64, Autocalibration External Input, Gain = 128, Autocalibration External Input, Gain = 256, Autocalibration External Input, Gain = 1, 2x Speed External Input, Gain = 2, 2x Speed External Input, Gain = 4, 2x Speed External Input, Gain = 8, 2x Speed External Input, Gain = 16, 2x Speed External Input, Gain = 32, 2x Speed External Input, Gain = 64, 2x Speed External Input, Gain = 128, 2x Speed External Input, Simultaneous 50Hz/60Hz Rejection External Input, 50Hz Rejection External Input, 60Hz Rejection Reserved, Do Not Use Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration Reserved, Do Not Use 2480f LTC2480 APPLICATIO S I FOR ATIO GAIN Input Span LSB Noise Free Resolution* Gain Error Offset Error 1 ±2.5 38.1 65536 5 0.5 4 ±0.625 9.54 65536 5 0.5 Table 2a. The LTC2480 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V) 8 ±0.312 4.77 65536 5 0.5 16 ±0.156 2.38 65536 5 0.5 32 ±78m 1.19 65536 5 0.5 64 ±39m 0.596 65536 5 0.5 128 ±19.5m 0.298 32768 5 0.5 256 ±9.76m 0.149 16384 8 0.5 UNIT V µV Counts ppm of FS µV Table 2b. The LTC2480 Performance vs GAIN in 2x Speed Mode (VCC = 5V, VREF = 5V) GAIN Input Span LSB Noise Free Resolution* Gain Error Offset Error 1 ±2.5 38.1 65536 5 200 2 ±1.25 19.1 65536 5 200 4 ±0.625 9.54 65536 5 200 8 ±0.312 4.77 65536 5 200 16 ±0.156 2.38 65536 5 200 32 ±78m 1.19 65536 5 200 64 ±39m 0.596 45875 5 200 128 ±19.5m 0.298 22937 5 200 UNIT V µV Counts ppm of FS µV *The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger. GAIN (GS2, GS1, GS0) The input referred gain of the LTC2480 is adjustable from 1 to 256. With a gain of 1, the differential input range is ±VREF/2 and the common mode input range is rail-to-rail. As the GAIN is increased, the differential input range is reduced to ±VREF/2 • GAIN but the common mode input range remains rail-to-rail. As the differential gain is increased, low level voltages are digitized with greater resolution. At a gain of 256, the LTC2480 digitizes an input signal range of ±9.76mV with over 16,000 counts. Temperature Sensor (IM) The LTC2480 includes an on-chip temperature sensor. The temperature sensor is selected by setting IM = 1 in the serial input data stream. Conversions are performed directly on the temperature sensor by the converter. While operating in this mode, the device behaves as a temperature to bits converter. The digital reading is proportional to the absolute temperature of the device. This feature allows the converter to linearize temperature sensors or continuously remove temperature effects from external sensors. Several applications leveraging this feature are presented in more detail in the applications section. While operating in this mode, the gain is set to 1 and the speed is set to normal independent of the control bits (GS2, GS1, GS0 and SPD). U Rejection Mode (FA, FB) The LTC2480 includes a high accuracy on-chip oscillator with no required external components. Coupled with a 4th order digital lowpass filter, the LTC2480 rejects line frequency noise. In the default mode, the LTC2480 simultaneously rejects 50Hz and 60Hz by at least 87dB. The LTC2480 can also be configured to selectively reject 50Hz or 60Hz to better than 110dB. Speed Mode (SPD) The LTC2480 continuously performs offset calibrations. Every conversion cycle, two conversions are automatically performed (default) and the results combined. This result is free from offset and drift. In applications where the offset is not critical, the autocalibration feature can be disabled with the benefit of twice the output rate. Linearity, full-scale accuracy and full-scale drift are identical for both 2x and 1x speed modes. In both the 1x and 2x speed there is no latency. This enables input steps or multiplexer channel changes to settle in a single conversion cycle easing system overhead and increasing the effective conversion rate. 2480f W UU 15 LTC2480 APPLICATIO S I FOR ATIO Output Data Format The LTC2480 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 17 bits are the conversion result, MSB first. The remaining 4 bits indicate the configuration state associated with the current conversion result. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS). In applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2480’s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and output “1” for the extra clock cycles. Furthermore, CS may be pulled high prior to outputting all 24 bits, aborting the data out transfer and initiating a new conversion. Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 1nF at Both VIN(CM) – VREF(CM) IN+ and IN–. Can Take Large Source Resistance with Negligible Error UNBALANCED INPUT RESISTANCES CEXT > 1nF at Both IN+ and IN–. Can Take Large Source Resistance. Unbalanced Resistance Results in an Offset Which Can be Calibrated Minimize IN+ and IN– Capacitors and Avoid Large Source Impedance (< 5k Recommended) Varying CEXT > 1nF at Both IN+ VIN(CM) – VREF(CM) and IN–. Can Take Large Source Resistance with Negligible Error W UU The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1µV typical and 10µV maximum offset voltage. 2480f LTC2480 APPLICATIO S I FOR ATIO Reference Current In a similar fashion, the LTC2480 samples the differential reference pins VREF+ and GND transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations. For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same. Using internal oscillator for 60Hz mode, the typical differential reference resistance is 1MΩ which generates a full-scale (VREF/2) gain error of 0.51ppm for each ohm of source resistance driving the VREF pin. For 50Hz/60Hz mode, the related difference resistance is 1.1MΩ and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the VREF pin. For 50Hz mode, the related difference resistance is 1.2MΩ and the resulting full-scale error is 0.42ppm for each ohm of source resistance driving the VREF pin. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.30 • 1012/fEOSC Ω and each ohm of source resistance driving the VREF pin will result in 1.67 • 10–6 • fEOSCppm gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the VREF pin and external capacitance connected to that pin are shown in Figures 15-18. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms U –VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference pin current as expressed in Figure 11. When using internal oscillator and 60Hz mode, every 100Ω of reference source resistance translates into about 0.67ppm additional INL error. When using internal oscillator and 50Hz/60Hz mode, every 100Ω of reference source resistance translates into about 0.61ppm additional INL error. When using internal oscillator and 50Hz mode, every 100Ω of reference source resistance translates into about 0.56ppm additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100Ω of source resistance driving VREF translates into about 2.18 • 10–6 • fEOSCppm additional INL error. Figure 19 shows the typical INL error due to the source resistance driving the VREF pin when large CREF values are used. The user is advised to minimize the source impedance driving the VREF pin. In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (VREFCM – VINCM) and a 5V reference, each Ohm of reference source resistance introduces an extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error, which is 0.074ppm when using internal oscillator and 60Hz mode. When using internal oscillator and 50Hz/60Hz mode, the extra full-scale gain error is 0.067ppm. When using internal oscillator and 50Hz mode, the extra gain error is 0.061ppm. If an external clock is used, the corresponding extra gain error is 0.24 • 10–6 • fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by VREF+ and GND, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent 2480f W UU 29 LTC2480 APPLICATIO S I FOR ATIO 90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 –10 0 10 1k 100 RSOURCE (Ω) 10k 100k 2480 F15 –FS ERROR (ppm) VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF Figure 15. +FS Error vs RSOURCE at VREF (Small CREF) 10 0 –10 –FS ERROR (ppm) –20 –30 –40 –50 VCC = 5V –60 VREF = 5V V + = 1.25V –70 VIN– = 3.75V IN –80 FO = GND TA = 25°C –90 10 0 CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF INL (ppm OF VREF) 1k 100 RSOURCE (Ω) 10k 100k 2480 F16 Figure 16. –FS Error vs RSOURCE at VREF (Small CREF) 500 400 +FS ERROR (ppm) 300 VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C CREF = 1µF, 10µF CREF = 0.1µF 200 CREF = 0.01µF 100 0 0 200 600 400 RSOURCE (Ω) 800 1000 2480 F17 Figure 17. +FS Error vs RSOURCE at VREF (Large CREF) 30 U 0 –100 CREF = 0.01µF –200 CREF = 1µF, 10µF –300 VCC = 5V VREF = 5V VIN+ = 1.25V VIN– = 3.75V FO = GND TA = 25°C 0 200 600 400 RSOURCE (Ω) CREF = 0.1µF –400 –500 800 1000 2480 F18 W UU Figure 18. –FS Error vs RSOURCE at VREF (Large CREF) 10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10µF 2 0 R = 1k R = 500Ω R = 100Ω –2 –4 –6 –8 –10 – 0.5 – 0.3 0.1 – 0.1 VIN/VREF (V) 0.3 0.5 2480 F19 Figure 19. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1µF leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maximum full-scale error. Output Data Rate When using its internal oscillator, the LTC2480 produces up to 7.5 samples per second (sps) with a notch frequency of 60Hz, 6.25sps with a notch frequency of 50Hz and 6.82sps with the 50Hz/60Hz rejection mode. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an 2480f LTC2480 APPLICATIO S I FOR ATIO OFFSET ERROR (ppm OF VREF) external oscillator), the LTC2480 output data rate can be increased as desired. The duration of the conversion phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves as if the internal oscillator is used and the notch is set at 60Hz. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2480’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2480 typical performance can be inferred from Figures 13, 14, 15 and 16 in which the horizontal axis is scaled by 307200/fEOSC. Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 20 to 27. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating +FS ERROR (ppm OF VREF) –FS ERROR (ppm OF VREF) U 50 40 30 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F20 W UU VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK TA = 85°C Figure 20. Offset Error vs Output Data Rate and Temperature 3500 3000 2500 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK TA = 85°C 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F21 TA = 25°C Figure 21. +FS Error vs Output Data Rate and Temperature 0 –500 –1000 TA = 25°C TA = 85°C –2000 –1500 –2500 –3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F22 –3500 Figure 22. –FS Error vs Output Data Rate and Temperature 2480f 31 LTC2480 APPLICATIO S I FOR ATIO 24 TA = 25°C 22 TA = 85°C 20 18 16 14 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F23 RESOLUTION (BITS) RESOLUTION (BITS) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) Figure 23. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature 22 20 RESOLUTION (BITS) 18 TA = 85°C 16 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F24 RESOLUTION (BITS) TA = 25°C Figure 24. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 20 VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F25 OFFSET ERROR (ppm OF VREF) Figure 25. Offset Error vs Output Data Rate and Reference Voltage 32 U 24 VCC = VREF = 5V 22 20 18 16 14 VIN(CM) = VREF(CM) VIN = 0V FO = EXT CLOCK 12 T = 25°C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F26 W UU VCC = 5V, VREF = 2.5V Figure 26. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage 22 20 18 VCC = VREF = 5V 16 VCC = 5V, VREF = 2.5V VIN(CM) = VREF(CM) 14 VIN = 0V REF– = GND 12 FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2480 F27 Figure 27. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2480 input bandwidth. When the internal oscillator is used with the notch set at 60Hz, the 3dB input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If an external conversion clock generator of frequency fEOSC is connected to the FO pin, the 3dB input bandwidth is 11.8 • 10–6 • fEOSC. 2480f LTC2480 APPLICATIO S I FOR ATIO Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2480 input bandwidth is shown in Figure 28. When an external oscillator of frequency fEOSC is used, the shape of the LTC2480 input bandwidth can be derived from Figure 28, 60Hz mode curve in which the horizontal axis is scaled by fEOSC/307200. The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nV√Hz for an infinite bandwidth source and 64nV√Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2480, the ADC input referred system noise calculation can be simplified by Figure 29. The noise of an amplifier driving the LTC2480 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 29, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni • √freqi. The total system noise (referred to the LTC2480 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2480 internal noise, the noise of the IN + driving amplifier and the noise of the IN – driving amplifier. If the FO pin is driven by an external oscillator of frequency fEOSC, Figure 29 can still be used for noise calculation if the INPUT SIGNAL ATTENUATION (dB) INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) U 0 –1 50Hz AND 60Hz MODE –2 –3 –4 –5 –6 50Hz MODE 60Hz MODE 1 3 4 0 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2480 F28 W UU Figure 28. Input Signal Bandwidth Using the Internal Oscillator 100 10 60Hz MODE 50Hz MODE 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2480 F29 Figure 29. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 29 plot accuracy begins to decrease, but at the same time the LTC2480 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2480 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2480 allows external lowpass filtering without degrading the DC performance of the device. 2480f 33 LTC2480 APPLICATIO S I FOR ATIO The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2480’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048 • fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode with a 50Hz notch setting, fS = 12800Hz, with 50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch setting fS = 15360Hz. In the external oscillator mode, fS = fEOSC/20. The performance of the normal mode rejection is shown in Figures 30 and 31. 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2480 F30 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) Figure 30. Input Normal Mode Rejection, Internal Oscillator and 50Hz Notch Mode 0 fN = fEOSC/5120 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN 2480 F32 Figure 32. Input Normal Mode Rejection at DC 34 U In 1x speed mode, the regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 32 (rejection near DC) and Figure 33 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figures 34, 35 and 36. Typical measured values of the normal mode rejection of the LTC2480 operating with an internal oscillator and a 60Hz notch setting are shown in Figure 34 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2480 F31 W UU Figure 31. Input Normal Mode Rejection, Internal Oscillator and 60Hz Notch Mode or External Oscillator 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2480 F33 Figure 33. Input Normal Mode Rejection at fS = 256fN 2480f LTC2480 APPLICATIO S I FOR ATIO 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2480 F34 Figure 34. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2480 F35 Figure 35. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 Figure 36. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz/60Hz Mode) superimposed over the theoretical calculated curve. Similarly, the measured normal mode rejection of the LTC2480 for the 50Hz rejection mode and 50Hz/60Hz rejection mode are shown in Figures 35 and 36. U VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C W UU As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2480. If passive RC components are placed in front of the LTC2480, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2480 allows external RC networks without significant degradation in DC performance. Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2480 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and the LTC2480 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2480 has a full-scale differential input range of 5V peak-to-peak. Figures 37 and 38 show measurement results for the LTC2480 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. In Figure 37, the LTC2480 uses the internal oscillator with the notch set at 60Hz (FO = LOW) and in Figure 38 it uses the internal oscillator with the notch set at 50Hz. It is clear that the LTC2480 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. Using the 2x speed mode of the LTC2480, the device bypasses the digital offset calibration operation to double the output data rate. The superior normal mode rejection is maintained as shown in Figures 30 and 31. However, the magnified details near DC and fS = 256fN are different, see Figures 39 and 40. In 2x speed mode, the bandwidth is 11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz rejection mode and 12.4Hz for the 50Hz/60Hz rejection VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 200 220 2483 F36 2480f 35 LTC2480 APPLICATIO S I FOR ATIO 0 NORMAL MODE REJECTION (dB) NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2480 F37 Figure 37. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch) 0 INPUT NORMAL REJECTION (dB) INPUT NORMAL REJECTION (dB) –20 –40 –60 –80 –100 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (fN) 8fN 2480 F39 Figure 39. Input Normal Mode Rejection 2x Speed Mode 0 NORMAL MODE REJECTION (dB) –20 –40 –60 –80 NORMAL MODE REJECTION (dB) MEASURED DATA VCC = 5V CALCULATED DATA VREF = 5V VINCM = 2.5V VIN(P-P) = 5V FO = GND TA = 25°C –100 –120 0 25 50 75 100 125 150 175 200 225 INPUT FREQUENCY (Hz) 2480 F41 Figure 41. Input Normal Mode Rejection vs Input Frequency, 2x Speed Mode and 50Hz/60Hz Mode mode. Typical measured values of the normal mode rejection of the LTC2480 operating with the internal oscillator and 2x speed mode is shown in Figure 41. 36 U VCC = 5V VREF = 5V VINCM = 2.5V TA = 25°C 0 –20 –40 – 60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2480 F38 W UU Figure 38. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch) 0 –20 –40 –60 –80 –100 –120 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY (fN) 2480 F48 Figure 40. Input Normal Mode Rejection 2x Speed Mode –70 –80 NO AVERAGE –90 –100 –110 –120 –130 –140 60 62 54 56 58 48 50 52 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2480 F42 WITH RUNNING AVERAGE Figure 42. Input Normal Mode Rejection 2x Speed Mode When the LTC2480 is configured in 2x speed mode, by performing a running average, a SINC1 notch is combined with the SINC4 digital filter, yielding the normal mode 2480f LTC2480 APPLICATIO S I FOR ATIO rejection identical as that for the 1x speed mode. The averaging operation still keeps the output rate with the following algorithm: Result 1 = average (sample 0, sample 1) Result 2 = average (sample 1, sample 2) …… Result n = average (sample n – 1, sample n) The main advantage of the running average is that it achieves simultaneous 50Hz/60Hz rejection at twice the effective output rate, as shown in Figure 42. The raw output data provides a better than 70dB rejection over 48Hz to 62.4Hz, which covers both 50Hz ±2% and 60Hz ±2%. With running average on, the rejection is better than 87dB for both 50Hz ±2% and 60Hz ±2%. Complete Thermocouple Measurement System with Cold Junction Compensation The LTC2480 is ideal for direct digitization of thermocouples and other low voltage output sensors. The input has a typical offset error of 500nV (2.5µV max) offset drift of 10nV/°C and a noise level of 600nVRMS. The input span may be optimized for various sensors by setting the gain of the PGA. Using an external 5V reference with a PGA gain of 64 gives a ±78mV input range—perfect for thermocouples. Figure 44 (last page of this data sheet) is a complete type K thermocouple meter. The only signal conditioning is a simple surge protection network. In any thermocouple LT1236 2 IN OUT TRIM GND 4 6 5 R7 8k R8 1k + G1 NC1M4V0 TYPE K THERMOCOUPLE JACK (OMEGA MPJ-K-F) U meter, the cold junction temperature sensor must be at the same temperature as the junction between the thermocouple materials and the copper printed circuit board traces. The tiny LTC2480 can be tucked neatly underneath an Omega MPJ-K-F thermocouple socket ensuring close thermal coupling. The LTC2480’s 1.4mV/°C PTAT circuit measures the cold junction temperature. Once the thermocouple voltage and cold junction temperature are known, there are many ways of calculating the thermocouple temperature including a straight-line approximation, lookup tables or a polynomial curve fit. Calibration is performed by applying an accurate 500mV to the ADC input derived from an LT®1236 reference and measuring the local temperature with an accurate thermometer as shown in Figure 43. In calibration mode, the up and down buttons are used to adjust the local temperature reading until it matches an accurate thermometer. Both the voltage and temperature calibration are easily automated. The complete microcontroller code for this application is available on the LTC2480 product webpage at: http://www.linear.com It can be used as a template for may different instruments and it illustrates how to generate calibration coefficients for the onboard temperature sensor. Extensive comments detail the operation of the program. The read_LTC2480() function controls the operation of the LTC2480 and is listed below for reference. 5V C8 1µF ISOTHERMAL R2 2k 3 4 IN+ REF 2 VCC 6 9 7 1 10 C7 0.1µF IN– 5 CS SCK LTC2480 SDO SDI GND GND FO 8 11 2480 F43 W UU 26.3C 2480f Figure 43. Calibration Setup 37 LTC2480 APPLICATIO S I FOR ATIO /*** read_LTC2480() ************************************************************ This is the function that actually does all the work of talking to the LTC2480. The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus. Data changes state on falling clock edges and is valid on rising edges, as determined by the setup_spi() line in the initialize() function. A good starting point when porting to other processors is to write your own spi_write function. Note that each processor has its own way of configuring the SPI port, and different compilers may or may not have built-in functions for the SPI port. Also, since the state of the LTC2480’s SDO line indicates when a conversion is complete you need to be able to read the state of this line through the processor’s serial data input. Most processors will let you read this pin as if it were a general purpose I/O line, but there may be some that don’t. When in doubt, you can always write a “bit bang” function for troubleshooting purposes. The “fourbytes” structure allows byte access to the 32 bit return value: struct fourbytes { int8 te0; int8 te1; int8 te2; int8 te3; }; // // // // // // Define structure of four consecutive bytes To allow byte access to a 32 bit int or float. The make32() function in this compiler will also work, but a union of 4 bytes and a 32 bit int is probably more portable. Also note that the lower 4 bits are the configuration word from the previous conversion. The 4 LSBs are cleared so that they don’t affect any subsequent mathematical operations. While you can do a right shift by 4, there is no point if you are going to convert to floating point numbers - just adjust your scaling constants appropriately. *******************************************************************************/ signed int32 read_LTC2480(char config) { union // adc_code.bits32 all 32 bits { // adc_code.by.te0 byte 0 signed int32 bits32; // adc_code.by.te1 byte 1 struct fourbytes by; // adc_code.by.te2 byte 2 } adc_code; // adc_code.by.te3 byte 3 output_low(CS); while(input(PIN_C4)) {} // Enable LTC2480 SPI interface // Wait for end of conversion. The longest // you will ever wait is one whole conversion period // Now is the time to switch any multiplexers because the conversion is finished // and you have the whole data output time for things to settle. adc_code.by.te3 adc_code.by.te2 adc_code.by.te1 adc_code.by.te0 = = = = 0; spi_read(config); spi_read(0); spi_read(0); // // // // // // // Set upper byte to zero. Read first byte, send config byte Read 2nd byte, send speed bit Read 3rd byte. ‘0’ argument is necessary to act as SPI master!! (compiler and processor specific.) Disable LTC2480 SPI interface output_high(CS); // Clear configuration bits and subtract offset. This results in // a 2’s complement 32 bit integer with the LTC2480’s MSB in the 2^20 position adc_code.by.te0 = adc_code.by.te0 & 0xF0; adc_code.bits32 = adc_code.bits32 - 0x00200000; return adc_code.bits32; } // End of read_LTC2480() 2480f 38 U W UU LTC2480 PACKAGE DESCRIPTIO 3.50 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 ± 0.10 10 PIN 1 TOP MARK (SEE NOTE 5) 5 0.200 REF 0.75 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.675 ± 0.05 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD10) DFN 0403 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD 2480f 39 LTC2480 TYPICAL APPLICATIO ISOTHERMAL R2 2k TYPE K THERMOCOUPLE JACK (OMEGA MPJ-K-F) 5V 1 R6 5k 2 3 RELATED PARTS PART NUMBER LTC1050 LT1236A-5 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 DESCRIPTION Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference 24-Bit, No Latency ∆Σ ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ∆Σ ADCs in MSOP 4-/8-Channel, 24-Bit, No Latency ∆Σ ADCs with Differential Inputs 24-Bit, No Latency ∆Σ ADC with Differential Inputs COMMENTS No External Components 5µV Offset, 1.6µVP-P Noise 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.8µVRMS Noise, 2ppm INL 1.45µVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 2.8µV Noise, SSOP-16/MSOP Package 3ppm INL, Simultaneous 50Hz/60Hz Rejection 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2480/LTC2482 2480f LT/TP 0405 500 • PRINTED IN THE USA LTC2411/LTC2411-1 24-Bit, No Latency ∆Σ ADCs with Differential Inputs in MSOP LTC2413 LTC2415/ LTC2415-1 LTC2414/LTC2418 LTC2420 LTC2430/LTC2431 LTC2440 LTC2482 LTC2484 24-Bit, No Latency ∆Σ ADC with Differential Inputs 24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate 8-/16-Channel 24-Bit, No Latency ∆Σ ADCs 20-Bit, No Latency ∆Σ ADC in SO-8 20-Bit, No Latency ∆Σ ADCs with Differential Inputs High Speed, Low Noise 24-Bit ∆Σ ADC 16-Bit ∆Σ ADC with Easy Drive Inputs 24-Bit ∆Σ ADC with Easy Drive Inputs LTC2435/LTC2435-1 20-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate 40 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U 5V PIC16F73 C8 1µ F C7 0.1µF 18 17 16 15 14 13 12 11 28 27 26 25 24 23 22 21 7 6 5 4 3 2 5V CALIBRATE 2 1 R3 10k R4 10k R5 10k RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA5 RA4 RA3 RA2 RA1 RA0 VDD 20 C6 0.1µF Y1 6MHz 5V 4 IN+ IN– 5 CS SCK LTC2480 SDO SDI GND GND FO 8 5V D7 VCC D6 2 × 16 CHARACTER D5 LCD DISPLAY D4 (OPTREX DMC162488 EN OR SIMILAR) RW CONTRAST GND D0 D1 D2 D3 RS 11 3 REF 2 VCC 6 9 7 1 10 OSC1 OSC2 9 10 R1 1 10k D1 BAT54 5V MCLR VSS VSS 2480 F44 9 19 DOWN UP Figure 44. Complete Type K Thermocouple Meter www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005