LTC2481HDD-PBF

FEATURES n n n n n n n n n n n n n n n LTC2481 16-Bit ΔΣ ADC with Easy Drive Input Current Cancellation and I2C Interface DESCRIPTION The LTC®2481 combines a 16-bit plus sign No Latency ΔΣ™ analog-to-digital converter with patented Easy Drive technology and I2C digital interface. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals, with rail-torail input range to be directly digitized while maintaining exceptional DC accuracy. The LTC2481 includes on-chip programmable gain, a temperature sensor and an oscillator. The LTC2481 can be configured through an I2C interface to provide a programmable gain from 1 to 256 in 8 steps, to digitize an external signal or internal temperature sensor, reject line frequencies (50Hz, 60Hz or simultaneous 50Hz/60Hz) as well as a 2x speed-up mode. The LTC2481 allows a wide common mode input range (0V to VCC) independent of the reference voltage. The reference can be as low as 100mV or can be tied directly to VCC. The LTC2481 includes an on-chip trimmed oscillator eliminating the need for external crystals or oscillators. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No Latency Δ∑ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents Pending. Easy Drive™ Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy Programmable Gain from 1 to 256 Integrated Temperature Sensor GND to VCC Input/Reference Common Mode Range 2-Wire I2C Interface Programmable 50Hz, 60Hz or Simultaneous 50Hz/60Hz Rejection Mode 2ppm (0.25LSB) INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error Selectable 2x Speed Mode No Latency: Digital Filter Settles in a Single Cycle Single Supply 2.7V to 5.5V Operation Internal Oscillator Six Addresses Available and One Global Address for Synchronization Available in a Tiny (3mm × 3mm) 10-Lead DFN Package Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Strain Gauge Transducers Instrumentation Industrial Process Control DVMs and Meters APPLICATIONS n n n n n n n TYPICAL APPLICATION VCC 0.1μF 10k SENSE VIN– 10k 0.1μF GND IDIFF = 0 REF+ LTC2481 REF– VCC 1μF SCL SDA CA0/f0 CA1 2481 TA01a +FS Error vs RSOURCE at IN+ and IN– VCC = 5V 60 VREF = 5V VIN+ = 3.75V – 40 VIN = 1.25V fO = GND 20 TA = 25°C CIN = 1μF 0 –20 –40 –60 –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2481 TA01b 80 VIN+ 2-WIRE I2C INTERFACE 6 ADDRESSES +FS ERROR (ppm) 2481fc 1 LTC2481 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW REF+ VCC REF – IN+ IN– 1 2 3 4 5 11 10 CA0/f 0 9 CA1 8 GND 7 SDA 6 SCL Supply Voltage (VCC) to GND ...................... – 0.3V to 6V Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V) Digital Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND...... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2481C.................................................... 0°C to 70°C LTC2481I .................................................– 40°C to 85°C LTC2481H .............................................. –40°C to 125°C Storage Temperature Range ................. –65°C to 125°C DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2481CDD#PBF LTC2481IDD#PBF LTC2481HDD#PBF TAPE AND REEL LTC2481CDD#TRPBF LTC2481IDD#TRPBF LTC2481HDD#TRPBF PART MARKING* LBPV LBPV LBPV PACKAGE DESCRIPTION 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS (NORMAL SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF (H-Grade) 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF (H-Grade) 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 12) TA = 27°C See Table 2a The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN l l l l TYP 2 1 0.5 10 MAX 10 2.5 25 40 UNITS Bits ppm of VREF ppm of VREF μV nV/°C ppm of VREF ppm ppm of VREF /°C ppm of VREF ppm ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF μVRMS mV mV/°C 16 0.1 l 25 40 0.1 15 15 15 0.6 420 1.4 Output Noise Internal PTAT Signal Internal PTAT Temperature Coefficient Programmable Gain l 1 256 2481fc 2 LTC2481 ELECTRICAL CHARACTERISTICS (2X SPEED) PARAMETER Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Output Noise Programmable Gain CONDITIONS l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 16 2 1 0.5 100 25 0.1 l TYP MAX 10 2 UNITS Bits ppm of VREF mV nV/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C μVRMS Resolution (No Missing Codes) 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC See Table 2b 25 0.1 0.84 l 1 128 CONVERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz ± 2% Input Common Mode Rejection 60Hz ±2% Input Normal Mode Rejection 50Hz ±2% Input Normal Mode Rejection 60Hz ±2% Input Normal Mode Rejection 50Hz/60Hz ±2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ±2% Power Supply Rejection, 60Hz ±2% CONDITIONS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN l l l l l l l l l TYP MAX UNITS dB dB dB 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (H-Grade) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (H-Grade) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) VREF VREF VREF = 2.5V, IN– = IN+ = GND = 2.5V, IN– = IN+ = GND (Notes 7, 9) = 2.5V, IN– = IN+ = GND (Notes 8, 9) 140 140 140 110 104 110 104 87 120 140 120 120 120 120 120 dB dB dB dB dB dB dB dB dB ANALOG INPUT AND REFERENCE SYMBOL IN+ IN– FS LSB VIN VREF CS (IN+) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage Full Scale of the Differential Input (IN+ – IN–) Least Significant Bit of the Output Code Input Differential Voltage Range (IN+ – IN–) Reference Voltage Range (REF+ – REF–) IN+ Sampling Capacitance The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN GND – 0.3V GND – 0.3V l l l l TYP MAX VCC + 0.3V VCC + 0.3V UNITS V V V 0.5VREF/GAIN FS/216 –FS 0.1 11 +FS VCC V V pF 2481fc 3 LTC2481 ANALOG INPUT AND REFERENCE SYMBOL CS (IN–) CS (VREF) IDC_LEAK (IN+) IDC_LEAK (IN–) IDC_LEAK (VREF) PARAMETER IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current REF+, REF– DC Leakage Current Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, VREF = VCC l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN TYP 11 11 –10 –10 –100 1 1 1 10 10 100 MAX UNITS pF pF nA nA nA I2C DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL VIL(CA1) VIH(CA0/f0,CA1) RINH RINL RINF II VHYS VOL tOF tSP IIN CI CB CCAX VIH(EXT,OSC) VIL(EXT,OSC) PARAMETER High Level Input Voltage Low Level Input Voltage Low Level Input Voltage for Address Pin High Level Input Voltage for Address Pins Resistance from CA0/f0, CA1 to VCC to Set Chip Address Bit to 1 Resistance from CA1 to GND to Set Chip Address Bit to 0 Resistance from CA0/f0, CA1 to VCC or GND to Set Chip Address Bit to Float Digital Input Current Hysteresis of Schmitt Trigger Inputs Low Level Output Voltage SDA Output Fall Time from VIHMIN to VILMAX Input Spike Suppression Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line External Capacitive Load On-Chip Address Pins (CA0/f 0,CA1) for Valid Float High Level CA0/f0 External Oscillator Low Level CA0/f0 External Oscillator 2.7V ≤ VCC < 5.5V 2.7V ≤ VCC < 5.5V 0.1VCC ≤ VIN ≤ VCC (Note 5) I = 3mA CONDITIONS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN l l l l l l l l l l l l l l l l l TYP MAX 0.3VCC 0.05VCC UNITS V V V V kΩ kΩ MΩ 0.7VCC 0.95VCC 10 10 2 –10 0.05VCC 0.4 20+0.1CB 250 50 1 10 400 10 VCC – 0.5V 0.5 10 μA V V ns ns μA pF pF pF V V Bus Load CB 10pF to 400pF (Note 14) POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS l MIN 2.7 l l l TYP 160 1 MAX 5.5 250 2 20 UNITS V μA μA μA Conversion Mode (Note 11) Sleep Mode (Note 11) H-Grade 2481fc 4 LTC2481 TIMING CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time for 1x Speed Mode 50Hz Mode 50Hz Mode (H-Grade) 60Hz Mode 60Hz Mode (H-Grade) Simultaneous 50Hz/60Hz Mode Simultaneous 50Hz/60Hz Mode (H-Grade) External Oscillator (Note 10) 50Hz Mode 50Hz Mode (H-Grade) 60Hz Mode 60Hz Mode (H-Grade) Simultaneous 50Hz/60Hz Mode Simultaneous 50Hz/60Hz Mode (H-Grade) External Oscillator (Note 10) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS l l l l l l l l l l l l l l l l l MIN 10 0.125 0.125 157.2 157.2 131.0 131.0 144.1 144.1 78.7 65.6 72.2 TYP MAX 4000 100 100 UNITS kHz μs μs ms ms ms ms ms ms ms ms ms ms ms ms ms ms 160.3 160.3 133.6 133.6 146.9 146.9 41036/fEOSC 80.3 66.9 73.6 20556/fEOSC 163.5 165.1 136.3 137.6 149.9 151.0 81.9 82.7 68.2 68.9 75.1 75.6 tCONV_2 Conversion Time for 2x Speed Mode I2C TIMING CHARACTERISTICS SYMBOL fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) PARAMETER SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Clock Pin HIGH Period of the SCL Clock Pin Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for Both SDA and SCL Signals Fall Time for Both SDA and SCL Signals Set-Up Time for STOP Condition The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15) CONDITIONS l l l l l l l l l l MIN 0 0.6 1.3 0.6 0.6 0 100 20+0.1CB 20+0.1CB 0.6 TYP MAX 400 UNITS kHz μs μs μs μs 0.9 300 300 μs ns ns ns μs (Note 14) (Note 14) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF/GAIN; VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator). Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The external oscillator is connected to the CA0/f0 pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation. Note 14: CB = capacitance of one bus line in pF . Note 15: All values refer to VIH(MIN) and VIL(MAX) levels. 2481fc 5 LTC2481 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) 1 0 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V –45°C INL (ppm OF VREF) 3 2 1 0 –1 –2 –3 –1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V INL (ppm OF VREF) 3 2 1 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V 25°C –45°C, 25°C, 90°C –45°C, 25°C, 90°C 0 –1 –2 –3 –1.25 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2481 G02 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2481 G03 2481 G01 Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C VCC = 5V VREF = 5V VIN(CM) = 2.5V 25°C 12 8 85°C TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V 25°C 12 85°C 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V 25°C 85°C –45°C –45°C 2 2.5 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2481 G05 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2481 G06 2481 G04 Noise Histogram (6.8sps) 14 12 NUMBER OF READINGS (%) 10,000 CONSECUTIVE READINGS RMS = 0.60μV VCC = 5V AVERAGE = –0.69μV VREF = 5V 10 VIN = 0V GAIN = 256 8 TA = 25°C 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (μV) 1.2 1.8 14 12 NUMBER OF READINGS (%) Noise Histogram (7.5sps) 10,000 CONSECUTIVE READINGS RMS = 0.59μV VCC = 2.7V AVERAGE = –0.19μV VREF = 2.5V 10 VIN = 0V GAIN = 256 8 TA = 25°C 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (μV) 1.2 1.8 5 Long-Term ADC Readings VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V 4 GAIN = 256, TA = 25°C, RMS NOISE = 0.60μV 3 ADC READING ( V) 2 1 0 –1 –2 –3 –4 –5 0 10 30 40 20 TIME (HOURS) 50 60 2481 G09 2481 G07 2481 G08 2481fc 6 LTC2481 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs Input Differential Voltage 1.0 0.9 RMS NOISE (ppm OF VREF) 0.8 0.7 0.6 0.5 0.4 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) 1.0 VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C RMS NOISE (μV) 0.9 0.8 0.7 0.6 0.5 0.4 2.5 –1 0 1 2 3 4 5 6 2481 G11 RMS Noise vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 RMS Noise vs Temperature (TA) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND GAIN = 256 0.4 –45 –30 –15 VIN(CM) (V) 0 15 30 45 60 TEMPERATURE (°C) 75 90 2481 G10 2481 G12 RMS Noise vs VCC 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 0.4 2.7 VREF = 2.5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 0.4 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 RMS Noise vs VREF VCC = 5V VIN = 0V VIN(CM) = GND GAIN = 256 TA = 25°C 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 Offset Error vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25°C 0 1 2 3 VREF (V) 4 5 2481 G14 OFFSET ERROR (ppm OF VREF) –1 0 1 3 2 VIN(CM) (V) 4 5 6 2481 G15 2481 G13 Offset Error vs Temperature 0.3 0.2 0.1 0 0.3 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND 0.2 0.1 0 –0.1 –0.2 Offset Error vs VCC REF VIN = 0V VIN(CM) = GND TA = 25°C REF+ = 2.5V – = GND 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 –0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 0 1 2 3 VREF (V) 4 5 2481 G18 2481 G16 2481 G17 2481fc 7 LTC2481 TYPICAL PERFORMANCE CHARACTERISTICS Temperature Sensor vs Temperature 0.40 VCC = 5V VREF = 1.4V TEMPERATURE ERROR (°C) 5 4 3 FREQUENCY (kHz) 2 1 0 –1 –2 –3 –4 0.20 –60 –30 0 30 60 TEMPERATURE (°C) 90 120 2481 G19 Temperature Sensor Error vs Temperature VCC = 5V VREF = 1.4V 310 On-Chip Oscillator Frequency vs Temperature 308 0.35 VPTAT/VREF (V) 306 0.30 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND 0 15 30 45 60 TEMPERATURE (°C) 75 90 0.25 302 –5 –60 –30 30 60 0 TEMPERATURE (°C) 90 120 2481 G20 300 –45 –30 –15 2481 G21 On-Chip Oscillator Frequency vs VCC 310 VREF = 2.5V VIN = 0V VIN(CM) = GND REJECTION (dB) 0 –20 –40 306 –60 –80 –100 302 –120 300 –140 PSRR vs Frequency at VCC VCC = 4.1V DC VREF = 2.5V IN+ = GND IN– = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 PSRR vs Frequency at VCC VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND TA = 25°C 308 FREQUENCY (kHz) 304 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2481 G22 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2481 G24 2481 G23 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 TA = 25°C –60 –80 –100 –120 –140 30600 0 200 Conversion Current vs Temperature 2.0 1.8 CONVERSION CURRENT (μA) SLEEP MODE CURRENT (μA) 180 VCC = 5V 160 VCC = 2.7V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Sleep Mode Current vs Temperature REJECTION (dB) VCC = 5V 140 VCC = 2.7V 120 30650 30750 FREQUENCY AT VCC (Hz) 30700 30800 2481 G25 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2481 G26 2481 G27 2481fc 8 LTC2481 TYPICAL PERFORMANCE CHARACTERISTICS Conversion Current vs Output Data Rate 500 VREF = VCC + 450 IN– = GND IN = GND 400 CA0/f0 = EXT OSC TA = 25°C 350 300 250 200 150 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 G28 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 5V) 3 2 VCC = 5V INL (ppm OF VREF) 1 0 –1 –45°C –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –2 25°C, 90°C VCC = 5V VREF = 5V VIN(CM) = 2.5V INL (ppm OF VREF) 3 2 1 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V SUPPLY CURRENT (μA) 90°C 0 –1 –45°C, 25°C VCC = 3V 2 2.5 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2481 G30 2481 G29 Integral Nonlinearity (2x Speed Mode; VCC = 2.7V, VREF = 2.5V) 3 2 INL (ppm OF VREF) 1 90°C 0 –1 –2 –3 –1.25 –45°C, 25°C VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V 16 Noise Histogram (2x Speed Mode) RMS = 0.86μV 10,000 CONSECUTIVE AVERAGE = 0.184mV 14 READINGS VCC = 5V 12 VREF = 5V VIN = 0V GAIN = 256 10 TA = 25°C 8 6 4 2 1.0 RMS Noise vs VREF (2x Speed Mode) NUMBER OF READINGS (%) 0.8 RMS NOISE (μV) 0.6 0.4 VCC = 5V VIN = 0V VIN(CM) = GND TA = 25°C 0 1 3 2 VREF (V) 4 5 2481 G33 0.2 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2481 G31 0 179 0 181.4 186.2 OUTPUT READING (μV) 183.8 188.6 2481 G32 Offset Error vs VIN(CM) (2x Speed Mode) 200 198 196 OFFSET ERROR (μV) 194 192 190 188 186 184 182 180 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2481 G34 Offset Error vs Temperature (2x Speed Mode) 240 230 OFFSET ERROR (μV) 220 210 200 190 180 170 160 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND VCC = 5V VREF = 5V VIN = 0V TA = 25°C 2481 G35 2481fc 9 LTC2481 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs VCC (2x Speed Mode) 250 VREF = 2.5V VIN = 0V VIN(CM) = GND TA = 25°C OFFSET ERROR (μV) 240 230 220 210 200 190 180 170 0 2.7 3 3.5 4 4.5 VCC (V) 5 5.5 2481 G36 Offset Error vs VREF (2x Speed Mode) 0 VCC = 5V VIN = 0V VIN(CM) = GND TA = 25°C REJECTION (dB) –20 –40 –60 –80 –100 –120 –140 0 1 2 3 VREF (V) 4 5 2481 G37 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC REF+ = 2.5V REF– = GND IN+ = GND IN– = GND TA = 25°C 200 OFFSET ERROR (μV) 150 100 50 160 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2481 G38 PSRR vs Frequency at VCC (2x Speed Mode) 0 –20 –40 –60 –80 –100 –120 –140 VCC = 4.1V DC ±1.4V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND TA = 25°C 0 –20 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC ±0.7V REF+ = 2.5V REF– = GND IN+ = GND –40 IN– = GND TA = 25°C RREJECTION (dB) REJECTION (dB) –60 –80 –100 –120 –140 30600 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2481 G39 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2481 G40 PIN FUNCTIONS REF+ (Pin 1), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is more positive than the reference negative input, REF –, by at least 0.1V. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1μF tantalum capacitor in parallel with 0.1μF ceramic capacitor as close to the part as possible. IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5 • VREF /GAIN to 0.5 • VREF/GAIN. Outside this input range the converter produces unique overrange and underrange output codes. 2481fc 10 LTC2481 PIN FUNCTIONS SCL (Pin 6): Serial Clock Pin of the I2C Interface. The LTC2481 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. SDA (Pin 7): Bidirectional Serial Data Line of the I2C Interface. In the transmitter mode (Read), the conversion result is output through the SDA pin, while in the receiver mode (Write), the device configuration bits are input through the SDA pin. At data input mode, the pin is high impedance; while at data output mode, it is an open-drain N-channel driver and therefore an external pull-up resistor or current source to VCC is needed. GND (Pin 8): Ground. Connect this pin to a ground plane through a low impedance connection. CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is configured as a three state (LOW, HIGH, or Floating) address control bit for the device I2C address. CA0/f0 (Pin 10): Chip Address Control Pin/External Clock Input Pin. When no transition is detected on the CA0/f0 pin, it is a two state (HIGH or Floating) address control bit for the device I2C address. When the pin is driven by an external clock signal with a frequency fEOSC of at least 10kHz, the converter uses this signal as its system clock and the fundamental digital filter rejection null is located at a frequency fEOSC/5120 and sets the Chip Address CA0 internally to a HIGH. FUNCTIONAL BLOCK DIAGRAM 2 1 4 5 REF+ IN+ IN– MUX IN+ VCC SCL I2C SERIAL INTERFACE SDA CA1 CA0/f 0 REF+ 6 7 9 10 3RD ORDER ADC (1-256) IN– REF– GAIN TEMP SENSOR AUTOCALIBRATION AND CONTROL REF– 3 8 GND INTERNAL OSCILLATOR 2481 FD 2481fc 11 LTC2481 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2481 is a low power, ΔΣ analog-to-digital converter with an I2C interface. After power on reset, its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output/input (see Figure 1). POWER ON RESET DEFAULT CONFIGURATION: EXTERNAL INPUT GAIN = 1 50/60Hz REJECTION 1X SPEED, AUTOCAL CONVERSION The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a read/write request. Once the LTC2481 is addressed for a read operation, the device begins outputting the conversion result under control of the serial clock (SCL). There is no latency in the conversion result. The data output is 24 bits long and contains a 16-bit plus sign conversion result plus a readback of the configuration bits corresponds to the conversion just performed. This result is shifted out on the SDA pin under the control of the SCL. Data is updated on the falling edges of SCL allowing the user to reliably latch data on the rising edge of SCL. In write operation, the device accepts one configuration byte and the data is shifted in on the rising edges of the SCL. A new conversion is initiated by a STOP condition following a valid write operation or at the conclusion of a data read operation (read out all 24 bits). I2C INTERFACE SLEEP NO ACKNOWLEDGE YES DATA OUTPUT/INPUT NO STOP OR READ 24-BITS YES 2481 F01 The LTC2481 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the bus wires LOW and can never drive the bus HIGH. The bus wires are externally connected to a positive supply voltage via a currentsource or pull-up resistor. When the bus is free, both lines are HIGH. Data on the I2C-bus can be transferred at rates of up to 100kbit/s in the Standard-mode and up to 400kbit/s in the Fast-mode. The VCC power should not be removed from the device when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. Each device on the I2C bus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At the same time any device addressed is considered a slave. Figure 1. LTC2481 State Transition Diagram Initially, the LTC2481 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as it is not addressed for a read/write operation. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. 2481fc 12 LTC2481 APPLICATIONS INFORMATION The LTC2481 can only be addressed as a slave. Once addressed, it can receive configuration bits or transmit the last conversion result. Therefore the serial clock line SCL is an input only and the data line SDA is bidirectional. The device supports the Standard-mode and the Fast-mode for data transfer speeds up to 400kbit/s. Figure 2 shows the definition of timing for Fast/Standard-mode devices on the I2C-bus. The START and STOP Conditions A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free again a certain time after the STOP condition. START and STOP conditions are always generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical to the START (S). Data Transferring After the START condition, the I2C bus is busy and data transfer is set between a master and a slave. Data is transferred over I2C in groups of nine bits (one byte) followed by an acknowledge bit, therefore each group takes nine SCL cycles. The transmitter releases the SDA line during the acknowledge clock pulse and the receiver issues an Acknowledge (ACK) by pulling SDA LOW or leaves SDA HIGH to indicate a Not Acknowledge (NACK) condition. Change of data state can only happen while SCL is LOW. Accessing the Special Features of the LTC2481 The LTC2481 combines a high resolution, low noise ΔΣ analog-to-digital converter with an on-chip selectable temperature sensor, programmable gain, programmable digital filter and output rate control. These special features are selected through a single 8-bit serial input word during the data input/output cycle (see Figure 3). The LTC2481 powers up in a default mode commonly used for most measurements. The device will remain in this mode until a valid write cycle is performed. In this default mode, the measured input is external, the GAIN is 1, the digital filter simultaneously rejects 50Hz and 60Hz line frequency noise, and the speed mode is 1x (offset automatically, continuously calibrated). The I2C serial interface grants access to any or all special functions contained within the LTC2481. In order to change the mode of operation, a valid write address followed by 8 bits of data are shifted into the device (see Table 1). The first 3 bits (GS2, GS1, GS0) control the GAIN of the converter from 1 to 256. The 4th bit is reserved and should be low. The 5th bit (IM) is used to select the internal temperature sensor as the conversion input, while the 6th and 7th bits (FA, FB) combine to determine the line frequency rejection mode. The 8th bit (SPD) is used to double the output rate by disabling the offset auto calibration. SDA tf SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S 2481 F02 tLOW tr tSU;DAT tr tHD;STA tSP tr tBUF Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus 2481fc 13 LTC2481 APPLICATIONS INFORMATION 1 SCL 2 … 7 8 9 1 2 3 4 5 6 7 8 9 SDA START BY MASTER 7-BIT ADDRESS W ACK BY LTC2481 SLEEP GS2 GS1 GS0 IM FA FB SPD ACK BY LTC2481 DATA INPUT 2481 F03 Figure 3. Timing Diagram for Writing to the LTC2481 Table 1. Selecting Special Modes Rejection Mode FB SPD Comments External Input, Gain = 1, Autocalibration External Input, Gain = 4, Autocalibration External Input, Gain = 8, Autocalibration External Input, Gain = 16, Autocalibration External Input, Gain = 32, Autocalibration External Input, Gain = 64, Autocalibration External Input, Gain = 128, Autocalibration External Input, Gain = 256, Autocalibration External Input, Gain = 1, 2x Speed External Input, Gain = 2, 2x Speed External Input, Gain = 4, 2x Speed External Input, Gain = 8, 2x Speed External Input, Gain = 16, 2x Speed External Input, Gain = 32, 2x Speed External Input, Gain = 64, 2x Speed External Input, Gain = 128, 2x Speed External Input, Simultaneous 50Hz/60Hz Rejection External Input, 50Hz Rejection External Input, 60Hz Rejection Reserved, Do Not Use Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration Reserved, Do Not Use Gain GS2 GS1 GS0 IM FA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Any Gain X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Any 0 0 Rejection 1 0 Mode 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 Any 1 0 Speed 0 1 1 0 1 0 0 X 1 0 1 X 1 1 0 X 1 1 1 X 2481 TBL1 2481fc 14 LTC2481 APPLICATIONS INFORMATION Table 2a. The LTC2481 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V) GAIN Input Span LSB Noise Free Resolution* Gain Error Offset Error 1 ±2.5 38.1 65536 5 0.5 4 ±0.625 9.54 65536 5 0.5 8 ±0.312 4.77 65536 5 0.5 16 ±0.156 2.38 65536 5 0.5 32 ±78m 1.19 65536 5 0.5 64 ±39m 0.596 65536 5 0.5 128 ±19.5m 0.298 32768 5 0.5 256 ±9.76m 0.149 16384 8 0.5 UNIT V μV Counts ppm of FS μV Table 2b. The LTC2481 Performance vs GAIN in 2x Speed Mode (VCC = 5V, VREF = 5V) GAIN Input Span LSB Noise Free Resolution* Gain Error Offset Error 1 ±2.5 38.1 65536 5 200 2 ±1.25 19.1 65536 5 200 4 ±0.625 9.54 65536 5 200 8 ±0.312 4.77 65536 5 200 16 ±0.156 2.38 65536 5 200 32 ±78m 1.19 65536 5 200 64 ±39m 0.596 45875 5 200 128 ±19.5m 0.298 22937 5 200 UNIT V μV Counts ppm of FS μV *The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger. GAIN (GS2, GS1, GS0) The input referred gain of the LTC2481 is adjustable from 1 to 256. With a gain of 1, the differential input range is ±VREF/2 and the common mode input range is rail-to-rail. As the GAIN is increased, the differential input range is reduced to ±VREF/2 • GAIN but the common mode input range remains rail-to-rail. As the differential gain is increased, low level voltages are digitized with greater resolution. At a gain of 256, the LTC2481 digitizes an input signal range of ±9.76mV with over 16,000 counts. Temperature Sensor (IM) The LTC2481 includes an on-chip temperature sensor. The temperature sensor is selected by setting IM = 1 in the serial input data stream. Conversions are performed directly on the temperature sensor by the converter. While operating in this mode, the device behaves as a temperature to bits converter. The digital reading is proportional to the absolute temperature of the device. This feature allows the converter to linearize temperature sensors or continuously remove temperature effects from external sensors. Several applications leveraging this feature are presented in more detail in the applications section. While operating in this mode, the gain is set to 1 and the speed is set to normal independent of the control bits (GS2, GS1, GS0 and SPD). Rejection Mode (FA, FB) The LTC2481 includes a high accuracy on-chip oscillator with no required external components. Coupled with a 4th order digital lowpass filter, the LTC2481 rejects line frequency noise. In the default mode, the LTC2481 simultaneously rejects 50Hz and 60Hz by at least 87dB. The LTC2481 can also be configured to selectively reject 50Hz or 60Hz to better than 110dB. Speed Mode (SPD) The LTC2481 continuously performs offset calibrations. Every conversion cycle, two conversions are automatically performed (default) and the results combined. This result is free from offset and drift. In applications where the offset is not critical, the autocalibration feature can be disabled with the benefit of twice the output rate. Linearity, full-scale accuracy and full-scale drift are identical for both 2x and 1x speed modes. In both the 1x and 2x speed there is no latency. This enables input steps or multiplexer channel changes to settle in a single conversion cycle easing system overhead and increasing the effective conversion rate. 2481fc 15 LTC2481 APPLICATIONS INFORMATION LTC2481 Data Format After a START condition, the master sends a 7-bit address followed by a R/W bit. The bit R/W is 1 for a Read request and 0 for a Write request. If the 7-bit address agrees with an LTC2481’s address, that device is selected. When the device is in the conversion state, it does not accept the request and issues a Not-Acknowledge (NACK) by leaving SDA HIGH. If the conversion is complete, it issues an acknowledge (ACK) by pulling SDA LOW. The LTC2481 has two registers. The output register contains the result of the last conversion and a user programmable configuration register that sets the converter operation mode. The output register contains the last conversion result. After each conversion is completed, the device automatically enters the sleep state where the supply current is reduced to 1μA. When the LTC2481 is addressed for a Read operation, it acknowledges (by pulling SDA LOW) and acts as a transmitter. The master and receiver can read up to three bytes from the LTC2481. After a complete Read operation (3 bytes), the output register is emptied, a new conversion is initiated, and a following Read request in the same input/output phase will be NACKed. The LTC2481 output data stream is 24 bits long, shifted out on the falling edges of SCL. The first bit is the conversion result sign bit (SIG), see Tables 3 and 4. This bit is HIGH if VIN ≥ 0. It is Table 4. LTC2481 Output Data Format DIFFERENTIAL INPUT VOLTAGE VIN* VIN* ≥ FS** FS** – 1LSB 0.5 • FS** 0.5 • FS** – 1LSB 0 –1LSB – 0.5 • FS** – 0.5 • FS** – 1LSB – FS** VIN* < –FS** = IN+ – IN–. BIT 23 SIG 1 1 1 1 1/0*** 0 0 0 0 0 BIT 22 MSB 1 0 0 0 0 1 1 1 1 0 BIT 21 0 1 1 0 0 1 1 0 0 1 BIT 20 0 1 0 1 0 1 0 1 0 1 BIT 19 0 1 0 1 0 1 0 1 0 1 … … … … … … … … … … … BIT 6 0 1 0 1 0 1 0 1 0 1 LOW if VIN 1nF at Both IN+ Constant VIN(CM) – VREF(CM) and IN–. Can Take Large Source Resistance with Negligible Error UNBALANCED INPUT RESISTANCES CEXT > 1nF at Both IN+ and IN–. Can Take Large Source Resistance. Unbalanced Resistance Results in an Offset Which Can be Calibrated Minimize IN+ and IN– Capacitors and Avoid Large Source Impedance (< 5k Recommended) a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1μV typical and 10μV maximum offset voltage. Reference Current In a similar fashion, the LTC2481 samples the differential reference pins REF+ and REF– transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations. For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same. Using internal oscillator for 60Hz mode, the typical differential reference resistance is 1MΩ which generates a full-scale (VREF/2) gain error of 0.51ppm for each ohm of source resistance driving the REF+ and REF– pins. For 50Hz/60Hz mode, the related difference resistance is 1.1MΩ and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving 2481fc Varying CEXT > 1nF at Both IN+ VIN(CM) – VREF(CM) and IN–. Can Take Large Source Resistance with Negligible Error The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such 24 LTC2481 APPLICATIONS INFORMATION the REF+ and REF– pins. For 50Hz mode, the related difference resistance is 1.2MΩ and the resulting full-scale error is 0.42ppm for each ohm of source resistance driving the REF+ and REF– pins. When CA0/f0 is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.30 • 1012/fEOSC Ω and each ohm of source resistance driving the REF+ or REF– pins will result in 1.67 • 10–6 • fEOSCppm gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the REF+ or REF– pins and external capacitance connected to that pin are shown in Figures 16-19. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms –VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference 90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 –10 0 0 10 1k 100 RSOURCE (Ω) 10k 100k 2481 F16 pin current as expressed in Figure 12. When using internal oscillator and 60Hz mode, every 100Ω of reference source resistance translates into about 0.67ppm additional INL error. When using internal oscillator and 50Hz/60Hz mode, every 100Ω of reference source resistance translates into about 0.61ppm additional INL error. When using internal oscillator and 50Hz mode, every 100Ω of reference source resistance translates into about 0.56ppm additional INL error. When CA0/f0 is driven by an external oscillator with a frequency fEOSC, every 100Ω of source resistance driving REF+ or REF– translates into about 2.18 • 10–6 • fEOSCppm additional INL error. Figure 20 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The user is advised to minimize the source impedance driving the REF+ and REF– pins. 500 VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V TA = 25°C +FS ERROR (ppm) VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V TA = 25°C CREF = 0.01μF CREF = 0.001μF CREF = 100pF CREF = 0pF CREF = 1μF 10μF , 400 300 CREF = 0.1μF 200 CREF = 0.01μF 100 0 200 600 400 RSOURCE (Ω) 800 1000 2481 F18 Figure 16. +FS Error vs RSOURCE 10 0 –10 –FS ERROR (ppm) –20 –30 –40 –50 –60 VCC = 5V VREF = 5V –70 V + = 1.25V IN – –80 VIN = 3.75V TA = 25°C –90 10 0 CREF = 0.01μF CREF = 0.001μF CREF = 100pF CREF = 0pF at REF+ or REF– (Small C REF) Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Large CREF) 0 –100 –FS ERROR (ppm) CREF = 0.01μF –200 CREF = 1μF 10μF , –300 VCC = 5V VREF = 5V VIN+ = 1.25V VIN– = 3.75V TA = 25°C 0 200 600 400 RSOURCE (Ω) CREF = 0.1μF –400 1k 100 RSOURCE (Ω) 10k 100k 2481 F17 –500 800 1000 2481 F19 Figure 17. –FS Error vs RSOURCE at REF+ or REF– (Small CREF) Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Large CREF) 2481fc 25 LTC2481 APPLICATIONS INFORMATION In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (VREFCM – VINCM) and a 5V reference, each Ohm of reference source resistance introduces an extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error, which is 0.074ppm when using internal oscillator and 60Hz mode. When using internal oscillator and 50Hz/60Hz mode, the extra full-scale gain error is 0.067ppm. When using internal oscillator and 50Hz mode, the extra gain error is 0.061ppm. If an external clock is used, the corresponding extra gain error is 0.24 • 10–6 • fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature 10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10μF 2 0 –2 –4 –6 –8 –10 –0.5 –0.3 0.1 –0.1 VIN/VREF (V) 0.3 0.5 2481 F20 and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by VREF+ and VREF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±100nA max), results in a small gain error. A 100Ω source resistance will create a 0.05μV typical and 5μV maximum full-scale error. 3500 R = 1k +FS ERROR (ppm OF VREF) 3000 2500 VIN(CM) = VREF(CM) VCC = VREF = 5V CA0/f0 = EXT CLOCK INL (ppm OF VREF) TA = 85°C 2000 1500 1000 500 0 TA = 25°C R = 500Ω R = 100Ω 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F22 Figure 20. INL vs DIFFERENTIAL Input Voltage and Reference Source Resistance for CREF > 1μF 50 40 30 TA = 85°C 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F21 Figure 22. +FS Error vs Output Data Rate and Temperature OFFSET ERROR (ppm OF VREF) –FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V CA0/f0 = EXT CLOCK 0 –500 –1000 TA = 25°C TA = 85°C –1500 –2000 –2500 –3000 VIN(CM) = VREF(CM) VCC = VREF = 5V CA0/f0 = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F23 –3500 Figure 21. Offset Error vs Output Data Rate and Temperature Figure 23. –FS Error vs Output Data Rate and Temperature 2481fc 26 LTC2481 APPLICATIONS INFORMATION Output Data Rate When using its internal oscillator, the LTC2481 produces up to 7.5 samples per second (sps) with a notch frequency of 60Hz, 6.25sps with a notch frequency of 50Hz and 6.82sps with the 50Hz/60Hz rejection mode. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (CA0/f0 connected to an external oscillator), the LTC2481 output data rate can be increased as desired. The duration of the conversion phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves as if the internal oscillator is used and the notch is set at 60Hz. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2481’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2481 typical performance can be inferred from Figures 14, 15, 16 and 17 in which the horizontal axis is scaled by 307200/fEOSC. Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3x increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 21 to 28. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2481 input bandwidth. When the internal oscillator is used with the notch set at 60Hz, the 3dB input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If an external conversion clock generator of frequency fEOSC is connected to the CA0/f0 pin, the 3dB input bandwidth is 11.8 • 10–6 • fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2481 input bandwidth is shown in Figure 29. When an external oscillator of frequency fEOSC is used, the shape of the LTC2481 input bandwidth can be derived from Figure 29, 60Hz mode curve in which the horizontal axis is scaled by fEOSC/307200. The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nV√Hz for an infinite bandwidth source and 64nV√Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively 2481fc 27 LTC2481 APPLICATIONS INFORMATION 24 TA = 25°C 22 TA = 85°C RESOLUTION (BITS) RESOLUTION (BITS) 20 18 16 14 12 10 VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V CA0/f0 = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F24 22 20 18 TA = 85°C 16 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V CA0/f0 = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F25 20 OFFSET ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VIN = 0V 15 CA0/f0 = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F26 Figure 24. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature 24 VCC = VREF = 5V 22 RESOLUTION (BITS) Figure 25. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 22 20 Figure 26. Offset Error vs Output Data Rate and Reference Voltage RESOLUTION (BITS) 20 18 16 VCC = 5V, VREF = 2.5V 18 VCC = VREF = 5V 16 14 VCC = 5V, VREF = 2.5V 14 VIN(CM) = VREF(CM) VIN = 0V CA0/f0 = EXT CLOCK 12 T = 25°C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F27 VIN(CM) = VREF(CM) VIN = 0V 12 CA0/f0 = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2481 F28 Figure 27. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage 0 INPUT SIGNAL ATTENUATION (dB) –1 50Hz AND 60Hz MODE –2 –3 –4 –5 –6 50Hz MODE 60Hz MODE Figure 28. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage 100 INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) 10 60Hz MODE 50Hz MODE 1 1 3 0 4 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2481 F29 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2481 F30 Figure 29. Input Signal Using the Internal Oscillator Figure 30. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source 2481fc 28 LTC2481 APPLICATIONS INFORMATION high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2481, the ADC input referred system noise calculation can be simplified by Figure 30. The noise of an amplifier driving the LTC2481 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 30, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni • √freqi. The total system noise (referred to the LTC2481 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2481 internal noise, the noise of the IN+ driving amplifier and the noise of the IN– driving amplifier. If the CA0/f0 pin is driven by an external oscillator of frequency fEOSC, Figure 30 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. 0 INPUT NORMAL MODE REJECTION (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2481 F31 For large values of the ratio fEOSC/307200, the Figure 30 plot accuracy begins to decrease, but at the same time the LTC2481 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2481 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2481 allows external lowpass filtering without degrading the DC performance of the device. The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2481’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048 • fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode with a 50Hz notch setting, fS = 12800Hz, with 50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch setting fS = 15360Hz. In the external oscillator mode, fS = fEOSC/20. The performance of the normal mode rejection is shown in Figures 31 and 32. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2481 F32 –10 Figure 31. Input Normal Mode Rejection, Internal Oscillator and 50Hz Notch Mode Figure 32. Input Normal Mode Rejection at DC 2481fc 29 LTC2481 APPLICATIONS INFORMATION In 1x speed mode, the regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 33 (rejection near DC) and Figure 34 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figures 35, 36 and 37. Typical measured values of the normal mode rejection of the LTC2481 operating with an internal oscillator and a 60Hz notch setting are shown in Figure 35 superimposed over the theoretical calculated curve. Similarly, the measured normal mode rejection of the LTC2481 for the 50Hz rejection mode and 50Hz/60Hz rejection mode are shown in Figures 36 and 37. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2481. If passive RC components are placed in front of the LTC2481, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2481 allows external RC networks without significant degradation in DC performance. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2481 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full-scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed on volt level perturbations and the LTC2481 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2481 has a full-scale differential input range of 5V peak-to-peak. Figures 38 and 39 show measurement results for the LTC2481 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peak-to-peak (full-scale) input signal. In Figure 38, the LTC2481 uses the internal oscillator with the notch set at 60Hz and in Figure 39 it uses the internal oscillator with the notch set at 50Hz. It is clear that the LTC2481 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2481 F34 fN = fEOSC/5120 2481 F33 Figure 33. Input Normal Mode Rejection at DC Figure 34. Input Normal Mode Rejection at fs = 256fN 2481fc 30 LTC2481 APPLICATIONS INFORMATION 0 NORMAL MODE REJECTION (dB) –20 –40 –60 –80 –100 –120 MEASURED DATA CALCULATED DATA NORMAL MODE REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 –60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2481 F35 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2481 F36 Figure 35. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full-Scale (60Hz Notch) Figure 36. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full-Scale (50Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 –60 –80 –100 –120 MEASURED DATA CALCULATED DATA NORMAL MODE REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 –60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VINCM = 2.5V TA = 25°C 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2481 F37 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2481 F38 Figure 37. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full-Scale (50Hz/60Hz Mode) Figure 38. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full-Scale (60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 –60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2481 F39 Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full-Scale (50Hz Notch) 2481fc 31 LTC2481 APPLICATIONS INFORMATION 0 INPUT NORMAL REJECTION (dB) INPUT NORMAL REJECTION (dB) 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (fN) 8fN 2481 F40 0 –20 –40 –60 –80 –100 –120 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY (fN) 2481 F41 –20 –40 –60 –80 –100 –120 Figure 40. Input Normal Mode Rejection 2x Speed Mode Figure 41. Input Normal Mode Rejection 2x Speed Mode 0 NORMAL MODE REJECTION (dB) –20 –40 –60 –80 –70 NORMAL MODE REJECTION (dB) MEASURED DATA VCC = 5V CALCULATED DATA VREF = 5V VINCM = 2.5V VIN(P-P) = 5V TA = 25°C –80 NO AVERAGE –90 –100 –110 –120 –130 –140 0 25 50 75 100 125 150 175 200 225 INPUT FREQUENCY (Hz) 2481 F42 WITH RUNNING AVERAGE –100 –120 60 62 54 56 58 48 50 52 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2481 F43 Figure 42. Input Normal Mode Rejection vs Input Frequency, 2x Speed Mode and 50Hz/60Hz Mode Figure 43. Input Normal Mode Rejection 2x Speed Mode 5V C8 1μF ISOTHERMAL C7 0.1μF LT1236 2 IN OUT TRIM GND 4 6 5 R7 8k R8 1k + G1 NC1M4V0 R2 2k 4 IN+ IN– 5 1 2 REF+ VCC SCL SDA LTC2481 CA1 CA0/f0 REF– GND 3 8 1.7k 6 7 9 10 1.7k 2481 F44 TYPE K THERMOCOUPLE JACK (OMEGA MPJ-K-F) 26.3C Figure 44. Calibration Setup 2481fc 32 LTC2481 APPLICATIONS INFORMATION Using the 2x speed mode of the LTC2481, the device bypasses the digital offset calibration operation to double the output data rate. The superior normal mode rejection is maintained as shown in Figures 31 and 32. However, the magnified details near DC and fS = 256fN are different, see Figures 40 and 41. In 2x speed mode, the bandwidth is 11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz rejection mode and 12.4Hz for the 50Hz/60Hz rejection mode. Typical measured values of the normal mode rejection of the LTC2481 operating with the internal oscillator and 2x speed mode is shown in Figure 42. When the LTC2481 is configured in 2x speed mode, by performing a running average, a SINC1 notch is combined with the SINC4 digital filter, yielding the normal mode rejection identical as that for the 1x speed mode. The averaging operation still keeps the output rate with the following algorithm: Result 1 = average (sample 0, sample 1) Result 2 = average (sample 1, sample 2) …… Result n = average (sample n – 1, sample n) The main advantage of the running average is that it achieves simultaneous 50Hz/60Hz rejection at twice the effective output rate, as shown in Figure 43. The raw output data provides a better than 70dB rejection over 48Hz to 62.4Hz, which covers both 50Hz ±2% and 60Hz ±2%. With running average on, the rejection is better than 87dB for both 50Hz ±2% and 60Hz ±2%. Complete Thermocouple Measurement System with Cold Junction Compensation The LTC2481 is ideal for direct digitization of thermocouples and other low voltage output sensors. The input has a typical offset error of 500nV (2.5μV max) offset drift of 10nV/°C and a noise level of 600nVRMS. The input span may be optimized for various sensors by setting the gain of the PGA. Using an external 5V reference with a PGA gain of 64 gives a ±78mV input range—perfect for thermocouples. Figure 45 (page 39 of this data sheet) is a complete type K thermocouple meter. The only signal conditioning is a simple surge protection network. In any thermocouple meter, the cold junction temperature sensor must be at the same temperature as the junction between the thermocouple materials and the copper printed circuit board traces. The tiny LTC2481 can be tucked neatly underneath an Omega MPJ-K-F thermocouple socket ensuring close thermal coupling. The LTC2481’s 1.4mV/°C PTAT circuit measures the cold junction temperature. Once the thermocouple voltage and cold junction temperature are known, there are many ways of calculating the thermocouple temperature including a straight-line approximation, lookup tables or a polynomial curve fit. Calibration is performed by applying an accurate 500mV to the ADC input derived from an LT®1236 reference and measuring the local temperature with an accurate thermometer as shown in Figure 44. In calibration mode, the up and down buttons are used to adjust the local temperature reading until it matches an accurate thermometer. Both the voltage and temperature calibration are easily automated. The complete microcontroller code for this application is available on the LTC2481 product webpage at: http://www.linear.com It can be used as a template for may different instruments and it illustrates how to generate calibration coefficients for the onboard temperature sensor. Extensive comments detail the operation of the program. The read_LTC2481() function controls the operation of the LTC2481 and is listed below for reference. 2481fc 33 LTC2481 APPLICATIONS INFORMATION /* LTC248X.h Processor setup and Lots of useful defines for configuring the LTC2481 and LTC2485. */ #include #use delay(clock=6000000) // Device // 6MHz clock //#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT // Configuration fuses #rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config. #use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port #include “PCM73A.h” // Various defines #include “lcd.c” // LCD driver functions // Useful defines for the LTC2481 and LTC2485 - OR them together to make the // 8 bit config word. #define READ 0x01 // bitwise OR with address for read or write #define WRITE 0x00 #define LTC248XADDR 0b01001000 // The one and only LTC248X in this circuit, // with both address lines floating. // Select gain - 1 to 256 (also depends on speed setting) #define GAIN1 0b00000000 // G = 1 (SPD = 0), G = 1 (SPD = 1) #define GAIN2 0b00100000 // G = 4 (SPD = 0), G = 2 (SPD = 1) #define GAIN3 0b01000000 // G = 8 (SPD = 0), G = 4 (SPD = 1) #define GAIN4 0b01100000 // G = 16 (SPD = 0), G = 8 (SPD = 1) #define GAIN5 0b10000000 // G = 32 (SPD = 0), G = 16 (SPD = 1) #define GAIN6 0b10100000 // G = 64 (SPD = 0), G = 32 (SPD = 1) #define GAIN7 0b11000000 // G = 128 (SPD = 0), G = 64 (SPD = 1) #define GAIN8 0b11100000 // G = 256 (SPD = 0), G = 128 (SPD = 1) // Select ADC source - differential input or PTAT circuit #define VIN 0b00000000 #define PTAT 0b00001000 // Select rejection frequency - 50, 55, or 60Hz #define R50 0b00000010 #define R55 0b00000000 #define R60 0b00000100 // Speed settings is bit 7 in the 2nd byte #define SLOW 0b00000000 // slow output rate with autozero #define FAST 0b00000001 // fast output rate with no autozero 2481fc 34 LTC2481 APPLICATIONS INFORMATION /* LTC2481.c Basic voltmeter test program for LTC2481 Reads LTC2481 input at gain = 1, 1X speed mode, converts to volts, and prints voltage to a 2 line by 16 character LCD display. Mark Thoren Linear Technology Corporation June 23, 2005 Written for CCS PCM compiler, Version 3.182 */ #include “LTC248X.h” /*** read_LTC2481() ************************************************************ This is the function that actually does all the work of talking to the LTC2481. Arguments: Returns: addr - device address config - configuration bits for next conversion zero if conversion is in progress, 32 bit signed integer with lower 8 bits clear, 24 bit LTC2481 output word in the upper 24 bits. Data is left-justified for compatibility with the 24 bit LTC2485. the i2c_xxxx() functions do the following: void i2c_start(void): generate an i2c start or repeat start condition void i2c_stop(void): generate an i2c stop condition char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device These functions are very compiler specific, and can use either a hardware i2c port or software emulation of an i2c port. This example uses software emulation. A good starting point when porting to other processors is to write your own i2c functions. Note that each processor has its own way of configuring the i2c port, and different compilers may or may not have built-in functions for the i2c port. When in doubt, you can always write a “bit bang” function for troubleshooting purposes. The “fourbytes” structure allows byte access to the 32 bit return value: struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; Also note that the lower 4 bits are the configuration word from the previous conversion. 2481fc 35 LTC2481 APPLICATIONS INFORMATION *******************************************************************************/ signed int32 read_LTC2481(char addr, char config) { struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; union // adc_code.bits32 all 32 bits { // adc_code.by.te0 byte 0 signed int32 bits32; // adc_code.by.te1 byte 1 struct fourbytes by; // adc_code.by.te2 byte 2 } adc_code; // adc_code.by.te3 byte 3 // Start communication with LTC2481: i2c_start(); if(i2c_write(addr | WRITE))// If no acknowledge, return zero { i2c_stop(); return 0; } i2c_write(config); i2c_start(); i2c_write(addr | READ); adc_code.by.te3 = i2c_read(); adc_code.by.te2 = i2c_read(); adc_code.by.te1 = i2c_read(); adc_code.by.te0 = 0; i2c_stop(); return adc_code.bits32; } // End of read_LTC2481() /*** initialize() ************************************************************** Basic hardware initialization of controller and LCD, send Hello message to LCD *******************************************************************************/ void initialize(void) { // General initialization stuff. setup_adc_ports(NO_ANALOGS); setup_adc(ADC_OFF); setup_counters(RTCC_INTERNAL,RTCC_DIV_1); setup_timer_1(T1_DISABLED); setup_timer_2(T2_DISABLED,0,1); // This is the important part - configuring the SPI port setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock CKP = 0; // Set up clock edges - clock idles low, data changes on CKE = 1; // falling edges, valid on rising edges. 2481fc 36 LTC2481 APPLICATIONS INFORMATION lcd_init(); delay_ms(6); printf(lcd_putc, “Hello!”); delay_ms(500); } // End of initialize() // Initialize LCD // Obligatory hello message // for half a second *** main() ******************************************************************** Main program initializes microcontroller registers, then reads the LTC2481 repeatedly *******************************************************************************/ void main() { signed int32 x; // Integer result from LTC2481 float voltage; // Variable for floating point math int16 timeout; initialize(); // Hardware initialization while(1) { delay_ms(1); // // // // // // Pace the main loop to something more than 1 ms This is a basic error detection scheme. The LTC248X will never take more than 163.5ms, 149.9ms, or 136.5ms to complete a conversion in the 50Hz, 55Hz, and 60Hz rejection modes, respectively. If read_LTC248X() does not return non-zero within this time period, something is wrong, such as an incorrect i2c address or bus conflict. if((x = read_LTC2481(LTC248XADDR, GAIN1 | VIN | R55)) != 0) { // No timeout, everything is okay timeout = 0; // reset timer x &= 0xFFFFFFC0; // clear config bits so they don’t affect math x ^= 0x80000000; // Invert MSB, result is 2’s complement voltage = (float) x; // convert to float voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31 lcd_putc(‘\f’); // Clear screen lcd_gotoxy(1,1); // Goto home position printf(lcd_putc, “V %01.4f”, voltage); // Display voltage } else { ++timeout; } if(timeout > 200) { timeout = 200; // Prevent rollover lcd_gotoxy(1,1); printf(lcd_putc, “ERROR - TIMEOUT”); delay_ms(500); } } // End of main loop } // End of main() 2481fc 37 LTC2481 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev B) 0.70 0.05 3.55 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.125 TYP 6 0.40 10 0.10 3.00 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 1.65 0.10 (2 SIDES) (DD) DFN REV B 0309 5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES) 1 0.25 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2481fc 38 LTC2481 REVISION HISTORY REV A B C DATE 11/09 04/10 06/10 DESCRIPTION Update Tables 3 and 4 Added H-grade to Absolute Maximum Ratings, Order Information, Electrical Characteristics (Normal Speed), Converter Characteristics, Power Requirements, Timing Characteristics, and Typical Performance Characteristics Revised Typical Application drawing Added text to I2C Interface section PAGE NUMBER 16 2-10 1 12 2481fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 39 LTC2481 TYPICAL APPLICATION 5V PIC16F73 C8 1μF ISOTHERMAL R2 2k 32 REF VCC LTC2481 TYPE K THERMOCOUPLE JACK (OMEGA MPJ-K-F) 5 C7 0.1μF 1.7k 1.7k 18 17 16 15 14 13 12 11 28 27 26 25 24 23 22 21 7 6 5 4 3 2 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA5 RA4 RA3 RA2 RA1 RA0 VDD 20 C6 0.1μF Y1 6MHz 5V 4 IN+ SCL SDA 6 7 OSC1 OSC2 9 10 IN– 10 CA1 GND REF– CAO/fO 9 5V 8 3 MCLR R1 1 10k D1 BAT54 5V 5V 1 R6 5k 2 3 D7 D6 2 16 CHARACTER D5 LCD DISPLAY D4 (OPTREX DMC162488 EN OR SIMILAR) RW CONTRAST GND D0 D1 D2 D3 RS VCC 5V CALIBRATE 2 1 R3 10k R4 10k R5 10k 9 VSS 19 VSS 2481 F45 DOWN UP Figure 45. Complete Type K Thermocouple Meter RELATED PARTS PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 LTC2411/ LTC2411-1 LTC2413 LTC2415/ LTC2415-1 LTC2414/LTC2418 LTC2440 LTC2480 LTC2482 LTC2483 LTC2484 LTC2485 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency ΔΣ ADC in SO-8 24-Bit, No Latency ΔΣ ADC with Differential Inputs 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP 24-Bit, No Latency ΔΣ ADC with Differential Inputs 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate 8-/16-Channel 24-Bit, No Latency ΔΣ ADCs High Speed, Low Noise 24-Bit ΔΣ ADC 16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit ΔΣ ADC with Easy Drive Inputs 16-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface 24-Bit ΔΣ ADC with Easy Drive Inputs 24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface and Temperature Sensor 2481fc COMMENTS 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.05% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.8μVRMS Noise, 2ppm INL 1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs Pin Compatible with LTC2482/LTC2484 Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2481/LTC2483 Pin Compatible with LTC2480/LTC2482 Pin Compatible with LTC2481/LTC2483 40 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0610 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005