LTC2482IDD-TRPBF

FEATURES n n n n n n n n n n n n LTC2482 16-Bit ΔΣ ADC with Easy Drive Input Current Cancellation DESCRIPTION The LTC®2482 combines a 16-bit plus sign No Latency ΔΣ™ analog-to-digital converter with patented Easy Drive™ technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals with rail-to-rail input range to be directly digitized while maintaining exceptional DC accuracy. The LTC2482 allows a wide common mode input range (0V to VCC) independent of the reference voltage. The reference can be as low as 100mV or can be tied directly to VCC. The noise level is 600nV RMS independent of VREF . This allows direct digitization of low level signals with 16-bit accuracy. The LTC2482 includes an on-chip trimmed oscillator, eliminating the need for external crystals or oscillators and provides 87dB rejection of 50Hz and 60Hz line frequency noise. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending. Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise, Independent of VREF Operates with a Reference as Low as 100mV with 16-Bit Resolution GND to VCC Input/Reference Common Mode Range Simultaneous 50Hz/60Hz Rejection Mode 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Total Unadjusted Error No Latency: Digital Filter Settles in a Single Cycle Single Supply 2.7V to 5.5V Operation Internal Oscillator Available in a Tiny (3mm × 3mm) 10-Lead DFN Package APPLICATIONS n n n n n n n Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Strain Gauge Transducers Instrumentation Industrial Process Control DVMs and Meters TYPICAL APPLICATION 80 VCC 1μF 10k SENSE 10k +FS ERROR (ppm) +FS Error vs RSOURCE at IN+ and IN– VCC = 5V 60 VREF = 5V VIN+ = 3.75V – 40 VIN = 1.25V fO = GND 20 TA = 25°C CIN = 1μF 0 –20 –40 –60 –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2482 TA02 IDIFF = 0 1μF VIN+ VREF LTC2482 VCC SDO SCK CS 3-WIRE SPI INTERFACE VIN– GND fO 2482 TA01 2482fb 1 LTC2482 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW *GND VCC VREF IN+ IN– 1 2 3 4 5 11 10 fO 9 SCK 8 GND 7 SDO 6 CS Supply Voltage (VCC) to GND ...................... –0.3V to 6V Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ –0.3V to (VCC + 0.3V) Digital Output Voltage to GND ...... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2482C ............................................... 0°C to 70°C LTC2482I ............................................ –40°C to 85°C Storage Temperature Range.................. –65°C to 125°C DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 160°C/W EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB *PIN 1 MAY BE DRIVEN WITH A DIGITAL SIGNAL IN ORDER TO REMAIN PIN COMPATIBLE WITH THE LTC2480/LTC2482 ORDER INFORMATION LEAD FREE FINISH LTC2482CDD#PBF LTC2482IDD#PBF TAPE AND REEL LTC2482CDD#TRPBF LTC2482IDD#TRPBF PART MARKING* LBSQ LBSQ PACKAGE DESCRIPTION 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS (NORMAL SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN l l l l TYP 2 1 0.5 10 MAX 20 5 32 UNITS Bits ppm of VREF ppm of VREF μV nV/°C ppm of VREF ppm of VREF/°C 16 0.1 l 32 0.1 15 ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF μVRMS Output Noise 0.6 2482fb 2 LTC2482 CONVERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection, 50Hz ±2% Input Common Mode Rejection, 60Hz ±2% Input Normal Mode Rejection, 50Hz ±2% Input Normal Mode Rejection, 60Hz ±2% Input Normal Mode Rejection, 50Hz/60Hz ±2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ±2% Power Supply Rejection, 60Hz ±2% CONDITIONS 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) VREF = 2.5V, IN– = IN+ = GND VREF = 2.5V, IN– = IN+ = GND (Note 7) VREF = 2.5V, IN– = IN+ = GND (Note 8) l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 140 140 140 110 110 87 120 140 120 120 120 120 120 TYP MAX UNITS dB dB dB dB dB dB dB dB dB dB ANALOG INPUT AND REFERENCE SYMBOL IN+ IN– FS LSB VIN VREF CS (IN+) CS (IN–) CS (VREF) IDC_LEAK (IN+) IDC_LEAK (IN–) IDC_LEAK (VREF) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage Full Scale of the Differential Input (IN+ – IN–) Least Significant Bit of the Output Code Input Differential Voltage Range (IN+ – IN–) Reference Voltage Range IN+ Sampling Capacitance IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current VREF Leakage Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN GND – 0.3V GND – 0.3V l l l l TYP MAX VCC + 0.3V VCC + 0.3V UNITS V V V 0.5VREF FS/216 –FS 0.1 11 11 11 +FS VCC V V pF pF pF Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, VREF = VCC l l l –10 –10 –100 1 1 1 10 10 100 nA nA nA 2482fb 3 LTC2482 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage; CS, fO Low Level Input Voltage; CS, fO High Level Input Voltage, SCK Low Level Input Voltage, SCK Digital Input Current; CS, fO Digital Input Current, SCK Digital Input Capacitance; CS, fO Digital Input Capacitance, SCK High Level Output Voltage, SDO Low Level Output Voltage, SDO High Level Output Voltage, SCK Low Level Output Voltage, SCK Hi-Z Output Leakage, SDO IO = –800μA IO = 1.6mA IO = –800μA IO = 1.6mA l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V (Note 10) 2.7V ≤ VCC ≤ 5.5V (Note 10) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Note 10) l l l l l l MIN VCC – 0.5 TYP MAX 0.5 UNITS V V V V μA μA pF pF V VCC – 0.5 0.5 –10 –10 10 10 VCC – 0.5 0.4 VCC – 0.5 0.4 –10 10 10 10 V V V μA POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS l MIN 2.7 l l TYP 160 1 MAX 5.5 250 2 UNITS V μA μA Conversion Mode (Note 12) Sleep Mode (Note 12) 2482fb 4 LTC2482 TIMING CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV_1 fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time Simultaneous 50Hz/60Hz External Oscillator Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 10) (Note 10) (Note 10) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 10) l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS (Note 15) l l l l l MIN 10 0.125 0.125 144.1 TYP MAX 4000 100 100 UNITS kHz μs μs ms ms kHz kHz 146.9 41036/fEOSC (in kHz) 38.4 fEOSC/8 149.9 45 125 125 0.61 0.625 192/fEOSC (in kHz) 24/fESCK (in kHz) 0 0 0 50 55 4000 % kHz ns ns 0.64 ms ms ms ns ns ns ns ns ns ns tDOUT_ESCK External SCK 24-Bit Data Output Time t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 CS↓ to SDO Low CS↑ to SDO Hi-Z CS↓ to SCKØ CS↓ to SCK≠ SCK↓ to SDO Valid SDO Hold After SCK↓ SCK Set-Up Before CS↓ SCK Hold After CS↓ 200 200 200 200 (Note 10) (Note 10) (Note 5) 15 50 50 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified: VREFCM = VREF/2, FS = 0.5VREF VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2 Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: fEOSC = 256kHz ±2% (external oscillator). Note 8: fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz rejection (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as digital input and the driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital output and the output clock signal during the data output is fISCK. Note 11: The external oscillator is connected to the fO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: Refer to Applications Information section for performance vs data rate graphs. 2482fb 5 LTC2482 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) 1 0 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V fO = GND INL (ppm OF VREF) –45°C 25°C 3 2 1 0 –1 –2 –3 –1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V fO = GND INL (ppm OF VREF) –45°C, 25°C, 90°C 3 2 1 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V fO = GND –45°C, 25°C, 90°C 0 –1 –2 –3 –1.25 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2482 G02 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2482 G03 2482 G01 Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C VCC = 5V VREF = 5V VIN(CM) = 2.5V fO = GND 12 8 85°C TUE (ppm OF VREF) 25°C 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 5V VIN(CM) = 1.25V fO = GND 12 85°C 25°C TUE (ppm OF VREF) 4 0 –4 –8 8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V fO = GND 25°C 85°C –45°C –45°C 2 2.5 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2482 G05 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2482 G06 2482 G04 Offset Error vs VIN(CM) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2482 G07 Offset Error vs Temperature 0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND fO = GND OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) VCC = 5V VREF = 5V VIN = 0V TA = 25°C –0.1 –0.2 –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2482 G08 2482fb 6 LTC2482 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs VCC 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 2.7 REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C OFFSET ERROR (ppm OF VREF) 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 0 1 2 3 VREF (V) 4 5 2482 G10 2482 G09 On-Chip Oscillator Frequency vs Temperature 310 310 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND fO = GND 308 FREQUENCY (kHz) FREQUENCY (kHz) 90 308 306 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND fO = GND 0 15 30 45 60 TEMPERATURE (°C) 75 304 302 302 300 –45 –30 –15 300 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2482 G12 2482 G11 PSRR vs Frequency at VCC 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 0 10 VCC = 4.1V DC VREF = 2.5V IN+ = GND IN– = GND fO = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M PSRR vs Frequency at VCC VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND fO = GND TA = 25°C 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2482 G14 2482 G13 2482fb 7 LTC2482 TYPICAL PERFORMANCE CHARACTERISTICS PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 fO = GND TA = 25°C –60 –80 –100 –120 –140 30600 0 200 Conversion Current vs Temperature fO = GND CS = GND SCK = NC SDO = NC VCC = 5V 160 VCC = 2.7V CONVERSION CURRENT (μA) 30800 2482 G15 180 REJECTION (dB) 140 120 30650 30750 FREQUENCY AT VCC (Hz) 30700 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2482 G16 Sleep Mode Current vs Temperature 2.0 fO = GND 1.8 CS = VCC SCK = NC 1.6 SDO = NC 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 VCC = 2.7V VCC = 5V 500 450 SUPPLY CURRENT (μA) Conversion Current vs Data Output Rate VREF = VCC IN+ = GND IN– = GND 400 SCK = NC SDO = NC 350 CS = GND fO = EXT OSC TA = 25°C 300 250 200 150 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 G18 SLEEP MODE CURRENT (μA) VCC = 5V VCC = 3V 2482 G17 2482fb 8 LTC2482 PIN FUNCTIONS GND (Pin 1): Ground. This pin should be tied to ground; however, in order to remain pin compatible with the LTC2480/LTC2484, this pin may be driven high or low. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1μF tantalum capacitor in parallel with 0.1μF ceramic capacitor as close to the part as possible. VREF (Pin 3): Positive Reference Input. The voltage on this pin can have any value between 0.1V and VCC. The negative reference input is GND (Pin 8). IN+ (Pin 4), IN– (Pin 5): Differential Analog Inputs. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5 • VREF to 0.5 • VREF . Outside this input range the converter produces unique overrange and underrange output codes. CS (Pin 6): Active Low Chip Select. A low on this pin enables the digital input/output and wakes up the ADC. Following each conversion the ADC automatically enters the sleep mode and remains in this low power state as long as CS is high. A low-to-high transition on CS during the data output transfer aborts the data transfer and starts a new conversion. SDO (Pin 7): Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select, CS, is high (CS = VCC), the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS low. GND (Pin 8): Ground. Shared pin for analog ground, digital ground and reference ground. Should be connected directly to a ground plane through a minimum impedance. SCK (Pin 9): Bidirectional Digital Clock Pin. In internal serial clock operation mode, SCK is used as the digital output for the internal serial interface clock during the data output period. In external serial clock operation mode, SCK is used as the digital input for the external serial interface clock during the data output period. A weak internal pull-up is automatically activated in internal serial clock operation mode. The serial clock operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. fO (Pin 10): Frequency Control Pin. Digital input that controls the conversion clock. When fO is connected to GND the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the fO pin with an external clock in order to change the output rate or the digital filter rejection null. Exposed Pad (Pin 11): This pin is ground and should be soldered to the PCB, GND plane. For prototyping purposes this pin may remain floating. 2482fb 9 LTC2482 FUNCTIONAL BLOCK DIAGRAM 3 VREF 2 VCC GND 1 SCK SERIAL INTERFACE SD0 CS 9 7 6 4 IN+ IN+ REF+ 3RD ORDER ADC 5 IN– IN– REF– AUTOCALIBRATION AND CONTROL fO 10 GND 8 INTERNAL OSCILLATOR 2482 FD TEST CIRCUITS VCC 1.69k SDO 1.69k CLOAD = 20pF SDO CLOAD = 20pF Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 2482 TC01 Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2482 TC02 2482fb 10 LTC2482 TIMING DIAGRAMS Timing Diagram Using Internal SCK CS t1 SDO t3 SCK SLEEP DATA OUT CONVERSION 2482 TD1 t2 tKQMIN tKQMAX Timing Diagram Using External SCK CS t1 SDO t5 SCK SLEEP t6 t4 DATA OUT CONVERSION 2482 TD2 t2 tKQMIN tKQMAX APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2482 is a low power, delta-sigma analog-to-digital converter with an easy-to-use 3-wire serial interface and automatic differential input current cancellation. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2482 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced SLEEP CONVERT FALSE CS = LOW AND SCK TRUE DATA OUTPUT 2482 F01 Figure 1. LTC2482 State Transition Diagram 2482fb 11 LTC2482 APPLICATIONS INFORMATION by two orders of magnitude. The part remains in the sleep state as long as CS is high. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled low, the device exits the low power mode and enters the data output state. If CS is pulled high before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains low after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data output state and start a new conversion. The conversion result is shifted out of the device through the serial data output pin (SDO) on the falling edge of the serial clock (SCK) (see Figure 2). Through timing control of the CS and SCK pins, the LTC2482 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Easy Drive Input Current Cancellation The LTC2482 combines a high precision delta-sigma ADC with an automatic differential input current cancellation front end. A proprietary front-end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2482 without CS BIT 23 SDO Hi-Z EOC BIT 22 DMY BIT 21 SIG BIT 20 MSB BIT 19 B16 CONVERSION RESULT BIT 18 BIT 4 LSB BIT 3 BIT 2 BIT 1 BIT 0 external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Input Current Cancellation section). This unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to VCC. Furthermore, the cancellation does not interfere with the transparent offset and full-scale autocalibration and the absolute accuracy (full scale + offset + linearity) is maintained with external RC networks. Output Data Format The LTC2482 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 17 bits are the conversion result, MSB first. The remaining 4 bits are always zero. Bit 21 and Bit 20 together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS). In applications where a processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the LTC2482’s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and output “1” for the extra clock cycles. Furthermore, CS may be pulled high prior to outputting all 24 bits, aborting the data out transfer and initiating a new conversion. SCK SLEEP DATA OUTPUT CONVERSION 2482 F02 Figure 2. Output Data Timing 2482fb 12 LTC2482 APPLICATIONS INFORMATION Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is low. This bit is high during the conversion and goes low when the conversion is complete. Bit 22 (second output bit) is a dummy bit (DMY) and is always low. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is high. If VIN is 1nF at Both IN+ and IN–. Can Take Large Source Resistance. Unbalanced Resistance Results in an Offset Which Can be Calibrated Varying CIN > 1nF at Both IN+ Minimize IN+ and IN– –. Can Take Large Capacitors and Avoid VIN(CM) – VREF(CM) and IN Source Resistance with Large Source Impedance ( 1nF at Both IN+ Constant VIN(CM) – VREF(CM) and IN–. Can Take Large Source Resistance with Negligible Error 23 LTC2482 APPLICATIONS INFORMATION RSOURCE CPAR 20pF LTC2482 RSOURCE CPAR 20pF IN+ CIN VINCM + 0.5VIN IN– CIN 2482 F11 VINCM – 0.5VIN Figure 11. An RC Network at IN+ and IN– +FS ERROR (ppm) VCC = 5V 60 VREF = 5V VIN+ = 3.75V – 40 VIN = 1.25V fO = GND 20 TA = 25°C 0 –20 –40 –60 –80 1 10 80 The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1μV typical and 10μV maximum offset voltage. Reference Current CIN = 0pF CIN = 100pF CIN = 1nF, 0.1μF, 1μF 1k RSOURCE (Ω) 100 10k 100k 2482 F12 Figure 12. +FS Error vs RSOURCE at IN+ and IN– –FS ERROR (ppm) VCC = 5V 60 VREF = 5V VIN+ = 1.25V – 40 VIN = 3.75V fO = GND 20 TA = 25°C 0 –20 –40 –60 –80 1 10 80 In a similar fashion, the LTC2482 samples the differential reference pins VREF+ and GND transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations. For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. CIN = 1nF, 0.1μF, 1μF CIN = 100pF CIN = 0pF 1k RSOURCE (Ω) 100 10k 100k 2482 F13 Figure 13. –FS Error vs RSOURCE at IN+ and IN– Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same. Using internal oscillator (50Hz/60Hz rejection), the differential reference 2482fb 24 LTC2482 APPLICATIONS INFORMATION resistance is 1.1MΩ and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the VREF pin. When fO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.33 • 1012/ fEOSC Ω and each ohm of source resistance driving the VREF pin will result in 1.53 • 10–6 • fEOSCppm gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the VREF pin and external capacitance connected to that pin are shown in Figures 14-17. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL 90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 –10 0 10 1k 100 RSOURCE (Ω) 10k 100k 2482 F14 is caused by the input dependent terms –VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference pin current as expressed in Figure 10. When using internal oscillator with 50Hz/60Hz rejection, every 100Ω of reference source resistance translates into about 0.61ppm additional INL error. When fO is driven by an external oscillator with a frequency fEOSC, every 100Ω of source resistance driving VREF translates into about 1.99 • 10–6 • fEOSCppm additional INL error. Figure 18 shows the typical INL error due to the source resistance driving the VREF pin when large CREF values are used. The user is advised to minimize the source impedance driving the VREF pin. 10 0 –10 –FS ERROR (ppm) –20 –30 –40 –50 VCC = 5V –60 VREF = 5V V + = 1.25V –70 VIN– = 3.75V IN –80 fO = GND TA = 25°C –90 10 0 CREF = 0.01μF CREF = 0.001μF CREF = 100pF CREF = 0pF VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V fO = GND TA = 25°C CREF = 0.01μF CREF = 0.001μF CREF = 100pF CREF = 0pF 1k 100 RSOURCE (Ω) 10k 100k 2482 F15 Figure 14. +FS Error vs RSOURCE at VREF (Small CREF) 500 Figure 15. –FS Error vs RSOURCE at VREF (Small CREF) 0 400 +FS ERROR (ppm) 300 CREF = 0.1μF –FS ERROR (ppm) VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V fO = GND TA = 25°C CREF = 1μF, 10μF –100 CREF = 0.01μF –200 CREF = 1μF, 10μF –300 VCC = 5V VREF = 5V VIN+ = 1.25V VIN– = 3.75V fO = GND TA = 25°C 0 200 600 400 RSOURCE (Ω) CREF = 0.1μF 200 CREF = 0.01μF 100 –400 0 0 200 600 400 RSOURCE (Ω) 800 1000 2482 F16 –500 800 1000 2482 F17 Figure 16. +FS Error vs RSOURCE at VREF (Large CREF) Figure 17. –FS Error vs RSOURCE at VREF (Large CREF) 2482fb 25 LTC2482 APPLICATIONS INFORMATION 10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10μF 2 0 –2 –4 –6 –8 –10 –0.5 –0.3 0.1 –0.1 VIN/VREF (V) 0.3 0.5 2482 F18 Output Data Rate R = 1k R = 500Ω R = 100Ω When using its internal oscillator, the LTC2482 produces 6.8ps with a notch frequency of 55Hz, for simultaneous 50Hz/60Hz rejection. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (fO connected to an external oscillator), the LTC2482 output data rate can be increased as desired. The duration of the conversion phase is 41036/fEOSC. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2482’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2482 typical performance can be inferred from Figures 12, 13, 14 and 15 in which the horizontal axis is scaled by 307200/fEOSC. Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive 2482fb Figure 18. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1μF In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (VREFCM – VINCM) and a 5V reference, each Ohm of reference source resistance introduces an extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error which is 0.067ppm when using the internal oscillator (50Hz/60Hz rejection). If an external clock is used, the corresponding extra gain error is 0.22 • 10–6 • fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by VREF+ and GND, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05μV typical and 0.5μV maximum full-scale error. 26 INL (ppm OF VREF) LTC2482 APPLICATIONS INFORMATION 50 40 30 TA = 85°C 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F19 OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V fO = EXT CLOCK 3500 3000 2500 VIN(CM) = VREF(CM) VCC = VREF = 5V fO = EXT CLOCK TA = 85°C 2000 1500 1000 500 0 TA = 25°C 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F20 Figure 19. Offset Error vs Output Data Rate and Temperature 0 –500 –FS ERROR (ppm OF VREF) Figure 20. +FS Error vs Output Data Rate and Temperature 22 RESOLUTION (BITS) –1000 TA = 25°C TA = 85°C VIN(CM) = VREF(CM) VCC = VREF = 5V 20 fO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 18 16 TA = 25°C –1500 –2000 –2500 –3000 –3500 VIN(CM) = VREF(CM) VCC = VREF = 5V fO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F21 14 TA = 85°C 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F22 Figure 21. –FS Error vs Output Data Rate and Temperature Figure 22. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 22 20 OFFSET ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VIN = 0V 15 fO = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V RESOLUTION (BITS) VIN(CM) = VREF(CM) VIN = 0V – 20 REF = GND fO = EXT CLOCK TA = 25°C 18 RES = LOG 2 (VREF/INLMAX) 16 VCC = VREF = 5V VCC = 5V, VREF = 2.5V 14 12 10 –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F23 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F24 Figure 23. Offset Error vs Output Data Rate and Reference Voltage Figure 24. Resolution (INLMAX) ≤ 2LSB vs Output Data Rate and Reference Voltage 2482fb 27 LTC2482 APPLICATIONS INFORMATION degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 19 to 24. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2482 input bandwidth. When the internal oscillator is used the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the fO pin, the 3dB input bandwidth is 10.7 • 10–6 • fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2482 input bandwidth is shown in Figure 25. When an external oscillator of frequency fEOSC is used, the shape of the LTC2482 input bandwidth can be derived from Figure 25 in which the horizontal axis is scaled by fEOSC/307200. 0 INPUT SIGNAL ATTENUATION (dB) –1 –2 –3 –4 –5 –6 The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nV√Hz for an infinite bandwidth source and 64nV√Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2482, the ADC input referred system noise calculation can be simplified by Figure 26. The noise of an amplifier driving the LTC2482 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 26, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni • √freqi. The total system noise 100 INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) 1 3 0 4 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2482 F25 10 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2482 F26 Figure 25. Input Signal Bandwidth Using the Internal Oscillator Figure 26. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source 2482fb 28 LTC2482 APPLICATIONS INFORMATION (referred to the LTC2482 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2482 internal noise, the noise of the IN+ driving amplifier and the noise of the IN– driving amplifier. If the fO pin is driven by an external oscillator of frequency fEOSC, Figure 26 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 26 plot accuracy begins to decrease, but at the same time the LTC2482 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2482 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2482 allows external lowpass filtering without degrading the DC performance of the device. The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2482’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048 • fOUTMAX where fN is the notch frequency and fOUTMAX 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN fN = fEOSC/5120 is the maximum output data rate. In the internal oscillator mode with 50Hz/60Hz rejection, fS = 13960Hz. In the external oscillator mode, fS = fEOSC/20. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 27 (rejection near DC) and Figure 28 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figure 29. Typical measured values of the normal mode rejection of the LTC2482 operating with an internal oscillator (50Hz/60Hz rejection) is shown in Figure 29. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2482. If passive RC components are placed in front of the LTC2482, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2482 allows external RC networks without significant degradation in DC performance. Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2482 third 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2482 F28 2482 F27 Figure 27. Input Normal Mode Rejection at DC Figure 28. Input Normal Mode Rejection at fS = 256fN 2482fb 29 LTC2482 APPLICATIONS INFORMATION 0 NORMAL MODE REJECTION (dB) –20 –40 –60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C Fundamentally, an oversampled data converter (ΔΣ ADC) directly connected to a long cable and a low precision RC network leads to many problems greatly limiting the accuracy of the system. These include transmission line effects, noise and DC settling errors. The sampling network of ΔΣ ADCs injects high frequency current spikes into the cable. The resulting voltage spikes are reflected through the long wire and result in excessive noise and reduced accuracy. This problem is solved by placing a bypass capacitor across the input to the ADC. This capacitor serves as a charge reservoir for the ADC’s sampling network and reduces the voltage spikes by the ratio of internal sampling capacitor to external bypass capacitor. A 1μF bypass capacitor reduces the voltage spikes generated by the sampling network by a factor of 50,000 (1V spikes are reduced to 18μV) and is sufficient to achieve data sheet specified noise and accuracy. The addition the large external bypass capacitor results in input settling errors. Typical 24-bit high resolution delta sigma ADCs sample at time intervals on the order of 10μs. In order to fully settle with a 1μF bypass capacitor, the source impedance must be lower than 1Ω. Source impedances greater than 1Ω result in offset and full-scale errors due to the accumulation of charge settling errors over the complete conversion cycle. Easy Drive technology automatically removes the differential component of this error. The remaining common mode error is reduced to a fixed offset as a function of the external resistor matching seen at the plus and minus input of the ADC. In this extreme case, 1k external resistors with 1% matching result in a 3.5μV offset while the linearity and noise are unaffected. The signal path contains a 100 meter wire connected to a low voltage source in a very noisy environment. Line frequency noise is rejected by the on-chip digital filter and guaranteed by the high accuracy on-chip oscillator. High frequency noise is rejected by the external lowpass filter formed by the input bypass capacitor and external resistors. 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2482 F29 Figure 29. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and the LTC2482 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2482 has a full-scale differential input range of 5V peak-to-peak. Remote Sensing with Easy Drive Input Current Cancellation One problem faced by designers of high performance data acquisition systems is achieving data sheet specified performance in a real world environment. One advantage delta sigma type ADCs offer over the alternatives is on-chip digital filtering (noise suppression). The disadvantage (solved by Easy Drive technology) is the drive requirements inherent in delta sigma ADC architectures. In order to demonstrate the full potential of the Easy Drive technology, a practical test case was characterized (see Figure 30). Precise measurements of offset, noise and linearity were measured under extreme test conditions. A remote sensor was digitized through 100 meters of cable applied to an RC network with low accuracy 1% resistors. A remote sensor voltage was swept from 0 to 2.5 with less than 1LSB linearity error (see Figure 31). Noise levels of 650nV RMS and offsets below 5μV were measured (see Figure 32). 2482fb 30 LTC2482 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ± 0.05 3.50 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 ± 0.10 10 3.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 1.65 ± 0.10 (2 SIDES) (DD) DFN 1103 5 0.200 REF 0.75 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2482fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2482 TYPICAL APPLICATION 5V C8 1μF 100 METERS 1k 1% 1μF VIN– 1k 1% REMOTE SENSOR 2482 F30 C7 0.1μF VIN+ REF VCC LTC2482 GND GND CS SCK SDO fO Figure 30. Differential Input Current Cancellation Enables Direct Digitization of Remote Sensors 5 4 3 2 INL (LSB) 1 0 –1 –2 –3 –4 –5 0 0.5 1.5 1 INPUT VOLTAGE (V) 2 2.5 2482 F31 NUMBER OF READINGS (%) INTEGRAL NONLINEARITY THROUGH 100 METERS OF WIRE AND A 1kΩ, 1μF RC NETWORK 12 RMS NOISE = 630nV AVERAGE = –3.5μV 10 2500 CONSECUTIVE READINGS 8 6 4 2 0 –5.25 –4.65 –4.05 –3.45 –2.85 –2.25 –1.65 2482 F32 OUTPUT READING (mV) Figure 31. Current Cancellation Enables Precise DC Measurements Under Extreme Conditions Figure 32. Input Current Cancellation Enables Low Noise/ Low Offset Measurements Under Extreme Conditions RELATED PARTS PART NUMBER LTC1050 LT1236A-5 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2411/LTC2411-1 LTC2413 LTC2415/ LTC2415-1 LTC2414/LTC2418 LTC2420 LTC2430/LTC2431 LTC2435/LTC2435-1 LTC2440 LTC2480 LTC2484 DESCRIPTION Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference 24-Bit, No Latency ΔΣ ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ΔΣ ADCs in MSOP 4-/8-Channel, 24-Bit, No Latency ΔΣ ADCs with Differential Inputs 24-Bit, No Latency ΔΣ ADC with Differential Inputs 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP 24-Bit, No Latency ΔΣ ADC with Differential Inputs 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate 8-/16-Channel 24-Bit, No Latency ΔΣ ADCs 20-Bit, No Latency ΔΣ ADC in SO-8 20-Bit, No Latency ΔΣ ADCs with Differential Inputs 20-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate High Speed, Low Noise 24-Bit ΔΣ ADC 24-Bit, No Latency ΔΣ ADC with Temperature Sensor COMMENTS No External Components 5μV Offset, 1.6μVP-P Noise 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.8μVRMS Noise, 2ppm INL 1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 2.8μV Noise, SSOP-16/MSOP Package 3ppm INL, Simultaneous 50Hz/60Hz Rejection 3.5kHz Output Rate, 200mV Noise, 24.6 ENOBs Pin Compatible with LTC2482 2482fb LT 1107 REV B • PRINTED IN USA 16-Bit, No Latency ΔΣ ADC with PGA and Temperature Sensor Pin Compatible with LTC2482 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005