LTC2483CDD

LTC2483 16-Bit ∆Σ ADC with Easy Drive Input Current Cancellation and I2C Interface FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise, Independent of VREF GND to VCC Input/Reference Common Mode Range 2-Wire I2C Interface Simultaneous 50Hz/60Hz Rejection 2ppm (0.25LSB) INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error No Latency: Digital Filter Settles in a Single Cycle Single Supply 2.7V to 5.5V Operation Internal Oscillator Six Addresses Available and One Global Address for Synchronization Available in a Tiny (3mm × 3mm) 10-Lead DFN Package The LTC®2483 combines a 16-bit plus sign No Latency ∆ΣTM analog-to-digital converter with patented Easy DriveTM technology and I2C digital interface. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and input signals, with rail-torail input range to be directly digitized while maintaining exceptional DC accuracy. The LTC2483 allows a wide common mode input range (0V to VCC) independent of the reference voltage. The reference can be as low as 100mV or can be tied directly to VCC. The noise level is 600nV RMS independent of VREF. This allows direct digitization of low level signals with 16bit accuracy. The LTC2483 includes an on-chip trimmed oscillator, eliminating the need for external crystals or oscillators and provides 87dB rejection of 50Hz and 60Hz line frequency noise. Absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending. APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Strain Gauge Transducers Instrumentation Industrial Process Control DVMs and Meters TYPICAL APPLICATIO VCC +FS Error vs RSOURCE at IN+ and IN– 80 VCC = 5V 60 VREF = 5V VIN+ = 3.75V – 40 VIN = 1.25V FO = GND 20 TA = 25°C CIN = 1µF 0 –20 –40 –60 –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2483 TA02 10k SENSE 10k IDIFF = 0 1µ F VIN+ REF+ LTC2483 VCC SCL SDA CA0/F0 CA1 2483 TA01 2-WIRE I2C INTERFACE 6 ADDRESSES VIN– GND REF– +FS ERROR (ppm) 1µF U 2483f U U 1 LTC2483 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW REF+ 1 VCC 2 REF – 3 IN+ 4 IN– 5 11 10 CA0/F0 9 CA1 8 GND 7 SDA 6 SCL Supply Voltage (VCC) to GND ...................... – 0.3V to 6V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2483C ................................................... 0°C to 70°C LTC2483I ................................................ – 40°C to 85°C Storage Temperature Range ................ – 65°C to 125°C DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/ W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2483CDD LTC2483IDD DD PART MARKING* LBSR Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN ● ● ● ● TYP 2 1 0.5 10 MAX 10 2.5 25 UNITS Bits ppm of VREF ppm of VREF µV nV/°C ppm of VREF ppm of VREF/°C 0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF 2.5V ≤ VREF ≤ VCC , IN– = 0.75VREF, IN+ = 0.25VREF 16 0.1 ● 25 0.1 15 15 15 0.6 ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF µVRMS 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 12) Output Noise 2 U 2483f W U U WW W LTC2483 CO VERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz ± 2% Input Common Mode Rejection 60Hz ± 2% Input Normal Mode Rejection 50Hz ± 2% Input Normal Mode Rejection 60Hz ± 2% Input Normal Mode Rejection 50Hz/60Hz ± 2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ± 2% Power Supply Rejection, 60Hz ± 2% CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN ● ● ● ● ● ● ● A ALOG I PUT A D REFERE CE The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL IN+ IN– FS LSB VIN VREF CS (IN+) CS (IN–) CS (VREF) IDC_LEAK (IN+) IDC_LEAK (IN–) IDC_LEAK (VREF) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage Full Scale of the Differential Input (IN+ – IN–) ● ● ● ● Least Significant Bit of the Output Code Input Differential Voltage Range (IN+ – IN–) Reference Voltage Range (REF+ IN+ Sampling Capacitance IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current DC Leakage Current Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, VREF = VCC – REF–) IN– DC Leakage Current REF+, REF– U U U U TYP MAX UNITS dB dB dB 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 140 140 140 110 110 87 120 140 120 120 120 120 120 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) VREF = 2.5V, IN– = IN+ = GND VREF VREF = 2.5V, IN– = 2.5V, IN– = IN+ = IN+ = GND (Notes 7, 9) = GND (Notes 8, 9) dB dB dB dB dB dB dB U CONDITIONS MIN GND – 0.3V GND – 0.3V 0.5VREF FS/216 –FS 0.1 TYP MAX VCC + 0.3V VCC + 0.3V UNITS V V V +FS VCC 11 11 11 V V pF pF pF ● ● ● –10 –10 –100 1 1 1 10 10 100 nA nA nA 2483f 3 LTC2483 I2C DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL VIL(CA1) VIH(CA0/F0,CA1) RINH RINL RINF II VHYS VOL tOF tSP IIN CI CB CCAX VIH(EXT,OSC) VIL(EXT,OSC) PARAMETER High Level Input Voltage Low Level Input Voltage Low Level Input Voltage for Address Pin High Level Input Voltage for Address Pins Resistance from CA0/F0,CA1 to VCC to Set Chip Address Bit to 1 Resistance from CA1 to GND to Set Chip Address Bit to 0 Resistance from CA0/F0, CA1 to VCC or GND to Set Chip Address Bit to Float Digital Input Current Hysteresis of Schmitt Trigger Inputs Low Level Output Voltage SDA Output Fall Time from VIHMIN to VILMAX Input Spike Suppression Input Leakage Capacitance for Each I/O Pin Capacitance Load for Each Bus Line External Capacitive Load on Chip Address Pins (CA0/F0,CA1) for Valid Float High Level CA0/F0 External Oscillator Low Level CA0/F0 External Oscillator 2.7V ≤ VCC < 5.5V 2.7V ≤ VCC < 5.5V 0.1VCC ≤ VIN ≤ VCC (Note 5) I = 3mA ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● ● ● ● ● ● ● ● POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● 4 U UW U MIN 0.7VCC TYP MAX 0.3VCC 0.05VCC UNITS V V V V kΩ kΩ MΩ 0.95VCC 10 10 2 –10 0.05VCC 0.4 20+0.1CB 250 50 1 10 400 10 VCC – 0.5V 0.5 10 µA V V ns ns µA pF pF pF V V Bus Load CB 10pF to 400pF (Note 14) ● ● ● ● ● ● ● ● MIN 2.7 ● ● TYP 160 1 MAX 5.5 250 2 UNITS V µA µA Conversion Mode (Note 11) Sleep Mode (Note 11) 2483f LTC2483 TI I G CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15) SYMBOL fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) PARAMETER SCL Clock Frequency Hold Time (Repeated) START Condition LOW Period of the SCL Clock Pin HIGH Period of the SCL Clock Pin Set-Up Time for a Repeated START Condition Data Hold Time Data Set-Up Time Rise Time for Both SDA and SCL Signals Fall Time for Both SDA and SCL Signals Set-Up Time for STOP Condition (Note 14) (Note 14) CONDITIONS ● ● ● ● ● ● ● ● ● ● I2C TI I G CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF; VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz fEOSC = 256kHz ±2% (external oscillator). UW UW MIN 10 0.125 0.125 144.1 TYP MAX 4000 100 100 UNITS kHz µs µs ms ms Simultaneous 50Hz/60Hz External Oscillator (Note 10) ● ● 146.9 149.9 41036/fEOSC MIN 0 0.6 1.3 0.6 0.6 0 100 20+0.1CB 20+0.1CB 0.6 TYP MAX 400 UNITS kHz µs µs µs µs 0.9 300 300 µs ns ns ns µs Note 8: 60Hz fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The external oscillator is connected to the CA0/F0 pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation. Note 14: CB = capacitance of one bus line in pF. Note 15: All values refer to VIH(MIN) and VIL(MAX) levels. 2483f 5 LTC2483 TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 VCC = 5V VREF = 5V VIN(CM) = 2.5V –45°C INL (ppm OF VREF) 1 0 INL (ppm OF VREF) INL (ppm OF VREF) 25°C 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) VCC = 5V VREF = 5V VIN(CM) = 2.5V 25°C 85°C TUE (ppm OF VREF) TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C Noise Histogram (6.8sps) 10,000 CONSECUTIVE READINGS 12 RMS = 0.60µV VCC = 5V AVERAGE = –0.69µV VREF = 5V 10 VIN = 0V TA = 25°C 8 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (µV) 1.2 1.8 14 14 NUMBER OF READINGS (%) NUMBER OF READINGS (%) ADC READING (µV) 6 UW 2 2483 G01 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) 3 2 1 0 –1 –2 –3 –1.25 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V 3 2 1 0 –1 –2 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V –45°C, 25°C, 90°C –45°C, 25°C, 90°C 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2483 G02 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2483 G03 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) 12 8 4 0 –4 –8 –12 –1.25 –45°C VCC = 5V VREF = 2.5V VIN(CM) = 1.25V 25°C 12 85°C 8 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V 25°C 85°C –45°C 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2483 G05 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2483 G06 2483 G04 Noise Histogram (7.5sps) 10,000 CONSECUTIVE READINGS RMS = 0.59µV 12 VCC = 2.7V AVERAGE = –0.19µV VREF = 2.5V 10 VIN = 0V TA = 25°C 8 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (µV) 1.2 1.8 Long-Term ADC Readings 5 VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V 4 TA = 25°C, RMS NOISE = 0.60µV 3 2 1 0 –1 –2 –3 –4 –5 0 10 30 40 20 TIME (HOURS) 50 60 2483 G09 2483 G07 2483 G08 2483f LTC2483 TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Input Differential Voltage 1.0 0.9 VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C RMS NOISE (µV) RMS NOISE (ppm OF VREF) 0.8 0.7 0.6 0.5 0.4 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) RMS NOISE (µV) RMS Noise vs VCC 1.0 0.9 RMS NOISE (µV) 0.8 0.7 0.6 0.5 0.4 2.7 VREF = 2.5V VIN = 0V VIN(CM) = GND TA = 25°C RMS NOISE (µV) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 OFFSET ERROR (ppm OF VREF) 3.1 3.5 3.9 4.3 VCC (V) 4.7 Offset Error vs Temperature 0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) 0.1 0 –0.1 –0.2 OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) UW 2483 G10 RMS Noise vs VIN(CM) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND TA = 25°C 1.0 0.9 0.8 0.7 0.6 0.5 RMS Noise vs Temperature (TA) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND 2.5 –1 0 1 2 3 4 5 6 2483 G11 0.4 –45 –30 –15 VIN(CM) (V) 0 15 30 45 60 TEMPERATURE (°C) 75 90 2483 G12 RMS Noise vs VREF 0.3 VCC = 5V VIN = 0V VIN(CM) = GND TA = 25°C Offset Error vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25°C 0.2 0.1 0 –0.1 –0.2 –0.3 5.1 5.5 0 1 2 3 VREF (V) 4 5 2483 G14 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2483 G15 2483 G13 Offset Error vs VCC 0.3 0.2 REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C –0.1 –0.2 75 90 –0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 –0.3 0 1 2 3 VREF (V) 4 5 2483.G18 2483 G16 2483 G17 2483f 7 LTC2483 TYPICAL PERFOR A CE CHARACTERISTICS On-Chip Oscillator Frequency vs Temperature 310 308 FREQUENCY (kHz) FREQUENCY (kHz) 306 306 REJECTION (dB) 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND 0 15 30 45 60 TEMPERATURE (°C) 75 90 302 300 –45 –30 –15 PSRR vs Frequency at VCC 0 –20 –40 VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND TA = 25°C CONVERSION CURRENT (µA) REJECTION (dB) REJECTION (dB) –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2483 G24 Sleep Mode Current vs Temperature 2.0 1.8 SLEEP MODE CURRENT (µA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 VCC = 2.7V VCC = 5V SUPPLY CURRENT (µA) 8 UW 2483 G21 On-Chip Oscillator Frequency vs VCC 310 VREF = 2.5V VIN = 0V VIN(CM) = GND 0 –20 –40 –60 –80 –100 PSRR vs Frequency at VCC VCC = 4.1V DC VREF = 2.5V IN+ = GND IN– = GND TA = 25°C 308 304 302 –120 –140 300 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2483 G22 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2483 G23 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 TA = 25°C –60 –80 –100 –120 –140 30600 0 Conversion Current vs Temperature 200 180 VCC = 5V 160 VCC = 2.7V 140 120 30650 30750 FREQUENCY AT VCC (Hz) 30700 30800 2483 G25 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2483 G26 Conversion Current vs Output Data Rate 500 450 400 350 300 250 200 150 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 G28 VREF = VCC IN+ = GND IN– = GND CA0/F0 = EXT OSC TA = 25°C VCC = 5V VCC = 3V 2483 G27 2483f LTC2483 PI FU CTIO S REF+ (Pin 1), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is more positive than the reference negative input, REF –, by at least 0.1V. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. IN+ (Pin 4), IN– (Pin 5): D ifferential Analog Input. The voltage on these pins can have any value between GND – 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5 • VREF to 0.5 • VREF. Outside this input range the converter produces unique overrange and underrange output codes. SCL (Pin 6): Serial Clock Pin of the I2C Interface. The LTC2483 can only act as a slave and the SCL pin only accepts external serial clock. Data is shifted out the SDA pin on the falling edges of the SCL clock. SDA (Pin 7): Serial Data Output Line of the I2C Interface. In the transmitter mode (Read), the conversion result is output through the SDA pin. It is an open-drain N-channel driver and therefore an external pull-up resistor or current source to VCC is needed. GND (Pin 8): Ground. Connect this pin to a ground plane through a low impedance connection. CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is configured as a three state (LOW, HIGH, or Floating) address control bit for the device I2C address. CA0/F0 (Pin 10): Chip Address Control Pin/External Clock Input Pin. When no transition is detected on the CA0/F0 pin, it is a two state (HIGH or Floating) address control bit for the device I2C address. When the pin is driven by an external clock signal with a frequency fEOSC of at least 10kHz, the converter uses this signal as its system clock and the fundamental digital filter rejection null is located at a frequency fEOSC/5120 and sets the Chip Address CA0 internally to a HIGH. U U U 2483f 9 LTC2483 FU CTIO AL BLOCK DIAGRA 1 REF+ 4 IN+ IN+ REF+ 3RD ORDER ∆Σ ADC 5 IN – IN – REF – AUTOCALIBRATION AND CONTROL REF– 3 10 W 2 VCC SCL I 2C SERIAL INTERFACE 6 U U SDA CA1 CA0/F0 7 9 10 GND 8 INTERNAL OSCILLATOR 2483 FB 2483f LTC2483 APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2483 is a low power, ∆Σ analog-to-digital converter with an I2C interface. After power on reset, its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 1). POWER ON RESET CONVERSION SLEEP NO ACKNOWLEDGE YES DATA OUTPUT NO STOP OR READ 24-BITS YES 2483 F01 Figure 1. LTC2483 State Transition Diagram Initially, the LTC2483 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as it is not addressed for a read operation. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a read request. Once the U LTC2483 is addressed for a read operation, the device begins outputting the conversion result under control of the serial clock (SCL). There is no latency in the conversion result. The data output is 24 bits long and contains a 16-bit plus sign conversion result. This result is shifted out on the SDA pin under the control of the SCL. Data is updated on the falling edges of SCL allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated at the conclusion of a data read operation (read out all 24 bits). I2C INTERFACE The LTC2483 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the bus wires LOW and they never drive the bus HIGH. The bus wires are externally connected to a positive supply voltage via a currentsource or pull-up resistor. When the bus is free, both lines are HIGH. Data on the I2C-bus can be transferred at rates of up to 100kbit/s in the Standard-mode and up to 400kbit/s in the Fast-mode. Each device on the I2C bus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At the same time any device addressed is considered a slave. The LTC2483 can only be addressed as a slave. Once addressed, it can transmit the last conversion result. Therefore the serial clock line SCL is an input only and the data line SDA is bidirectional (data out/address in). The device supports the Standard-mode and the Fast-mode for data transfer speeds up to 400kbit/s. Figure 2 shows the definition of timing for Fast/Standard-mode devices on the I2C-bus. 2483f W UU 11 LTC2483 APPLICATIO S I FOR ATIO The START and STOP Conditions A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free again a certain time after the STOP condition. START and STOP conditions are always generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical to the START (S). SDA tf SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S 2483 F02 tLOW tr tSU;DAT Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus 12 U Data Transferring After the START condition, the I2C bus is busy and data transfer is set between a master and a slave. Data is transferred over I2C in groups of nine bits (one byte) followed by an acknowledge bit, therefore each group takes nine SCL cycles. The transmitter releases the SDA line during the acknowledge clock pulse and the receiver issues an Acknowledge (ACK) by pulling SDA LOW or leaves SDA HIGH to indicate a Not Acknowledge (NAK) condition. Change of data state can only happen while SCL is LOW. tr tHD;STA tSP tr tBUF 2483f W UU LTC2483 APPLICATIO S I FOR ATIO LTC2483 Data Format After a START condition, the master sends a 7-bit address followed by a R/W bit. The bit R/W is 1 for a Read request and 0 for a Write request. If the 7-bit address agrees with an LTC2483’s address, that device is selected. When the device is in the conversion state, it does not accept the request and issues a Not-Acknowledge (NAK) by leaving SDA HIGH. A write operation will also generate an NAK signal. If the conversion is complete, it issues an acknowledge (ACK) by pulling SDA LOW. The output register contains the last conversion result. After each conversion is completed, the device automatically enters the sleep state where the supply current is reduced to 1µA. When the LTC2483 is addressed for a Read operation, it acknowledges (by pulling SDA LOW) and acts as a transmitter. The master and receiver can read up to three bytes from the LTC2483. After a complete Read operation (3 bytes), the output register is emptied, a new conversion is initiated, and a following Read request in the same output phase will be NAKed. The LTC2483 output data stream is 24 bits long, shifted out on the falling edges of SCL. The first bit is the conversion result sign bit (SIG), see Tables 1 and 2. This bit is HIGH if VIN ≥ 0. It is LOW if VIN 1nF at Both IN+ and IN–. Can Take Large Source Resistance with Negligible Error UNBALANCED INPUT RESISTANCES CEXT > 1nF at Both IN+ and IN–. Can Take Large Source Resistance. Unbalanced Resistance Results in an Offset Which Can be Calibrated Minimize IN+ and IN– Capacitors and Avoid Large Source Impedance (< 5k Recommended) Varying VIN(CM) – VREF(CM) CEXT > 1nF at Both IN+ and IN–. Can Take Large Source Resistance with Negligible Error W UU The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current and offset will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1µV typical and 10µV maximum offset voltage. Reference Current In a similar fashion, the LTC2483 samples the differential reference pins REF+ and REF– transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in two distinct situations. For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain 2483f 19 LTC2483 APPLICATIO S I FOR ATIO performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 1nF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. In the following discussion, it is assumed the input and reference common mode are the same. For the internal oscillator, the related difference resistance is 1.1MΩ and 90 80 70 +FS ERROR (ppm) –FS ERROR (ppm) 60 50 40 30 20 10 0 –10 0 VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V TA = 25°C CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF 10 1k 100 RSOURCE (Ω) 10k 100k 2483 F11 Figure 11. +FS Error vs RSOURCE at REF+ or REF– (Small CREF) 500 400 +FS ERROR (ppm) 300 CREF = 0.1µF –FS ERROR (ppm) VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V TA = 25°C CREF = 1µF, 10µF –100 200 CREF = 0.01µF 100 0 0 200 600 400 RSOURCE (Ω) 800 1000 2483 F13 Figure 13. +FS Error vs RSOURCE at REF+ or REF– (Large CREF) 20 U the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the REF+ and REF– pins. When CA0/F0 is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.30 • 1012/fEOSC Ω and each ohm of source resistance driving the REF+ or REF– pins will result in 1.67 • 10–6 • fEOSCppm gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the REF+ or REF– pins and external capacitance connected to that pin are shown in Figures 11-14. 10 0 –10 –20 –30 –40 –50 –60 VCC = 5V VREF = 5V –70 V + = 1.25V IN – –80 VIN = 3.75V TA = 25°C –90 10 0 CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF W UU 1k 100 RSOURCE (Ω) 10k 100k 2483 F12 Figure 12. –FS Error vs RSOURCE at REF+ or REF– (Small CREF) 0 CREF = 0.01µF –200 CREF = 1µF, 10µF –300 –400 –500 VCC = 5V VREF = 5V VIN+ = 1.25V VIN– = 3.75V TA = 25°C 0 CREF = 0.1µF 200 600 400 RSOURCE (Ω) 800 1000 2483 F14 Figure 14. –FS Error vs RSOURCE at REF+ or REF– (Large C REF) 2483f LTC2483 APPLICATIO S I FOR ATIO In addition to this gain error, the converter INL performance is degraded by the reference source impedance. The INL is caused by the input dependent terms –VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference pin current as expressed in Figure 7. When using internal oscillator, every 100Ω of reference source resistance translates into about 0.61ppm additional INL error. When CA0/F0 is driven by an external oscillator with a frequency fEOSC, every 100Ω of source resistance driving REF+ or REF– translates into about 2.18 • 10–6 • fEOSCppm additional INL error. Figure 15 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The user is advised to minimize the source impedance driving the REF+ and REF– pins. In applications where the reference and input common mode voltages are different, extra errors are introduced. For every 1V of the reference and input common mode voltage difference (VREFCM – VINCM) and a 5V reference, each Ohm of reference source resistance introduces an extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error, which is 0.067ppm when using internal oscillator. If an 10 INL (ppm OF VREF) VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10µF 2 0 –2 –4 –6 –8 –10 – 0.5 – 0.3 0.1 – 0.1 VIN/VREF (V) Figure 15. INL vs DIFFERENTIAL Input Voltage and Reference Source Resistance for CREF > 1µF U external clock is used, the corresponding extra gain error is 0.24 • 10–6 • fEOSCppm. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF+ and REF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maximum full-scale error. R = 1k R = 500Ω R = 100Ω 0.3 0.5 2483 F15 W UU 2483f 21 LTC2483 APPLICATIO S I FOR ATIO Output Data Rate When using its internal oscillator, the LTC2483 produces up to 6.82sps with simultaneous 50Hz/60Hz rejection. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (CA0/F0 connected to an external oscillator), the LTC2483 output data rate can be increased as desired. The duration of the conversion phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter notch is set at 60Hz. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum 50 40 30 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F16 OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V CA0/F0 = EXT CLOCK TA = 85°C Figure 16. Offset Error vs Output Data Rate and Temperature 0 –500 –FS ERROR (ppm OF VREF) TA = 25°C TA = 85°C –2000 –1500 RESOLUTION (BITS) –1000 –2500 –3000 VIN(CM) = VREF(CM) VCC = VREF = 5V CA0/F0 = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F18 –3500 Figure 18. –FS Error vs Output Data Rate and Temperature 22 U output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2483’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. 3500 3000 2500 TA = 85°C 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F17 W UU VIN(CM) = VREF(CM) VCC = VREF = 5V CA0/F0 = EXT CLOCK TA = 25°C Figure 17. +FS Error vs Output Data Rate and Temperature 24 TA = 25°C 22 TA = 85°C 20 18 16 14 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V CA0/F0 = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) Figure 19. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature 2483f 2483 F19 LTC2483 APPLICATIO S I FOR ATIO Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2483 typical performance can be inferred from Figures 9, 10, 11 and 12 in which the horizontal axis is scaled by 307200/fEOSC. 22 20 RESOLUTION (BITS) 18 TA = 85°C 16 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V CA0/F0 = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F20 OFFSET ERROR (ppm OF VREF) TA = 25°C Figure 20. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 24 VCC = VREF = 5V 22 RESOLUTION (BITS) RESOLUTION (BITS) 20 18 16 VCC = 5V, VREF = 2.5V 18 VCC = VREF = 5V 16 14 VCC = 5V, VREF = 2.5V 14 VIN(CM) = VREF(CM) VIN = 0V CA0/F0 = EXT CLOCK 12 T = 25°C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F22 Figure 22. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage U Third, an increase in the frequency of the external oscillator above 1MHz (a more than 3+ increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 16 to 23. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. 20 VIN(CM) = VREF(CM) VIN = 0V 15 CA0/F0 = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F21 W UU Figure 21. Offset Error vs Output Data Rate and Reference Voltage 22 20 VIN(CM) = VREF(CM) VIN = 0V 12 CA0/F0 = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2483 F23 Figure 23. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage 2483f 23 LTC2483 APPLICATIO S I FOR ATIO Input Bandwidth The combined effect of the internal SINC4 digital filter and of the analog and digital autocalibration circuits determines the LTC2483 input bandwidth. When the internal oscillator is used, the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the CA0/F0 pin, the 3dB input bandwidth is 11.8 • 10–6 • fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2483 input bandwidth is shown in Figure 24. When an external oscillator of frequency fEOSC is used, the shape of the LTC2483 input bandwidth can be derived from Figure 24, in which the horizontal axis is scaled by f EOSC/279.2kHz. The conversion noise (600nVRMS typical for VREF = 5V) can be modeled by a white noise source connected to a noise free converter. The noise spectral density is 47nV√Hz for an infinite bandwidth source and 64nV√Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2483, the ADC input referred system noise calculation can be simplified by Figure 25. The noise of an amplifier driving the LTC2483 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 25, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these 24 U effects can be calculated as N = ni • √freqi. The total system noise (referred to the LTC2483 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2483 internal noise, the noise of the IN+ driving amplifier and the noise of the IN– driving amplifier. If the CA0/F0 pin is driven by an external oscillator of frequency fEOSC, Figure 25 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 25 plot accuracy begins to decrease, but at the same time the LTC2483 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2483 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature of the LTC2483 allows external lowpass filtering without degrading the DC performance of the device. The SINC4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2483’s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048 • fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode, fS = 13960Hz. In the external oscillator mode, fS = fEOSC/20. The performance of the normal mode rejection is shown in Figures 26 and 27. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 28 (rejection near DC) and Figure 29 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. 2483f W UU LTC2483 APPLICATIO S I FOR ATIO 0 INPUT SIGNAL ATTENUATION (dB) INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) –1 –2 –3 –4 –5 –6 60Hz fEOSC = 307.2kHz 50Hz fEOSC = 256kHz INTERNAL OSCILLATOR 1 3 4 0 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2483 F24 Figure 24. Input Signal Using the Internal Oscillator 0 INPUT NORMAL MODE REJECTION (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2483 F26 INPUT NORMAL MODE REJECTION (dB) –10 Figure 26. Input Normal Mode Rejection, External Oscillator (fEOSC = 256kHz) 50Hz Rejection 0 fN = fEOSC/5120 INPUT NORMAL MODE REJECTION (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN INPUT NORMAL MODE REJECTION (dB) –10 2483 F28 Figure 28. Input Normal Mode Rejection at DC U 100 10 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2483 F25 W UU Figure 25. Input Refered Noise Equivalent Bandwidth of an Input Connected White Noise Source 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2483 F27 Figure 27. Input Normal Mode Rejection at DC (Internal Oscillator) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2483 F29 Figure 29. Input Normal Mode Rejection at fs = 256fN 2483f 25 LTC2483 APPLICATIO S I FOR ATIO The user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by Figures 30, 31 and 32. Typical measured values of the normal mode rejection of the LTC2483 operating with an external oscillator and a 60Hz notch setting are shown in Figure 30 superimposed over the theoretical calculated curve. Similarly, the measured normal rejection of the LTC2483 for 50Hz rejection (fEOSC = 256kHz) and 50Hz/ 60Hz rejection (internal oscillator) are shown in Figures 31 and 32. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2483. If passive RC components are placed in front of the LTC2483, the input dynamic current should be considered (see Input Current section). In this case, the differential input current cancellation feature of the LTC2483 allows external RC networks without significant degradation in DC performance. Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2483 third order modu- 26 U lator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed on volt level perturbations and the LTC2483 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2483 has a full-scale differential input range of 5V peak-to-peak. Figures 33 and 34 show measurement results for the LTC2483 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peak-topeak (full scale) input signal. In Figure 33, the LTC2483 uses the external oscillator with the notch set at 60Hz and in Figure 34 it uses the external oscillator with the notch set at 50Hz. It is clear that the LTC2483 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. 2483f W UU LTC2483 APPLICATIO S I FOR ATIO 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 NORMAL MODE REJECTION (dB) MEASURED DATA CALCULATED DATA 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2483 F30 Figure 30. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (60Hz Notch fEOSC = 307.2kHz) 0 NORMAL MODE REJECTION (dB) NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 Figure 32. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (Internal Oscillator) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2483 F34 Figure 34. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch fEOSC = 256kHz) U VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2483 F31 W UU Figure 31. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch fEOSC = 256kHz) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 – 60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VINCM = 2.5V TA = 25°C 200 220 2483 F32 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2483 F33 Figure 33. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch fEOSC = 307.2kHz) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) 2483f 27 LTC2483 APPLICATIO S I FOR ATIO /* LTC248X.h Processor setup and Lots of useful defines for configuring the LTC2481, LTC2483, and LTC2485. */ #include // Device #use delay(clock=6000000) // 6MHz clock //#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT // Configuration fuses #rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config. #use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port #include “PCM73A.h” // Various defines #include “lcd.c” // LCD driver functions #define READ 0x01 #define WRITE 0x00 #define LTC248XADDR 0b01001000 // bitwise OR with address for read or write // The one and only LTC248X in this circuit, // with both address lines floating. // Useful defines for the LTC2481 and LTC2485 - OR them together to make the // 8 bit config word. // These do NOT apply to the LTC2483. // Select gain - 1 to 256 (also depends on speed setting) // Does NOT apply to LTC2485. #define GAIN1 0b00000000 // G = 1 (SPD = 0), G = 1 #define GAIN2 0b00100000 // G = 4 (SPD = 0), G = 2 #define GAIN3 0b01000000 // G = 8 (SPD = 0), G = 4 #define GAIN4 0b01100000 // G = 16 (SPD = 0), G = 8 #define GAIN5 0b10000000 // G = 32 (SPD = 0), G = 16 #define GAIN6 0b10100000 // G = 64 (SPD = 0), G = 32 #define GAIN7 0b11000000 // G = 128 (SPD = 0), G = 64 #define GAIN8 0b11100000 // G = 256 (SPD = 0), G = 128 // Select ADC source - differential input or PTAT circuit #define VIN 0b00000000 #define PTAT 0b00001000 // Select rejection frequency - 50, 55, or 60Hz #define R50 0b00000010 #define R55 0b00000000 #define R60 0b00000100 // Select speed mode #define SLOW 0b00000000 // slow output rate with autozero #define FAST 0b00000001 // fast output rate with no autozero 28 U (SPD (SPD (SPD (SPD (SPD (SPD (SPD (SPD = = = = = = = = 1) 1) 1) 1) 1) 1) 1) 1) 2483f W UU LTC2483 APPLICATIO S I FOR ATIO /* LTC2483.c Basic voltmeter test program for LTC2483 Reads LTC2483, converts result to volts, and prints voltage to a 2 line by 16 character LCD display. Mark Thoren Linear Technonlgy Corporation June 23, 2005 Written for CCS PCM compiler, Version 3.182 */ #include “LTC248X.h” /*** read_LTC2483() ************************************************************ This is the funciton that actually does all the work of talking to the LTC2483. Arguments: Returns: addr - device address zero if conversion is in progress, 32 bit signed integer with lower 8 bits clear, 24 bit LTC2483 output word in the upper 24 bits. Data is left-justified for compatibility with the 24 bit LTC2485. the i2c_xxxx() functions do the following: void i2c_start(void): generate an i2c start or repeat start condition void i2c_stop(void): generate an i2c stop condition char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device These functions are very compiler specific, and can use either a hardware i2c port or software emulation of an i2c port. This example uses software emulation. A good starting point when porting to other processors is to write your own i2c functions. Note that each processor has its own way of configuring the i2c port, and different compilers may or may not have built-in functions for the i2c port. When in doubt, you can always write a “bit bang” function for troubleshooting purposes. The “fourbytes” structure allows byte access to the 32 bit return value: struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; *******************************************************************************/ signed int32 read_LTC2483(char addr) { struct fourbytes // Define structure of four consecutive bytes { // To allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // The make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; 2483f U W UU 29 LTC2483 APPLICATIO S I FOR ATIO union { signed int32 bits32; struct fourbytes by; } adc_code; // // // // // adc_code.bits32 adc_code.by.te0 adc_code.by.te1 adc_code.by.te2 adc_code.by.te3 // Start communication with LTC2483: i2c_start(); if(i2c_write(addr | READ))// If no acknowledge, return zero { i2c_stop(); return 0; } adc_code.by.te3 = i2c_read(); adc_code.by.te2 = i2c_read(); adc_code.by.te1 = i2c_read(); adc_code.by.te0 = 0; i2c_stop(); return adc_code.bits32; } // End of read_LTC2483() /*** initialize() ************************************************************** Basic hardware initialization of controller and LCD, send Hello message to LCD *******************************************************************************/ void initialize(void) { // General initialization stuff. setup_adc_ports(NO_ANALOGS); setup_adc(ADC_OFF); setup_counters(RTCC_INTERNAL,RTCC_DIV_1); setup_timer_1(T1_DISABLED); setup_timer_2(T2_DISABLED,0,1); // This is the important part - configuring the SPI port setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock CKP = 0; // Set up clock edges - clock idles low, data changes on CKE = 1; // falling edges, valid on rising edges. lcd_init(); delay_ms(6); printf(lcd_putc, “Hello!”); delay_ms(500); } // End of initialize() // Initialize LCD // Obligatory hello message // for half a second /*** main() ******************************************************************** Main program initializes microcontroller registers, then reads the LTC2483 repeatedly *******************************************************************************/ void main() { signed int32 x; // Integer result from LTC2481 float voltage; // Variable for floating point math int16 timeout; initialize(); // Hardware initialization while(1) { delay_ms(1); // Pace the main loop to something more than 1 ms // This is a basic error detection scheme. The LTC2483 will never take more than // 149.9ms to complete a conversion in the 55Hz // rejection mode. 2483f 30 U all 32 bits byte 0 byte 1 byte 2 byte 3 W UU LTC2483 APPLICATIO S I FOR ATIO // If read_LTC2483() does not return non-zero within this time period, something // is wrong, such as an incorrect i2c address or bus conflict. if((x = read_LTC2483(LTC248XADDR)) != 0) { // No timeout, everything is okay timeout = 0; // reset timer x ^= 0x80000000; // Invert MSB, result is 2’s complement voltage = (float) x; // convert to float voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31 lcd_putc(‘\f’); // Clear screen lcd_gotoxy(1,1); // Goto home position printf(lcd_putc, “V %01.4f”, voltage); // Display voltage } else { ++timeout; } if(timeout > 200) { timeout = 200; // Prevent rollover lcd_gotoxy(1,1); printf(lcd_putc, “ERROR - TIMEOUT”); delay_ms(500); } } // End of main loop } // End of main() PACKAGE DESCRIPTIO DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 6 0.675 ± 0.05 0.38 ± 0.10 10 3.50 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD10) DFN 1103 U W UU 5 0.200 REF 0.75 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SID 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2483f 31 LTC2483 TYPICAL APPLICATIO ISOTHERMAL R2 2k 32 REF VCC LTC2483 TYPE K THERMOCOUPLE JACK (OMEGA MPJ-K-F) 5 5V 1 R6 5k 2 3 RELATED PARTS PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency ∆Σ ADC in SO-8 24-Bit, No Latency ∆Σ ADC with Differential Inputs COMMENTS 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.05% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.8µVRMS Noise, 2ppm INL 1.45µVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs Pin Compatible with LTC2482/LTC2484 Pin Compatible with LTC2483/LTC2485 Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2480/LTC2482 Pin Compatible with LTC2481/LTC2483 2483f LTC2411/LTC2411-1 24-Bit, No Latency ∆Σ ADCs with Differential Inputs in MSOP LTC2413 LTC2415/ LTC2415-1 LTC2414/LTC2418 LTC2440 LTC2480 LTC2481 LTC2482 LTC2484 LTC2485 24-Bit, No Latency ∆Σ ADC with Differential Inputs 24-Bit, No Latency ∆Σ ADCs with 15Hz Output Rate 8-/16-Channel 24-Bit, No Latency ∆Σ ADCs High Speed, Low Noise 24-Bit ∆Σ ADC 16-Bit ∆Σ ADC with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit ∆Σ ADC with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit ∆Σ ADC with Easy Drive Inputs 24-Bit ∆Σ ADC with Easy Drive Inputs 24-Bit ∆Σ ADC with Easy Drive Inputs, I2C Interface and Temperature Sensor 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com U 5V PIC16F73 C8 1µF C7 0.1µF 1.7k 1.7k 18 17 16 15 14 13 12 11 28 27 26 25 24 23 22 21 7 6 5 4 3 2 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 RA5 RA4 RA3 RA2 RA1 RA0 VDD 20 C6 0.1µF Y1 6MHz 5V 4 IN+ SCL SDA 6 7 OSC1 OSC2 9 10 R1 1 10k D1 BAT54 5V IN– 10 CA1 GND REF– CAO/FO 9 5V D7 D6 2 × 16 CHARACTER D5 LCD DISPLAY D4 (OPTREX DMC162488 EN OR SIMILAR) RW CONTRAST GND D0 D1 D2 D3 RS VCC 5V CALIBRATE 2 1 R3 10k R4 10k R5 10k 8 3 MCLR VSS VSS 2483 F35 9 19 DOWN UP Figure 35. Voltage Measurement Circuit LT/LWI/TP 0805 500 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005